Clock Tree Optimization through Selective Airgap Insertion Daijoon Hyun, Wachirawit Ponghiran, and Youngsoo Shin School of Electrical Engineering, KAIST, Daejeon 34141, Korea Abstract—Airgap refers to a void inserted in some inter metal dielectric (IMD). It brings about reduced permittivity and corresponding reduction in coupling capacitance. We address a problem of selective airgap insertion in clock wires to reduce clock skew as well as power consumption. This is performed after conventional clock tree construction and optimization, so the reduction in clock skew due to inserted airgap is additional benefit. The problem is formulated as linear programming (LP); more practical heuristic algorithm is also proposed, whose performance is comparable to LP. Experiments demonstrate 17.0% reduction in clock skew and 11.1% reduction in clock power, on average of a few test circuits in 28-nm technology.

Cu

IMD

Metal layer (a)

(c)

(b) Airgap

(d)

1. Introduction

Figure 1. Airgap process steps: (a) formation of standard Cu interconnect, (b) selective IMD etch, (c) conformal dielectric deposition for sidewall passivation, and (d) non-conformal dielectric deposition and airgap formation.

Airgap refers to air being used together with some material (i.e. material has intentional void) as IMD instead of pure material. It brings about reduced IMD permittivity from 2.5 (porous SiOC:H) to below 2.0 (airgap with SiOC:H) [1], [2] and corresponding reduction in coupling capacitance. It has been reported that total wire capacitance including coupling component is reduced by 17% to 28% [3], [4]. Airgap has been employed in high-performance microprocessor design to reduce interconnect delay by 17% [5]. Another application of airgap is to reduce floating gate interference by 20% in NAND flash memory [6]. Airgap is formed following the steps shown in Figure 1 [4], [7]. After the formation of standard Cu interconnect (Figure 1(a)), IMD between some metal lines is removed with an additional mask (Figure 1(b)). Two consecutive depositions are applied (Figure 1(c) and (d)): conformal dielectric deposition using atomic layer deposition (ALD) for sidewall passivation of metal lines (this is to prevent Cu being oxidized by air), and non-conformal dielectric deposition using chemical vapor deposition (CVD) to pinch off the top portion of dielectric layer. Airgap insertion is an expensive process. It is associated with more than 10 additional process steps [7]. Therefore, the number of layers that employ airgap, called airgap layers, is usually limited to two or one [3], [5]. From designers perspective, however, airgap is very convenient option. It can be selectively assigned where coupling capacitance should be reduced; it does not affect chip area and routing resources. Systematic assignment of airgap, however, has not been explored yet.

978-1-5090-5404-6/17/$31.00 ©2017 IEEE

1.1. Motivational Example Consider a simple clock tree shown in Figure 2(a). Assume that each wire segment is shielded, i.e. it is sandwiched between two adjacent wires that are grounded (even though they are not explicitly shown in the figure); this is common practice in high frequency design to prevent clock noise [8]. Each buffer is associated with two delay numbers x(y); x is initial buffer delay and y is expected delay if airgap is inserted at all wire segments attached to buffers output. Assume that there are three data paths, from clock sink s1 to s2, from s1 to s3, and from s3 to s4; corresponding three clock skew values are shown in the figure. • •

If airgap is inserted at all clock wires as shown in Figure 2(b), clock skew may or may not decrease. Selective insertion of airgap (such that maximum clock skew is reduced as much as possible) is demonstrated in Figure 2(c), which is the problem we address. Note that airgap is only partially inserted at the output of buffer a, and so its new delay is between the two delay numbers, 3(1), shown in Figure 2(a); we will consider this flexibility of airgap insertion in our problem. We also address a problem, in which we try to minimize clock power consumption in addition to minimizing clock skew.

The remainder of this paper is organized as follows. Section 2 introduces the constraints in airgap insertion and

203

18th Int'l Symposium on Quality Electronic Design

2

3(2)

4(3)

3(1)

2(1)

2(1)

4(3)

s1

1

s2

s3

3

3

Airgap

2

4(3) s4 Clock skew

1

1 s1

3

1

3 2

3

s2

s3

2

2

3 2

s4

2

a s1

3 1

2 s2

s3

1

3 s4

1

Data path (a)

(c)

(b)

Figure 2. (a) Initial clock tree; each buffer is associated with two delay numbers x(y), x is initial buffer delay and y is the expected delay if airgap is inserted in the wire attached to buffer output, (b) clock tree and its skew after airgap is inserted in all wires, and (c) clock tree and its skew after selective airgap insertion.

then defines the problem. LP formulation to airgap insertion is presented in Section 3; a heuristic algorithm is also developed. Experimental results are presented in Section 4, in which we discuss the effectiveness of airgap insertion method in reducing clock skew and clock power consumption. Conclusions are drawn in Section 5.

2. Preliminaries

Airgap

Shield

Shield

Airgap Wire segment

Via space rule

Metal segment

No airgap

2.1. Constraints in Airgap Insertion There are two constraints in airgap insertion, which we take into account in our problem formulation. •

•

Via spacing rule: Airgap is not allowed near vias as illustrated in Figure 3(a). This is to prevent IMD break-down during high stress process such as chemical mechanical planarization [9]. A typical space adopted is one metal pitch. Minimum metal spacing rule: Airgap cannot be inserted between metal wires that are widely spaced since non-conformal dielectric deposition (see Figure 1(d)) is not possible [4]. A typical rule requires adjacent wires to be spaced in minimum metal pitch as shown in Figure 3(b).

These constraints are considered when identifying the amount of airgap (and thus corresponding reduction in coupling capacitance) that can be inserted for each wire segment. For a given layout, we extract the information of each wire segment, such as metal layer, width, length, space to adjacent wires, and via connections. Maximum lengths that satisfy minimum metal spacing rule and via spacing rule on the left, lk,le f t , and right, lk,right , are calculated for wire segment k. Upper bound of capacitance reduction ∆Ckmax for the segment is then obtained by ∆Ckmax = ε λ

lk,le f t + lk,right , 2

(1)

(a)

(b)

Figure 3. Airgap insertion rules: (a) via spacing rule and (b) minimum metal spacing rule.

where ε is a unit capacitance of wire and λ is a process dependent value corresponding to a capacitance change percentage from airgap insertion.

2.2. Problem Formulation Let a clock tree be given after clock tree synthesis (CTS) and clock tree optimization. All or some clock wires are shielded as we have mentioned in conjunction with Figure 2. For each clock wire segment k on airgap layer, the maximum amount of airgap that can be inserted is identified, which allows us to associate k with maximum potential change in its capacitance, ∆Ck . The problem of airgap insertion is to determine the value of ∆Ck with objective of minimizing the maximum clock skew. Additional goal we consider is to maximize the sum of ∆Ck so that clock power consumption is reduced as much as possible.

τ1

τ2

∆d

d1-2 clk

n2

n1

wa wb

n3

n4 u

n5

n6 v

∆d = αg ∆τ + βg ∆C L

∆τ

∆C L ∆C

max L

βg

(a)

clk

n3

n4

u

n5

n6

v

αg

0

Figure 5. Gate delay change is modeled as a linear equation of change in input transition time and change in load capacitance, where ∆τ max and ∆CLmax are set to empirical values.

n2

n1

∆τ

max

LCA(u,v) (b)

as shown in Figure 5. Change in output transition time at output pin v can be described similarly by

Figure 4. (a) A clock tree and (b) its timing graph.

∆τ(v) = ατ ∆τ(pv ) + βτ ∆CL (v),

3. Airgap Insertion

∆CL (v) =

∑

∀v ∈ Vo

∆Ck ,

(5) (6)

k∈w(v)

3.1. LP Formulation 3.1.1. Problem Modeling. A clock tree is modeled by a timing graph G = (Vi ∪ Vo , Eg ∪ Ew , {d }, {τ }), where Vo is a set of vertices representing output pin of buffers and clock source, and Vi is a set of vertices representing input pin of buffers and clock sinks. Each directed edge in Eg and Ew respectively denotes an input-to-output timing path of buffer and wire connection. An example timing graph is shown in Figure 4, where vertices in Vo and Vi are depicted by white and gray circles, and edges in Eg and Ew are represented by dashed and solid arrows. Each vertex in Vi and Vo is associated with transition time τ at input and output pin of a buffer, respectively. Each edge in Eg and Ew is associated with delay number. The delay d of each edge e after airgap insertion is obtained by d(e) = dnom (e) − ∆d(e), ∀e ∈ Eg ∪ Ew

(2)

where dnom is an initial delay of edge before airgap insertion, and ∆d is a delay change from airgap insertion. For gate delay, ∆d is modeled as a linear equation of change in an input transition time ∆τ and change in load capacitance ∆CL [10]. ∆d(e) = αg ∆τ(he ) + βg ∆CL (e), ∆CL (e) =

∑

∆Ck ,

∀e ∈ Eg ,

(3) (4)

k∈w(e)

where he is a vertex connected to edge e and located closer to root, and w(e) represents wire segments correponding to edge e. αg and βg are coefficients of changes in input transition time and load capacitance, which are obtained by fitting (3) to four delay values (black dots at each corner)

where pv denotes a parent node of vertex v. Elmore delay under ramp input is used to model the change in wire delay [11]. ∆d(e) =

∆τ(he ) + ∑ Rk,te ∆Ck , 2 k∈w(e)

∀e ∈ Ew

(7)

where the second term of equation represents Elmore delay change from parent node he to child node te connected by edge e. Rk,te is a resistance of common path from he to te and to k. Transition time change at each vertex in Vi is set to be equal to change in output transition time of fanin buffer [12]. Clock arrival time at sink v is obtained by adding delay values of edges on path p(v) from clock source clk to sink v. In order to account for process variation, we employ two derating factors, ξl > 1.0 and ξe < 1.0; they allow us to compute the late and early clock arrival time: A(v) = ξl

∑

d(e),

(8)

d(e).

(9)

e∈p(v)

a(v) = ξe

∑ e∈p(v)

Clock skew between two leaf nodes u and v is given by S(u, v) = max(A(u) − a(v), A(v) − a(u)) −CPP(u, v), (10) where CPP is an operation to remove common path pessimism. Consider two clock paths from clk to u and from clk to v in the Figure 4. Their common path is from clk to n2 , and branch point of that path, n2 , is denoted by LCA(u, v), least common ancestor between u and v. CPP is now given by CPP(u, v) = A(LCA(u, v)) − a(LCA(u, v)). (11)

Smax ≥ S(u, v),

∀ (u, v) ∈ T

(12)

where T is a set of clock sink pairs with datapath in between. 3.1.2. LP Formulation. Airgap insertion problem is to determine the value of ∆Ck for each wire segment k, which are located on airgap layer. The objective is to minimize the maximum clock skew; we also maximize the sum of ∆Ck so that clock power consumption is reduced as much as possible. We combine the two objectives as a weighted sum for the sake of LP formulation, in which larger weight is assigned to clock skew, the main objective of the problem. Minimize

γs Smax − γ p ∑ ∆Ck k

Subject to : Smax ≥

A(u) − a(v) −CPP(u, v),

∀ (u, v) ∈ T

Smax ≥

a(u) − A(v) −CPP(u, v),

∀ (u, v) ∈ T

CPP(u, v) = A(LCA(u, v)) − a(LCA(u, v)), ∀ (u, v) ∈ T A(v) = ξl

∑

d(e),

∀ v ∈ Vi ∪Vo

d(e),

∀ v ∈ Vi ∪Vo

e∈p(v)

a(v) = ξe

∑ e∈p(v)

d(e) = dnom (e) − ∆d(e),

∀ e ∈ Eg ∪ Ew

∆d(e) = αg ∆τ(he ) + βg ∆CL (e),

∀ e ∈ Eg

∆CL (e) =

∀ e ∈ Eg

∑

∆Ck ,

k∈w(e)

∆τ(v) = ατ ∆τ(pv ) + βτ ∆CL (v),

∀ v ∈ Vo

∆CL (v) =

∀ v ∈ Vo

∑

∆Ck ,

k∈w(v)

∆d(e) =

∆τ(he ) + ∑ Rk,te ∆Ck , 2 k∈w(e)

∀ e ∈ Eg ∀v ∈ Vi

∆τ(v) = ∆τ(pv ), 0 ≤ ∆Ck ≤ ∆Ckmax .

∀k

3.1.3. Pruning Method. For each clock sink pair, we estimate its best and worst clock skew. The best clock skew is obtained by fully inserting airgap to wire segments on a path to clock sink that has larger arrival time. The worst clock skew is obtained similarly by inserting airgap to wire segments on a path to clock sink that has smaller arrival time. This is pessimistic and unrealistic, but provides a confident upper and lower bounds of clock skew. Figure 6

Clock skew (ps)

Maximum clock skew, denoted by Smax , is a quantity that we want to minimize. In linear formulation, we require

Worst case max

S BST

200

Best case

100 0 0

Non-critical pairs

Critical pairs

0.5M 1M # clock sink pair

Figure 6. Clock skew curve of sink pairs in the worst (black) and best (red) scenarios of vga lcd. 76% of sink pairs are idenfied to be non-critical.

shows two curves obtained by plotting sorted clock skews in max denotes maximum clock the best and worst scenarios. SBST skew in best case, and LP cannot optimize maximum clock skew below this value. We define some clock sink pairs as non-critical when they have smaller clock skew in the max . Since the non-critical pairs do not worst case than SBST affect an optimization result, clock skew constraints for them can be removed from LP formulation. This brings about a significant runtime improvement. LP runtime of vga lcd is reduced by 94% after pruning 76% of total clock sink pairs which are non-critical.

3.2. Heuristic Algorithm For a given clock tree, we construct a timing graph similar to LP formulation and employ a pruning method to remove non-critical sink pairs. Amount of airgap at each wire segment is initialized to the largest value to minimize clock power consumption. Over iterations, we identify a sink pair with the worst clock skew, and selectively reduce amount of airgap to improve the skew of that pair. We first find a net to reduce airgap. Among several net candidates which improve the worst clock skew, we choose one that is close to clock source and reduce airgap of wire segments that belong to that net. This as result helps algorithm to select a net which affects less sink pairs by airgap reduction in the latter iterations. For sake of solution quality, the amount of airgap reduction for each iteration is set to a small value (0.25fF in our case). After airgap reduction, clock skews for affected sink pairs are updated and worst clock skew is identified. If, however, the worst clock skew after change is greater than the previous one, we revert the action and mark the selected net so that it is not again selected in the other iterations. The algorithm continues finding net to improve the worst clock skew and terminate when the worst clock skew cannot be furthered improved.

4. Experimental results Experiments are carried out on a set of sequential circuits from ITC and OpenCores benchmarks [13], [14], which are

TABLE 1. R EDUCTION IN CLOCK SKEW AND CLOCK POWER AFTER FULL AIRGAP INSERTION AND AFTER SELECTIVE AIRGAP INSERTION

After CTS Circuits

Full airgap insertion

#FFs #BUFs

b22 mem ctrl usb funct ac97 ctrl b18 b19 des3 perf vga lcd tate paring jpegencode gfx Average

613 1065 1738 2199 2777 5556 8808 17057 31416 38850 48248

Skew (ps) 86.0 77.0 101.0 98.0 144.0 165.0 183.0 232.0 314.0 342.0 279.0

70 109 171 217 326 662 885 1972 4227 5332 6320

Power (mW) 0.3 0.5 1.0 2.2 1.1 2.4 6.8 13.0 39.2 29.3 30.2

∆Skew (%) 8.6 5.8 3.9 6.6 11.4 8.8 11.8 10.1 10.5 4.1 9.6 8.3

Skew reduction [ps]

gfx

50

des3_perf b19

30

jpegencode vga_lcd

mem_ctrl

10

ac97_ctrl

0

5

15 20 10 # non-shared stages

Figure 7. Correlation between the worst clock skew reduction and an average number of non-shared stages of critical sink pairs.

listed in Table 1. Each circuit is synthesized by Design Compiler with 28-nm commercial library. IC Compiler is used for placement, routing, and CTS; clock tree optimization is also performed to reduce clock skew as much as possible. We then apply selective airgap insertion to further reduce clock skew as well as clock power. We assume that M5 and M6 are airgap layers and are used for clock routing. Upper bound of capacitance reduction for each wire segment is calculated from circuit layout. Process dependent value for capacitance change from airgap insertion, λ , is set to 23% [4]. Changes in gate delay and transition time from airgap are pre-characterized in look-up tables based on a simulation result with HSPICE. Airgap insertion is performed by LP and heuristic algorithm written in C++. GUROBI is used as an LP solver [15].

4.1. Assessment The results of airgap insertion are listed in Table 1. The columns 3-5 show the number of buffers, maximum clock skew, and clock power after CTS for each circuit. Column

∆Power (%) 11.1 10.6 11.0 11.3 12.0 11.9 11.6 12.4 12.3 12.5 12.4 11.7

Selective airgap insertion LP Heuristic ∆Skew ∆Power ∆Skew ∆Power (%) (%) (%) (%) 16.4 10.2 16.1 10.1 15.6 10.0 15.6 10.0 14.1 10.4 14.1 10.4 16.5 9.2 14.5 9.6 16.3 11.7 16.3 11.7 18.6 11.1 18.5 11.3 21.7 10.9 20.3 11.0 16.5 11.9 15.1 12.2 17.6 11.9 16.0 12.2 16.1 12.2 15.1 12.3 17.7 12.2 15.2 12.3 17.0 11.1 16.1 11.2

6 lists the worst skew reduction percentages after full airgap insertion while column 8 and 10 list the percentages after optimization with proposed LP and heuristic. Average clock skew improvement increases twofold when applying the proposed LP instead of full airgap insertion. This implies that the clock skew improvement does not come from airgap technology alone, but is a result of proper airgap allocation. Similar result is obtained by the proposed heuristic with 0.9% difference. Clock skew improvement, however, varies across circuits as shown in column 8. We observe that the improvement has a strong correlation with an average number of nonshared stages of critical sink pairs. As the number of nonshared stages increases, there is more possibility for airgap to improve clock skew. Figure 7 illustrates this relation for all circuits in Table 1. Clock power after selective airgap insertion is increased by less than 1% from full airgap insertion. This small change is due to clock tree structure in which one wire is shared by many clock sinks; thus, small airgap change in a proper wire can reduce clock skew of many clock sink pairs concurrently. As a result, selective airgap insertion changes small amount of airgap from full airgap insertion, and achieves large clock skew improvement.

4.2. Runtime Computation times for the proposed LP and heuristic are shown in Table 2. Due to an increasing number of sink pairs, LP requires long runtime for large circuits, especially for jpegencode and gfx which takes more than 10 hours for a single run. When applying pruning method to remove noncritical sink pairs, LP runtime can be significantly reduced. tate paring shows 19 times runtime improvement over LP without pruning; nontheless, runtime is still large for circuits like gfx. Runtime of heuristic linearly depends on a circuit size and a number of times that skew information is updated; it is 47 times faster for gfx compared to LP with pruning.

TABLE 2. C OMPARISON OF RUNTIME ( IN SECONDS )

TABLE 3. R EDUCTION OF GLOBAL SKEW VS LOCAL SKEW USING LP FORMULATION

Circuits b22 mem ctrl usb funct ac97 ctrl b18 b19 des3 perf vga lcd tate pairing jpegenconde gfx

LP <1 <1 <1 5 510 2630 120 428 6537 -

Pruning+LP <1 <1 <1 <1 4 87 8 257 340 2884 7955

Heuristic <1 <1 <1 <1 <1 9 3 19 8 60 168

Circuits b22 mem ctrl usb funct ac97 ctrl b18 b19 des3 perf vga lcd tate pairing jpegenconde gfx Average

Skew reduction (%) Global skew Local skew 12.9 16.4 9.1 15.6 4.2 14.1 12.2 16.5 11.6 16.3 10.6 18.6 10.6 21.7 11.3 16.5 11.1 17.6 9.4 16.1 13.0 17.7 10.5 17.0

4.3. Global vs Local Clock Skew We have so far considered the clock skew between clock sinks that have data path in between; this is often called a local clock skew. If we ignore data path, clock skew is defined in any pair of clock sinks; this is called a global clock skew. Many studies and practices rely on global rather than local clock skew due to convenience of skew calculation. We try to assess selective airgap insertion in global in addition to local clock skew. We implement one LP with an objective of global clock skew minimization, and second LP for minimizing local clock skew. The results are compared in Table 3, where the reduction ratio in global skew is 10.5% on average, which is 6.5% smaller than that in local skew. usb funct and des3 perf have large difference in skew reduction because clock sinks that have maximum and minimum arrival times do not belong to critical sink pairs. Based on these results, it is reasonable to consider local clock skew in clock skew minimization problem.

References [1]

S. W. King, “Dielectric barrier, etch stop, and metal capping materials for state of the art and beyond metal interconnects,” ECS Journal of Solid State Science and Technology, vol. 4, no. 1, pp. N3029–N3047, 2015.

[2]

L. Wilson, “International technology roadmap for semiconductors (ITRS),” Semiconductor Industry Association, 2013.

[3]

S. Natarajan et al., “A 14nm logic technology featuring 2nd -generation finFET, air-gapped interconnects, self-aligned double patterning and a 0.0588 um2 SRAM cell size,” in Proc. IEEE Electron Devices Meeting, Dec. 2014, pp. 3.7.1–3.7.3.

[4]

H. J. Yoo et al., “Demonstration of a reliable high-performance and yielding air gap interconnect process,” in Proc. Int. Interconnect Technology Conf., Jun. 2010, pp. 1–3.

[5]

K. Fischer, M. Agostinelli, C. Allen, and D. Bahr, “Low-k interconnect stack with multi-layer air gap and tri-metal-insulator-metal capacitors for 14nm high volume manufacturing,” in Proc. Int. Interconnect Technology Conf., May 2015, pp. 5–8.

[6]

J. Hwang, J. Seo, Y. Lee, S. Park, and J. Leem, “A middle-1X nm NAND flash memory cell (M1X-NAND) with highly manufacturable integration technologies,” in Proc. IEEE Electron Devices Meeting, Dec. 2011, pp. 9.1.1–9.1.4.

[7]

L. Xia et al., “Method for forming an air gap in multilevel interconnect structure,” Oct. 2007, US Patent App. 11/869,409.

[8]

R. Kan et al., “The 10th generation 16-core SPARC64 processor for mission critical UNIX server,” IEEE Journal of Solid-State Circuits, vol. 49, no. 1, pp. 32–40, Dec. 2014.

[9]

X. Zhang et al., “Mechanical stability of air-gap interconnects,” in Proc. Future Fab International, Oct. 2008, pp. 81–87.

5. Conclusion We have addressed airgap insertion to reduce clock skew as well as clock power consumption. It has been performed after clock tree is optimized, so its reduction in clock skew is in addition to conventional clock optimization. The problem has been formulated as LP, and more practical heuristic algorithm whose performance is comparable to LP has been proposed. Experiments indicate that selective airgap insertion achieves 17% reduction in clock skew, while current practice of inserting airgap in all wires achieves only 8% reduction; this is achieved without sacrificing the reduction in clock power, both achieve about 11% reduction.

[10] M. C. Kim, J. Hu, and N. Viswanathan, “ICCAD-2014 CAD contest in incremental timing-driven placement and benchmark suite,” in Proc. Int. Conf. on Computer Aided Design, Nov. 2014, pp. 361– 366. [11] A. B. Kahng, K. Masuko, and S. Muddu, “Analytical delay models for VLSI interconnects under ramp input,” in Proc. Int. Conf. on Computer Aided Design, Nov. 1996, pp. 30–36. [12] PrimeTime User Guide, Synopsys, Jun. 2015.

Acknowledgement This work was supported by the National Research Foundation of Korea (NRF) grant funded by the Korea government (MSIP) (No. 2015R1A2A2A01008037).

[13] ITC99. [Online]. Available: benchmarks/bench. html

http://www.cerc.utexas.edu/itc99-

[14] OpenCores. [Online]. Available: http://www.opencores.org [15] Gurobi Optimization, Inc., “Gurobi optimizer reference manual,” 2015. [Online]. Available: http://www.gurobi.com