USO0RE41379E
(19) United States (12) Reissued Patent
(10) Patent Number: US RE41,379 E (45) Date of Reissued Patent: Jun. 15, 2010
Takahashi et al. (54)
LARGE-CAPACITY SEMICONDUCTOR
4,658,377 A
MEMORY WITH IMPROVED LAYOUT FOR SUB-AMPLIFIERS TO INCREASE OPERATIONAL SPEED
(75) Inventors: Tsugio Takahashi, Tsukuba (JP); Goro KitsukaWa, Kamakura (JP); Takesada Akiba, Hachioji (JP); Yasushi KaWase, Tachikawa (JP); Masayuki Nakamura, Ome (JP)
(Continued) FOREIGN PATENT DOCUMENTS JP JP JP JP
(22) Filed:
A-1-245489 2-18784 A-2-18785 2-143982
9/1989 1/1990 1/1990 6/1990
(Continued)
(73) Assignee: Rising Silicon, Inc., Austin, TX (U S)
(21) App1.N0.: 11/759,345
4/1987 McElroy
OTHER PUBLICATIONS
Sugibayashi et al., “A 3(kns 256*Mb DRAM WithA Multi
Jun. 7, 2007
divided Array Structure, ” IEEE Journal of Solid State Cir
cuits, vol. 28, No. 11, Nov. 1993. (pp. 1092*1098).
Related US. Patent Documents
Reissue of:
(64) Patent No.: Issued:
Primary ExamineriVan Thu Nguyen (74) Attorney, Agent, or FirmiMarger Johnson & McCollom, PC.
5,966,341 Oct. 12, 1999
Appl. No.:
08/982,398
Filed:
Dec. 2, 1997
(57)
US. Applications: (63)
Continuation of application No. 11/176,881, ?led on Jul. 8, 2005, now Pat. No. Re. 40,356, which is a continuation of application No. 09/974,962, ?led on Oct. 12, 2001, now Pat. No. Re. 38,944, which is a continuation of application No. 08/779,835, ?led on Jan. 7, 1997, now Pat. No. 5,777,927, which is a continuation of application No. 08/ 574,104, ?led on Dec. 20, 1995, now Pat. No. 5,604,697.
(30)
Foreign Application Priority Data
Dec. 20, 1994
(51)
(JP)
Int. Cl. GIIC 8/00
(52)
........................................... .. 6-334950
(2006.01)
US. Cl. ..................... .. 365/230.03; 365/51; 365/63;
365/189.011; 365/189.02; 365/189.04; 365/230.01 (58)
Field of Classi?cation Search ........... .. 365/230.03,
365/51, 63, 189.01, 189.02, 189.04, 230.01 See application ?le for complete search history. (56) References Cited U.S. PATENT DOCUMENTS 4,590,588 A
ABSTRACT
A semiconductor memory such as a dynamic RAM having memory mats each divided into a plurality of units or sub memory mats. Each sub-memory mat comprises: a memory
array having sub-word lines and sub-bit lines intersecting orthogonally and dynamic memory cells located in lattice fashion at the intersection points between the intersecting sub-word and sub-bit lines; a sub-word line driver including unit sub-word line driving circuits corresponding to the sub word lines; a sense ampli?er including unit ampli?er circuits and column selection switches corresponding to the sub-bit lines; and sub-common I/O lines to which designated sub-bit lines are connected selectively via the column selection switches. The sub-memory mats are arranged in lattice fash ion. Above the sub-memory mats is a layer of: main word
lines and column selection signal lines intersecting orthogonally, the main word lines having a pitch that is an
integer multiple of the pitch of the sub-word lines, the col umn selection signal lines having a pitch that is an integer multiple of the pitch of the sub-bit lines; and main common I/O lines to which designated sub-common I/O lines are con
nected selectively. 3 Claims, 22 Drawing Sheets
5/1986 Itoh et al.
MIMI: MIDM '
US RE41,379 E Page 2
US. PATENT DOCUMENTS 4,939,696 A
7/1990 Katsuo et a1~
5,140,550 A 5,172,335 A 5,262,999 A 5,274,595 5,282,175 5,291,432 5,297,102 5,301,142
8/1992 12/1992 11/1993 12/1993 1/1994 3/1994 3/1994 4/1994
A A A A A
5,386,394 A
*
5,404,338 A 5,406,526 A 5,414,660 A 5,436,910 A
5,448,516 5,448,520 5,471,430 5,590,086 5,604,697
A A A A A
5,734,619 A 5,777,942 A 6,307,217 B1
*
1/1995
Miyaoka et a1. Sasaki et a1. Etoh et 31.
3/1998 Numata et a1. 7/1998 Dosaka et a1. 10/2001 Ikeda et a1.
FOREIGN PATENT DOCUMENTS
Seok et a1. Fujita et a1. Furutani TaniZaki Suzuki et a1.
JP JP JP JP JP
A-2-158995 2-246089 3-154287 A-4-59712 A-5-54634
6/1990 10/1990 7/1991 9/1992 3/1993
Kawahara et a1. ......... .. 365/208
JP
05-062467
3/1993
4/1995 Murai et a1. 4/1995 Sugibayashi et a1. 5/1995 Sugibayashi et a1.
JP JP JP
5-546634 05-226613 5-226613
3/1993 9/1993 9/1993
7/1995
Takeshima et a1. ........ .. 714/718
JP
5-234362
9/1993
Tsukikawa et a1. Shimohigashi et 31. SaWada et a1. Park et a1. Takahashi et a1.
JP JP JP
6-195966 6-196656 6-318391
7/1994 7/1994 11/1994
9/1995 9/1995 11/1995 12/1996 2/1997
* cited by examiner
US. Patent
Jun. 15, 2010
Sheet 2 0f 22
O! O:
MBO
US RE41,379 E
-| -|
MATR
MATL
XD
XD
\ ..
M81 ..../ ‘
MATL
a‘, a’ >- z
% % z>
MATR
PC
(10)
M82
PSUB
/
M83
US. Patent
Jun. 15, 2010
Sheet 8 0f 22
FIG. 8M)
swomiaos A 9 r1 W30T
wiom <1—-——-
40x40
H P1
“1*
N
USWDO
{I SWO
A A / MWBOT M W308
FIG. BIBN
US RE41,379 E
US. Patent
Jun. 15,2010
Sheet 9 or 22
FIG. 9M) MWBOB
<»——---
a DXLOT
—-~
4 0x405
US RE41,379 E
US. Patent
Jun. 15, 2010
Sheet 10 0f 22
'
.
SAP3 SHBLB
PP
s1
s1 1T
SANS HVC PN PE
US RE41,379 E
$101 VCL PCS
Ta ‘ REE! snaaa
SBBT
SBBB
YSAO C
SBOT
ND SBOB
MIOAOT IOAOB
CPPL
EPN4
LB SAP3
SAN3 PEHVC
VCL
3 SHBRB
US. Patent
Jun. 15,2010
Sheet 12 or 22
US RE41,379 E
FIG. 72 SAP3
--
m N/N04
SC.LPSADIPB
VV V
£ M» a CS.L
a C.UP
PDI
3W *
WSnuERU.nuf. L.VWU E
VB /
_ .S
N .LT.
LSLS S B
Mi
FIG. 74 SAP31 SAN3 SAP32
--VCC
SBOT 5808 V0‘ vss
US. Patent
Jun. 15, 2010
Sheet 14 0f 22
US RE41,379 E
(WIRING LAYER M3)
DXl§0,l02,l§lt,l06
MI0l+1*,MIDh2* .
I
CPPlhCPNl.
(WIRING
LAYER M3) YSl+0~YSL63
(WIRING LAYER M3) _
(WIRING LAYER M2)
SI02*,3* SHALBARB SAPI), SANA PC,PCS WElnRElo
(WIRING LAYER M2)
MW30=I=~MW363>I=
(WIRING LAYER M2)
SI00*,1* SH3LB,3RB SAP3,SAN3 PC,PCS WE3,RE3
DXM,l.3,l)5,lI7 MIOh0*,MI023* CPP4,CPNL CPP2,CPN2
US. Patent
Jun. 15, 2010
Sheet 15 0f 22
US RE41,379 E
FIG. 76 MWBOB
MW30T
(M2)
(M2)
L
I
|
I
n
DXIMMB)
FgIQ?ATION REGION
N WELL REGION
DXLZWB) '
DXLMMB)
DXQMMB) VCHlMB 2 FOR WELL
VOLTAGE SUPPLY)
DXL6(M3) DXMAMB) NMOS FORMATION REGION
DXLZH‘IB)
DX40(M3)
SWO, 2,L,6 (M11
