USO0RE42551E
(19) United States (12) Reissued Patent
(10) Patent Number: US RE42,551 E (45) Date of Reissued Patent: Jul. 12, 2011
Dalvi et al. (54)
BLOCK LOCKING APPARATUS FOR FLASH MEMORY
(76) Inventors: Vishram Prakash Dalvi, Folsom, CA
(US); Rodney R. Rozman, Placerville, CA (US); Christopher John Haid, Folsom, CA (US); Jerry Kreifels, El Dorado Hills, CA (US); Joseph Tsang,
5,134,384 A 5,293,424 A 5,325,430 A
7/1992 Kokubun ................. .. 3/1994 Holteyet a1. .. 6/1994
5,392,413 A *
2/1995 Nomuraet a1.
5,394,367 A
2/1995
Downs et a1. ..
5,442,704 A *
8/1995
Holtey
5,469,564 5,509,134 5,513,136 5,521,602 5,544,098
Elk Grove, CA (US); Jeff Evertt, Kirkland, WA (US); Jahanshir J. J avanifard, Sacramento, CA (US); Jeffrey J. Peterson, Folsom, CA (US)
Smyth et a1.
A A A A A
380/23 . . . . . ..
380/4
711/113
. . . . . . . .
365/195 . . . . . ..
711/163
11/1995 4/1996 4/1996 5/1996 8/1996
Junya ........... ..
5,635,940 A *
6/1997
Hickman et a1.
..... .. 342/389
5,640,347 A
6/1997
Lin et a1. .......... ..
.. 395/185.04
5,802,583 A * 6,006,299 A * 6,073,243 A *
(21) Appl.No.: 10/094,056
. . . . . . .
340/1462
..
395/188.01
Fandrich et a1. ............ .. 395/430
Fundrich et a1.
.. 395/18504
Carroll et a1.
. . . . . . . ..
. . . . . .
Matsuo etal.
342/50
.. 371/212
..... .. 711/152 9/1998 Yeageretal. .. 710/108 12/1999 Wang etal. 6/2000 Dalviet a1. ................. .. 713/202
* cited by examiner
(22) Filed:
Mar. 7, 2002 Primary Examiner * Hosuk Song
Related US. Patent Documents
(74) Attorney, Agent, or Firm * Trop, Pruner & Hu, RC.
Reissue of:
(64) Patent No.:
(51)
6,035,401
Issued:
Mar. 7, 2000
(57)
Appl. No.:
08/794,283
Filed:
Feb. 3, 1997
A ?ash memory device including a ?rst memory array, a control circuit coupled to the ?rst memory array, and a second
ABSTRACT
independent memory array coupled to the control circuit. The
Int. Cl. H04L 9/32
?rst memory array includes a plurality of memory blocks
(2006.01)
(52)
US. Cl. .......................................... .. 726/26; 726/27
each having a memory cell. The memory cell may be a non
(58)
Field of Classi?cation Search ........ .. 713/189*194,
volatile ?ash memory cell. The control circuit controls the
713/200, 202; 711/163,104,152,113,142; 342/389; 365/195, 189.07; 710/108; 726/26,
programming, erasing, and reading of the memory cells. The
References Cited
second memory array includes a plurality of block lock-bits each corresponding to one of the plurality of memory blocks. The state of each block lock-bit indicates Whether the memory cell in the corresponding memory block is locked.
U.S. PATENT DOCUMENTS
The second memory array may also include a master lock-bit that indicates Whether the block lock-bits are locked.
726/27, 30 See application ?le for complete search history. (56)
4,589,092 A
5/ 1986
4,897,662 A
l/l990 Lee et a1. .................... .. 343/701
Matick ........................ .. 364/900
18 Claims, 21 Drawing Sheets
144
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US. Patent
Jul. 12, 2011
Sheet 2 0121
EN\\
US RE42,551 E
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US. Patent
Jul. 12, 2011
Sheet 3 0f 21
US RE42,551 E
0.8 T0 1.4V
210 212 4 TO 6V
200 /
10TO13V O————{ I "/200
1
4
FLOATING
200
-8 TO -12v <>——-—‘ \ -/
US. Patent
Jul. 12, 2011
Sheet 4 0121
US RE42,551 E
600
602
WRITE SET BLOCK LOCK-BIT COMMAND TO MEMORY DEVICE
WHITE DATA AND ADDRESS TO MEMORY DEVICE
MASTER LOCK-B 1T SET?
OVERRIDE ENABLED?
SET BLOCK LOCK-BIT
614
SET BLOCK LOCK-BIT UNSUCOESSFUL
FIG. 6
US. Patent
Jul. 12, 2011
US RE42,551 E
Sheet 5 0f 21
702
WRTTE SET BLOCK LOCK-BIT COMMAND TO
DATA LATCH 08M DECODES COMMAND AND INDICATES TO THE wnmz STATE MACHINE (WSM) THE
704
NATURE OF THE COMMAND 706
LOCK-BIT ADDRESS AND LOCK-BIT DATA LATCHES
MASTER LOCK-BIT SET?
YES
722
WSM CAUSES VOLTAGE CONTOL CIRCUIT’ RY TO COUPLE APPROPRiATE PROGRAM VOLTAGES TO FLASH BLOCK LOCK MINI-ARRAY
OVERRIDE ENABLED?
712 /\/ 724
LOCK-BIT DATA PROGRAMMING INTO FLASH BLOCK LOCK MINIAAHRAY
WSM VERIFIES THE PROGRAMMING
UPDATE STATUS REGISTER TO INDICATE 714 FAILURE
I 716
UPDATE STATUS REGISTER
I 718
READ STATUS REGISTER
FAIL
FIG. 7
720
SET LOCK-BIT SUCCESSFUL
SET LOCK-BIT UNSUCCESSFUL
726
US. Patent
Jul. 12, 2011
Sheet 6 0f 21
WSM SENDS MASTER LOCK-BIT ADDRESS TO FLASH BLOCK LOCK MlNi~ARRAY
WSM CAUSES VOLTAGE CONTROL CTRCUITRY TO COUPLE APPROPRTATE READ VOLTAGES TO FLASH BLOCK LOCK MTNl-ARRAY
WSM ENABLES SENSING CIRCUIT
WSM READS THE STATE OF THE MASTER LOCK-BIT
FIG. 8
US RE42,551 E
US. Patent
Jul. 12, 2011
Sheet 7 0f 21
US RE42,551 E
900
WRITE SET MASTER LOCK-BIT CDMMAND TO MEMORY DEVICE
WRITE DATA AND ADDRESS TO MEMORY DEVICE
SET MASTER LOCK—BTT
FIG. 9
US. Patent
Jul. 12, 2011
1002
WRITE SET MASTER LOCK-BIT COMMAND INTO CSM ‘u
US RE42,551 E
Sheet 8 0f 21
V
1004
CSM DECODES COMMAND AND INDICATES TO WSM THE NATURE OF THE COMMAND 1006
MASTER LOCK-BIT ADDRESS AND MASTER
LOCK-BIT DATA LATCHED
1010
WSM CAUSES VOLTAGE CONTOL CIRCUITRY TO COUPLE APPROPRIATE PROGRAM VOLTAGES TO FLASH BLOCK
LOCK MINI-ARRAY MASTER LOCK-BIT DATA PROGRAMMED
1012
UPDATE STATUS REGISTER TO INDICATE 1014 FAILURE
INTO THE FLASH BLOCK LOCK MINI-ARRAY
WSM VERIFIES THE PROGRAMMING
| 1016
UPDATE THE STATUS REGISTER
I 1018
READ STATUS REGISTER
FAIL
1020
SET MASTER LOCK-BIT SUCCESSFUL
FIG. 10
p, 1022
SET MASTER LOCK-BIT UNSUCCESSFUL 1 024
US. Patent
Jul. 12, 2011
Sheet 9 0f 21
US RE42,551 E
1100
1102
WRITE CLEAR BLOCK-LOCK BR'S COMMAND T0 MEMORY DEVICE 1104
WRITE DATA TO THE MEMORY DEVICE
MASTER LOCK-BIT SET?
OVERRiDE ENABLED?
CLEAR LOCK-BITS
CLEAR UNSUCCESFUL 1114
FIG. 11
US. Patent
Jul. 12, 2011
US RE42,551 E
Sheet 10 0f 21
1202
WRIT E CLEAR BLOCK LOCK-BITS COMMAND TO CSM
1204
CSM DECODES COMMAND AND INDICATES TO THE WSM THE NATURE OF THE COMMAND
1206
LOCK-BIT DATA LATCHED
MASTER LOCK-BIT SET’?
I
YES
PRECONDITION
I‘ V 1210
WSM CAUSES VOLTAGE CONTOL CIRCUITRY TO COUPLE APPROPRIATE PROGRAM VOLTAGES TO BLOCK
OVERRI DE ENABLED?
LOCK MINI-ARRAY
LOCK-BITS ARE CLEARED
1212
t V
p/ 1224 UPDATE STATUS
REGISTER TO INDICATE FAILURE 1214
WSM VERIFIES CLEAR
I 1216
UPDATE STATUS REGISTER
I
CLEAR UNSUCCESSFUL
I
1218 READ STATUS REGISTER
1228 FAIL
FIG. 12
CLEAR SUCCESSFUL
US. Patent
Jul. 12, 2011
Sheet 11 0121
US RE42,551 E
1 300
WRITE READ IDENTIFIER CODES COMMAND TO MEMORY DEVICE
SUPPLY ADDRESS OF LOCK-BIT OR MASTER LOCK-BIT
READ LOCK~BIT OR MASTER LOCK-BIT STATUS ON DATA PADS
FIG. 13
US. Patent
Jul. 12, 2011
Sheet 12 0f 21
US RE42,551 E
‘I 400
WRITE READ IDENTIFIER CODES COMMAND TO CSM
' CSM DECODES COMMAND AND INDICATES
AND SENDS CDRDLK SIGNAL TO BLOCK
LOCK MINI-ARRAY
CSM ENABLES THE SENSE CIRCUITS AND THE OUTPUT MULTIPLEXER
APPROPRIATE READ VOLTAGES ARE APPLIED TO THE BLOCK LOCK MINI-ARRAY
LOCK-BIT OR MASTER LOCK-BIT ADDRESS LATCHED
LOCK-BIT OR MASTER LOCK-BIT READ OUT
TO DATA BUS
1402
US. Patent
Jul. 12, 2011
Sheet 13 0121
US RE42,551 E
1500
1502
WRJTE BYTE WRITE OR ERASE COMMAND TO MEMORY DEVICE 1504
WRITE DATA AND ADDRESS TO MEMORY DEViCE
PERFORM PROGRAM OR ERASE
FUNCTION
OVERRIDE ENABLED?
UNSUCCESSFUL PROGRAM/ERASE FUNCTION 1514
FIG. 15
US. Patent
Jul. 12, 2011
Sheet 14 0121
US RE42,551 E
1600
WSM CAUSES THE APPROPRIATE LOCK BLOCK-BIT ADDRESS TO BE COUPLED TO THE BLOCK LOCK MINI-ARRAY
WSM CAUSES VOLTAGE CONTROL CIRCUITRY TO COUPLE THE APPROPRIATE READ VOLTAGES TO BLOCK LOCK MINI-ARRAY
WSM ENABLES SENSING CIRCUIT
WSM READS THE STATE OF THE BLOCK LOCK-BIT
FIG. 16
US. Patent
Jul. 12, 2011
Sheet 15 0121
US RE42,551 E
1 700
1702
WRITE "PROGRAM PASS CODE‘ COMMAND TO MEMORY DEVICE
R131? 2 VHH?
¢ PROGRAM PASSCODE
UNSUCCESSFUL
1 706
WSM PROGRAMS PASSCODE DATA
FIG. 17
1710
US. Patent
Jul. 12, 2011
Sheet 16 0121
US RE42,551 E
1800
1 802
WHITE “PROGRAM PASSCODE"
COMMAND TO CSM
1 804
CSM DECODES COMMAND AND CHECKS F1P#
l UPDATE STATUS REGBTER TO SHOW FAILURE
WSM PROGRAMS PASSCODE DATA
1808
1810
UPDATE STATUS REGISTER
FIG. 18
1814
US. Patent
Jul. 12, 2011
Sheet 17 0121
US RE42,551 E
1 900
1 902
WRITE "PROGRAM PASSCODE“ COMMAND TO MEMORY DEVICE
1910 READ PASSCODE
1906
READ PASSCODE DATA ON
DATA BUS
FIG. 19
UNSUCCESSFUL
US. Patent
Jul. 12, 2011
Sheet 18 0121
US RE42,551 E
2000
2002
WRITE "READ PASSCODE"
COMMAND TO CSM
2004
CSM DEGODES COMMAND AND CHECKS RPII
2014
2008
FAIL
CSM ENABLES SENSE AND PASSCODE CIRCUIT RY
2010 PASSCODE READ OUT TO DATA BUS
FIG. 20
UPDATE STATUS REGISTER TO SHOW
US. Patent
Jul. 12, 2011
Sheet 19 0121
US RE42,551 E
2100
2102
WRITE ‘ENTER PASSCODE' COMMAND TO MEMORY DEViCE
WRITE PASSCODE DATA TO THE MEMORY DEVICE
COMPARE DATA TO INTERNAL
2104
2106
PASSCODE
PASSCODE MATCH?
2114
PASSCODE ENTRY UNSUCCESSFUL 2110
SET OVERRIDE ENABLE BlT
FIG. 21
