USO0RE43162E
(19) United States (12) Reissued Patent RaghuRam
(10) Patent Number: US (45) Date of Reissued Patent:
Feb. 7, 2012
OTHER PUBLICATIONS
(54) SEMICONDUCTOR MEMORY MODULE, ELECTRONIC APPARATUS AND METHOD FOR OPERATING THEREOF
RE43,162 E
Jun. 15, 2011 German Of?ce Action in German Patent Application No. 10 2007 009 817.2 which claims priority to US. patent applica
tion No. 11/364,135 (German language document).
(75) Inventor:
Siva RaghuRam,Unterschiei[3heim
* cited by examiner
(DE)
Primary Examiner * Pho M Luu
(74) Attorney, Agent, or Firm * John S. Economou
(73) Assignee: QimondaAG, Munich (DE)
(57)
(21) App1.No.: 12/759,827
A semiconductor memory module (1) includes a circuit sub strate (2), a ?rst (100), a second (200), a third (300) and a
(22) Filed:
fourth (400) rank of memory chips (3), a ?rst register (10) and a second register (20). The ?rst register (10) and the second
Apr. 14, 2010 Related US. Patent Documents
Reissue of:
(64) Patent No.: Issued: Appl. No.:
7,359,257 Apr. 15, 2008 11/364,135
Filed:
Feb. 28, 2006
ABSTRACT
register (20) each comprise a ?rst input (11, 21) for receiving a respective chip select signal (CS0, CS2), a second input (12, 22) for receiving a respective other chip select signal (CS1, CS3) at least one third input (13, 23) for receiving command/ address signals (CA), and at least one third output (16, 26). The at least one third output (1 6, 26) of the respective ?rst (1 0) and second (20) register transmits the command/ address sig nals (CA), if at least one of the respective chip select signal
(51)
Int. Cl. GIIC 7/00
(52)
US. Cl. ......... .. 365/191; 365/51; 365/194; 365/198
(58)
Field of Classi?cation Search .................. .. 365/51
(2006.01)
(CS0, CS2) received at the respective ?rst input (11, 21) of the respective register (10, 20) and the respective other chip select signal (CS1, CS3) received at the respective second input (12,
See application ?le for complete search history.
22) of the respective register (10, 20) is active, and blocks a transmission of the command/address signals (CA), if both the respective chip select signal (CS0, CS2) received at the
References Cited
respective ?rst input (11, 21) of the respective register (10, 20) and the respective other chip select signal (CS1, CS3)
U.S. PATENT DOCUMENTS
received at the respective second input (12, 22) of the respec tive register (10, 20) are inactive.
365/194,191,198 (56)
6,937,494 B2 * 7,072,201 B2 *
2004/0098528 Al
3
8/2005 7/2006
Funaba et a1. ................ .. 365/63 So et al. ........................ .. 365/63
48 Claims, 5 Drawing Sheets
5/2004 JanZen
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102 101
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CA 60
CA 301
302 402
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401
402
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Feb. 7, 2012
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US RE43,162 E 1
2
SEMICONDUCTOR MEMORY MODULE,
an inactive level, at least one third input for receiving com
ELECTRONIC APPARATUS AND METHOD FOR OPERATING THEREOF
mand/address signals, a ?rst output for transmitting the respective chip select signal to the memory chips of the ?rst rank and the third rank, respectively, a second output for
transmitting the respective other chip select signal to the Matter enclosed in heavy brackets [ ] appears in the original patent but forms no part of this reissue speci?ca
memory chips of the second rank and the fourth rank, respec tively, and at least one third output. The at least one third output of the ?rst register transmits the command/ address signals to the memory chips of the ?rst rank and to the memory chips of the second rank, if at least one of the chip select signal received at the ?rst input of the ?rst register and the other chip select signal received at the second input of the ?rst register is active, and blocks a trans mission/ switching of the command/address signals to the memory chips of the ?rst rank and to the memory chips of the second rank, if both the chip select signal received at the ?rst
tion; matter printed in italics indicates the additions made by reissue. TECHNICAL FIELD
The present invention relates to semiconductor memory modules and electronic apparatuses comprising a semicon ductor memory module and more speci?cally to semiconduc tor memory modules consuming low power.
input of the ?rst register and the other chip select signal BACKGROUND
Computer systems typically have a processing unit and a memory system connected to it for storing data. The memory
20
system includes a memory controller and one or more semi
conductor memory modules. The processing unit is con nected to the memory controller via a bus system and the memory controller is coupled to the semiconductor memory modules via a memory bus system. Each of the semiconduc tor memory modules comprises at least one register and a
25
number of ranks of memory chips coupled to the register. The
received at the second input of the ?rst register are inactive. The at least one third output of the second register transmits the command/address signals to the memory chips of the third rank and to the memory chips of the fourth rank, if at least one of the chip select signal received at the ?rst input of the second
register and the other chip select signal received at the second input of the second register is active, and blocks a transmis sion/ switching of the command/address signals to the memory chips of the third rank and to the memory chips of the fourth rank, if both the chip select signal received at the ?rst input of the second register and the other chip select signal
memory chips. For selecting a speci?c rank of memory chips
received at the second input of the second register are inac tive. Another aspect of the present invention provides an elec
for a memory access, respective chip select signals are used to
tronic apparatus including a controller device, a bus system
activate the respective rank. Typically, command/address
and at least one semiconductor memory module. The semi conductor memory module includes a circuit substrate, a ?rst, a second, a third and a fourth rank of memory chips each
registers transmit command/address signals and chip select signals received from the memory controller to the ranks of
inputs of memory chips of several ranks are coupled in par allel to one output of a single register. The register transmits command/address signals to the respective ranks of memory chips if at least one of the respective chip select signals is active. Therefore, command/address signals are transmitted unnecessarily to ranks of memory chips coupled to the reg ister but not being addressed by a memory access.
Due to the capacitance of the memory chips and the lines coupling the memory chips with the register, power is con sumed by the semiconductor memory module each time data signals are transmitted. Therefore, power is wasted during each memory access when transmitting command/address
30
35
including a multiplicity of memory chips and each being disposed on the circuit substrate. The semiconductor memory module further includes a ?rst register and a second register each disposed on the circuit substrate, wherein the ?rst reg 40
signal having one of an active and an inactive level, a second
45
signals to a number of ranks of memory chips that are not addressed.
50
third output.
55
One embodiment of the present invention provides a semi conductor memory module that includes a circuit substrate, a ?rst, a second, a third and a fourth rank of memory chips each
including a multiplicity of memory chips and each being
60
disposed on the circuit substrate. The semiconductor memory module further includes a ?rst register and a second register each disposed on the circuit substrate, wherein the ?rst reg
ister and the second register each comprise a ?rst input for receiving a respective chip select signal having one of an active and an inactive level, a second input for receiving a
respective other chip select signal having one of an active and
select signal to the memory chips of the ?rst rank and the third rank, respectively, a second output for transmitting the respective other chip select signal to the memory chips of the second rank and the fourth rank, respectively, and at least one
What is desired is a semiconductor memory module and an electronic apparatus comprising a memory module that con sumes low power and a method of operating thereof.
SUMMARY OF THE INVENTION
input coupled to the controller device for receiving a respec tive other chip select signal having one of an active and an inactive level, at least one third input coupled to the controller device via the bus system for receiving command/address
signals, a ?rst output for transmitting the respective chip
In addition, due to the increasing operating speed of the semiconductor memory modules, the power consumption further increases.
ister and the second register each include a ?rst input coupled to the controller device for receiving a respective chip select
The at least one third output of the ?rst register transmits the command/ address signals to the memory chips of the ?rst rank and to the memory chips of the second rank, if at least one of the chip select signal received at the ?rst input of the ?rst register and the other chip select signal received at the second input of the ?rst register is active, and blocks a trans mission/ switching of the command/address signals to the memory chips of the ?rst rank and to the memory chips of the second rank, if both the chip select signal received at the ?rst
input of the ?rst register and the other chip select signal 65
received at the second input of the ?rst register are inactive. The at least one third output of the second register transmits the command/address signals to the memory chips of the third rank and to the memory chips of the fourth rank, if at least one of the chip select signal received at the ?rst input of the second
US RE43,162 E 3
4
register and the other chip select signal received at the second input of the second register is active, and blocks a transmis sion/sWitching of the command/address signals to the memory chips of the third rank and to the memory chips of the fourth rank, if both the chip select signal received at the ?rst input of the second register and the other chip select signal
FIG. 3 depicts schematically an electronic apparatus according to one embodiment of the present invention; FIG. 4 depicts schematically an electronic apparatus according to one embodiment of the present invention; and FIG. 5 depicts schematically a cross-sectional vieW of the semiconductor memory module of the electronic apparatus depicted in FIG. 4.
received at the second input of the second register are inac tive. Another aspect of the present invention provides a method of operating a semiconductor memory module. The method includes providing a semiconductor memory module, Wherein the semiconductor memory module includes a cir
DETAILED DESCRIPTION OF ILLUSTRATIVE EMBODIMENTS
FIG. 1 depicts schematically a semiconductor memory module 1 according to one embodiment of the present inven tion. The semiconductor memory module 1 comprises a cir cuit substrate 2 having a ?rst surface S1 and a second surface S2. The circuit substrate 2 is preferably a circuit board, e.g., a
cuit substrate, a ?rst, a second, a third and a fourth rank of
memory chips, each including a multiplicity of memory chips and each being disposed on the circuit substrate. The semi conductor memory module further includes a ?rst register and a second register each disposed on the circuit substrate, Wherein the ?rst register and the second register each include
printed circuit board With conductive lines disposed thereon.
a ?rst input for receiving a respective chip select signal having one of an active and an inactive level, a second input for
20
A ?rst register 10, a ?rst rank 100 and a second rank 200 of memory chips 3 are disposed on the ?rst surface S1. In FIG. 1, each of the ?rst rank 100 and the second rank 200 of
memory chips 3 includes nine memory chips 3. HoWever, the
receiving a respective other chip select signal having one of an active and an inactive level, at least one third input for
?rst rank 100 and the second rank 200 may each include
receiving command/address signals, a ?rst output for trans
eighteen memory chips 3. Each of the ?rst 100 and second 200 ranks of memory chips 3 comprises a multiplicity of memory chips 3. In this embodiment, the memory chips 3 are
mitting the respective chip select signal to the memory chips of the ?rst rank and the third rank, respectively, a second
25
output for transmitting the respective other chip select signal
stacked upon each other and more speci?cally, the memory chips 3 of the second rank 200 are stacked upon memory
to the memory chips of the second rank and the fourth rank, respectively, and at least one third output. The method further includes determining, if of one of the
respective chip select signals and one of the respective other chip select signals is active, transmitting/switching the com mand/address signals to the memory chips of the ?rst rank
chips 3 of the ?rst rank 100. HoWever, memory chips 3 of the ?rst rank 100 and of the second rank 200 may be arranged in 30
and to the memory chips of the second rank via the at least one third output of the ?rst register, if at least one of the chip select
signal received at the ?rst input of the ?rst register and the other chip select signal received at the second input of the ?rst register is active, and blocking a transmission/switching of the command/address signals to the memory chips of the ?rst rank and to the memory chips of the second rank, if both the chip select signal received at the ?rst input of the ?rst register and the other chip select signal received at the second input of
35
40
The method further includes transmitting/switching the
chip select signal received at the ?rst input of the second register and the other chip select signal received at the second input of the second register is active, and blocking a trans mission/sWitching of the command/address signals to the memory chips of the third rank and to the memory chips of the fourth rank, if both the chip select signal received at the ?rst input of the second register and the other chip select signal received at the second input of the second register are inac tive.
select signal CSO, a second input 12 for receiving a chip select signal CS1, at least one third input 13 for receiving command/ address signals CA and a fourth input 17 for receiving a control signal CS GATE EN. The command/address signals CA may be transmitted by a bus system 60. Furthermore, the ?rst register has a ?rst output 14, a second output 15 and at least one third output 16. Chip select inputs 101 of memory chips 3 of the ?rst rank 100 are coupled in parallel to the ?rst
the ?rst register are inactive.
command/address signals via the at least one third output of the second register to the memory chips of the third rank and to the memory chips of the fourth rank, if at least one of the
a single layer on the ?rst surface S1 of the circuit substrate 2. The ?rst register 10 has a ?rst input 11 for receiving a chip
45
output 14 of the ?rst register 10 for transmitting the chip select signal CSO from the ?rst register 10 to the memory chips 3 of the ?rst rank 100. Chip select inputs 201 of the memory chips 3 of the second rank 200 are coupled in parallel to the second output 15 of the ?rst register 10 for transmitting the chip select signal CS1 from the ?rst register 10 to the memory chips 3 of the second rank 200. Command/address inputs 102, 202 of the memory chips 3 of the ?rst rank 100 and of the second rank 200 are coupled in parallel to the at least one third output 16 of the ?rst register 10 for transmitting/
50
sWitching command/ address signals CA from the ?rst regis
55
ter 10 to the memory chips 3 of the ?rst rank 100 and of the second rank 200. In FIG. 1, a connection betWeen the at least one third output 16 of the ?rst register 10 With the memory chips 3 of the ?rst rank 100 and With the memory chips 3 of the second rank 200 is illustrated by a single line for reasons
BRIEF DESCRIPTION OF THE DRAWINGS
of better clearness. HoWever, the connection may be provided by a bus system.
For a more complete understanding of the present inven tion, and the advantages thereof, reference is noW made to the
A second register 20, a third rank 300 and a fourth rank 400 of memory chips 3 are disposed on the second surface S2. In FIG. 1, each of the third rank 300 and the fourth rank 400 of
60
folloWing descriptions taken in conjunction With the accom
memory chips 3 includes nine memory chips 3. HoWever, the
panying draWing, in Which:
third rank 300 and the fourth rank 400 may each include
FIG. 1 depicts schematically a semiconductor memory module according to one embodiment of the present inven
eighteen memory chips 3. Each of the third 300 and fourth 400 ranks of memory chips 3 includes a multiplicity of memory chips 3. In this embodiment, the memory chips 3 are stacked upon each other and more speci?cally, the memory chips 3 of the fourth rank 400 are stacked upon memory chips
tion; FIG. 2 depicts a plan vieW of the semiconductor memory module as depicted in FIG. 1;
65
US RE43,162 E 5
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3 of the third rank 300. However, memory chips 3 of the third rank 300 and of the fourth rank 400 may be arranged in a single layer on the second surface S2 of the circuit substrate 2. The second register 20 has a ?rst input 21 for receiving a
the chip select signals CS0 and CS1 is active, then the com mand/address signals CA are transmitted via the at least one
chip select signal CS2, a second input 22 for receiving a chip select signal CS3, at least one third input 23 for receiving command/address signals CA and a fourth input 27 for receiving a control signal CS GATE EN. Furthermore, the second register 20 has a ?rst output 24, a second output 25 and at least one third output 26. Chip select inputs 301 of memory chips 3 of the third rank 300 are coupled in parallel to the ?rst output 24 of the second register 20 for transmitting the chip select signal CS2 from the second register 20 to the memory chips 3 of the third rank 300. Chip select inputs 401 of memory chips 3 of the fourth rank 400 are coupled in parallel to the second output 25 of the second register 20 for trans
mitting the chip select signal CS3 from the second register 20 to the memory chips 3 of the fourth rank 400. Command/
address inputs 302, 402 of the memory chips 3 of the third rank 300 and of the fourth rank 400 are coupled in parallel to the at least one third output 26 of the second register for
20
transmitting/switching command/address signals to the
Accordingly, in the second mode of operation, the respec
memory chips 3 of the third rank 300 and of the fourth rank
tive at least one third output 16, 26 of each of the ?rst 10 and
400. In FIG. 1, a connection betWeen the at least one third
output 26 of the second register 20 With the memory chips 3 of the third rank 300 and With the memory chips 3 of the
25
fourth rank 400 is illustrated by a single line for reasons of
better clearness. HoWever, the connection may be provided by a bus system. Preferably memory chips 3 are DRAM memory chips pro viding a dynamic random access. HoWever, other memory chips such as SDRAM memory chips may be used. A memory chip can be activated by applying an active chip select signal to the chip select input of the memory chip. To activate the memory chip, a value of 0 is sent to the chip select
third output 16 to the memory chips 3 of the ?rst rank 100 and of the second rank 200. If both chip select signals CS0 and CS1 are inactive, then the transmission of the command/ address signals CA via the at least one third output 16 to the memory chips 3 of the ?rst rank 100 and of the second rank 200 is blocked. Furthermore, in the second mode of operation, an active level of the control signal CS GATE EN is applied to the fourth input 27 of the second register 20. The transmission of command/address signals CA applied to the at least one third input 23 to memory chips 3 via the at least one third output 26 is dependent on the level of the chip select signals CS2 and CS3. If at least one ofthe chip select signals CS2 and CS3 is active, then the command/address signals CA are transmitted via the at least one third output 26 to the memory chips 3 of the third rank 300 and of the fourth rank 400. If both chip select signals CS2 and CS3 are inactive, then the transmission of the command/address signals CA via the at least one third output 26 to the memory chips 3 of the third rank 300 and of the fourth rank 400 is blocked.
30
second 20 registers drives the command/address signals CA only When the register 10, 20 receives a chip select signal that refers to a rank that is connected to the respective register 10, 20. Therefore, the poWer consumed during a memory access in Which only ranks connected to a single register are addressed, is reduced. This reduction of poWer consumption also reduces the heat generated in the semiconductor memory
module 1 and, therefore, less cooling, e. g., provided by an air How, of the semiconductor memory module is required. This advantageously reduces the cost of the semiconductor 35
input of the memory chips. If a value of l is applied to the chip select input of the memory chip, the memory chip is inactive.
memory module and the maintenance costs. FIG. 2 depicts a plan vieW of the semiconductor memory module 1 as depicted in FIG. 1. Memory chips 3 are mounted
The use of chip select signals alloWs selecting speci?c chips/
on a ?rst surface S1 of a circuit substrate 2. In this embodi
ranks during a memory access for reading data from the
ment, memory chips 3 are labeled U1 to U36. Memory chips U1 to U36 are arranged in tWo levels. Memory chips U1 to
memory chip or Writing data to the memory chip. The control signal CS GATE EN is coupled to the fourth input 17 of the ?rst register 10 and to the fourth input 27 of the second register 20 in parallel and may be provided by a motherboard of a computer. The control signal CS GATE EN has one of an active and an inactive level. The semiconductor memory module can be
40
U18 are mounted on the circuit substrate 2 and memory chips U19 to U36 are stacked upon memory chips U1 to U18. By
stacking the memory chips upon another, the density of 45
operated in a ?rst mode relating to this signal being inactive and in a second mode relating to the control signal being active. In the ?rst mode of operation, an inactive level of the
50
control signal CS GATE EN is applied to the fourth input 17 of the ?rst register 10 and to the fourth input 27 of the second register 20. The command/ address signals CA applied to the at least one third input 13 of the ?rst register 10 are transmit ted via the at least one third output 16 of the ?rst register 10 to the memory chips 3 of the ?rst rank 100 and of the second
memory chips on the circuit substrate 2 is increased. Memory chips U1 to U36 are grouped in ranks of memory chips. In this embodiment a ?rst rank 100 comprises memory chips U1 to U18 and a second rank 200 of memory chips comprises memory chips U19 to U36. HoWever, other compositions of the ?rst 100 and second ranks 200 are possible. It is also possible that U1 to U36 are thirty-six stacked chips, Wherein U1 to U18 are placed on the ?rst surface S1 of the circuit substrate 2 and U19 to U36 are placed on a second surface
55
(not shoWn in FIG. 2) of the circuit substrate 2. An edge connector 8 having pins 9 is disposed at a long end of the circuit substrate 2. The edge connector 8 provides a connection betWeen the semiconductor memory module 1
rank 200, and the command/address signals CA applied to the
and an external device such as a controller device by, for
at least one third input 23 of the second register 20 are trans mitted via the at least one third output 26 of the second
example, a bus system. One end of each of the pins 9 is
register 20 to the memory chips 3 of the third rank 300 and of the fourth rank 400. In the second mode of operation, an active level of the control signal CS GATE EN is applied to the fourth input 17 of the ?rst register 10. The transmission of command/address signals CA applied to the at least one third input 13 to memory chips 3 via the at least one third output 16 is dependent on the level ofthe chip select signals CS0 and CS1. Ifat least one of
coupled to register 10 by conductive lines (not shoWn) dis 60
posed on the circuit substrate 2 for the transmission of elec
trical signals. Another end of each of the pins 9 provides a connection to a socket of an external device.
FIG. 3 depicts schematically an electronic apparatus 65
according to one embodiment of the present invention. The electronic apparatus includes a ?rst semiconductor memory module 1, a second semiconductor memory module 1', a controller device 50 and a bus system 60.
US RE43,162 E 8
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module 1' are coupled to the ?rst output 34 of the ?rst register 30 of the second semiconductor memory module 1' for the transmission of the chip select signal CS4 to the memory chips (not shoWn in FIG. 3) of the ?rst rank 500 of the second semiconductor memory module 1'.
First 1 and second 1' semiconductor memory modules are
coupled to the controller device 50 via the bus system 60 for the transmission of electrical signals, e. g., command/address signals CA. First 1 and second 1' semiconductor memory modules preferably include a connector such as an edge con
Chip select inputs of memory chips (not shoWn in FIG. 3)
nector (not shoWn in FIG. 3) for connecting to bus system 60. Typically, the bus system 60 comprises sockets (not shoWn in FIG. 3) in Which ?rst 1 and second 1' semiconductor memory
of the second rank 600 of the second semiconductor memory module 1' are coupled to the second output 35 of the ?rst register 30 of the second semiconductor memory module 1' for the transmission of the chip select signal CS5 to the
modules are plugged in. The bus system 60 may include a
multiplicity of sockets for connecting a multiplicity of semi
memory chips (not shoWn in FIG. 3) of the second rank 600 of
conductor memory modules to the controller device 50. A bus termination 61 disposed at the end of the bus system 60 terminates the bus system 60. Each of the ?rst 1 and second 1' semiconductor memory modules includes a ?rst register 10, 30, a second register 20, 40, a ?rst 100, 500, a second 200, 600, a third 300,700 and a
the second semiconductor memory module 1'.
Chip select inputs of memory chips (not shoWn in FIG. 3) of the third rank 700 of the second semiconductor memory module 1' are coupled to the ?rst output 44 of the second register 40 of the second semiconductor memory module 1' for the transmission of the chip select signal CS6 to the
fourth rank 400, 800 of memory chips (not shoWn in FIG. 3). Each of the ?rst 10, 30 and second 20, 40 registers of the
memory chips (not shoWn in FIG. 3) of the third rank 700 of the second semiconductor memory module 1'.
?rst 1 and second 1' semiconductor memory modules have a
?rst input 11, 21, 31, 41 coupled to the controller circuit 50 for
20
receiving a respective chip select signal CS0, CS2, CS4, CS6, a second input 12, 22, 32, 42 coupled to the controller circuit 50 for receiving a respective other chip select signal CS1, CS3, CS5, CS7 and at least one third input 13, 23, 33, 43 coupled to the controller circuit 50 for receiving command/ address signals CA. Each of the ?rst 10, 30 and second 20, 40 registers of the
Chip select inputs of memory chips (not shoWn in FIG. 3) of the fourth rank 800 of the second semiconductor memory module 1' are coupled to the second output 45 of the second register 40 of the second semiconductor memory module 1' for the transmission of the chip select signal CS7 to the
25
memory chips (not shoWn in FIG. 3) of the fourth rank 800 of the second semiconductor memory module 1'.
Command/address inputs of memory chips (not shoWn in
coupled to the fourth inputs 17, 27, 37, 47 in parallel and may
FIG. 3) of the ?rst rank 100 and of the second rank 200 of the ?rst semiconductor memory module 1 are coupled in parallel to the at least one third output 16 of the ?rst register 10 of the ?rst semiconductor memory module 1 for the transmission of
be provided by a motherboard of a computer or may be Wired
command/address signals to the memory chips (not shoWn in
on the semiconductor memory module 1 itself.
FIG. 3) of the ?rst rank 100 and of the second rank 200 of the ?rst semiconductor memory module 1.
?rst 1 and second 1' semiconductor memory modules have a
respective fourth input 17, 27, 37, 47 for receiving a control signal CS GATE EN. The control signal CS GATE EN is
Furthermore, each of the ?rst 10, 30 and second 20, 40 registers of the ?rst 1 and second 1' semiconductor memory modules have a ?rst output 14, 24, 34, 44, a second output 15, 25, 35, 45 and at least one third output 16, 26, 36, 46.
30
35
Chip select inputs of memory chips (not shoWn in FIG. 3) of the ?rst rank 100 of the ?rst semiconductor memory mod ule 1 are coupled to the ?rst output 14 of the ?rst register 10 of the ?rst semiconductor memory module 1 for the transmis
40
Command/address inputs of memory chips (not shoWn in
shoWn in FIG. 3) of the ?rst rank 100 of the ?rst semiconduc tor memory module 1. 45
of the second rank 200 of the ?rst semiconductor memory module 1 are coupled to the second output 15 of the ?rst register 10 of the ?rst semiconductor memory module 1 for the transmission of the chip select signal CS1 to the memory
chips (not shoWn in FIG. 3) of the second rank 200 of the ?rst
50
Chip select inputs of memory chips (not shoWn in FIG. 3) 55
chips (not shoWn in FIG. 3) of the third rank 300 of semicon ductor the ?rst memory module 1.
Chip select inputs of memory chips (not shoWn in FIG. 3) of the fourth rank 400 of the ?rst semiconductor memory module 1 are coupled to the second output 25 of the second register 20 of the ?rst semiconductor memory module 1 for the transmission of the chip select signal CS3 to the memory
60
Chip select inputs of memory chips (not shoWn in FIG. 3) of the ?rst rank 500 of the second semiconductor memory
FIG. 3) of the third rank 700 and of the fourth rank 800 of the second semiconductor memory module 1' are coupled in par allel to the at least one third output 46 of the second register 40 of the second semiconductor memory module 1' for the trans mission of command/address signals to the memory chips (not shoWn in FIG. 3) of the third rank 700 and of the fourth rank 800 of the second semiconductor memory module 1'. If an inactive level of the control signal CS GATE EN is
applied to each of the fourth inputs 17, 27, 37, 47 of the respective ?rst 10, 30 and second 20, 40 registers of the respective ?rst 1 and second 1' semiconductor memory mod ules, then the command/address signals CA applied to the at least one third input 13 of the ?rst register 10 of the ?rst
chips (not shoWn in FIG. 3) of the fourth rank 400 of ?rst semiconductor memory module 1.
FIG. 3) of the ?rst rank 500 and of the second rank 600 of the second semiconductor memory module 1' are coupled in par allel to the at least one third output 36 of the ?rst register 30 of the second semiconductor memory module 1' for the trans mission of command/address signals to the memory chips (not shoWn in FIG. 3) of the ?rst rank 500 and of the second rank 600 of the second semiconductor memory module 1'.
Command/address inputs of memory chips (not shoWn in
semiconductor memory module 1.
of the third rank 300 of the ?rst semiconductor memory module 1 are coupled to the ?rst output 24 of the second register 20 of the ?rst semiconductor memory module 1 for the transmission of the chip select signal CS2 to memory
sion of command/address signals to the memory chips (not shoWn in FIG. 3) of the third rank 300 and of the fourth rank 400 of the ?rst semiconductor memory module 1.
sion of the chip select signal CS0 to the memory chips (not
Chip select inputs of memory chips (not shoWn in FIG. 3)
Command/address inputs of memory chips (not shoWn in FIG. 3) ofthe third rank 300 and ofthe fourth rank 400 ofthe ?rst semiconductor memory module 1 are coupled in parallel to the at least one third output 26 of the second register 20 of the ?rst semiconductor memory module 1 for the transmis
65
semiconductor memory module 1 are transmitted via the at
least one third output 16 of the ?rst register 10 of the ?rst semiconductor memory module 1 to the memory chips 3 of
US RE43,162 E 9
10
the ?rst rank 100 and of the second rank 200 of the ?rst
rank 800 of the second semiconductor memory module 1'. If
semiconductor memory module 1, the command/address sig
both chip select signals CS6 and CS7 are inactive, then the transmission of command/address signals CA via the at least one third output 46 to the memory chips 3 of the third rank 700 and of the fourth rank 800 is blocked. FIG. 4 depicts schematically an electronic apparatus according to one embodiment of the invention. The electronic
nals CA applied to the at least one third input 23 of the second register 20 of the ?rst semiconductor memory module 1 are transmitted via the at least one third output 26 of the second register 20 of the ?rst semiconductor memory module 1 to the memory chips 3 of the third rank 300 and of the fourth rank 400 of the ?rst semiconductor memory module 1, the com mand/address signals CA applied to the at least one third
apparatus includes a semiconductor memory module 1, a bus system 60 and a controller device 50 such as a memory
input 33 of the ?rst register 30 of the second semiconductor
controller. The semiconductor memory module 1 includes a ?rst 100,
memory module 1' are transmitted via the at least one third
output 36 of the ?rst register 30 of the second semiconductor memory module 1' to the memory chips 3 of the ?rst rank 500 and of the second rank 600 of the second semiconductor
a second 200, a third 300, a fourth 400, a ?fth 500, a sixth 600, a seventh 700 and an eighth 800 rank of memory chips dis
posed. Furthermore, the semiconductor memory module 1
memory module 1', the command/address signals CA applied
includes a ?rst 10, a second 20, a third 30 and a fourth 40
to the at least one third input 43 of the second register 40 of the second semiconductor memory module 1' are transmitted via the at least one third output 46 of the second register 40 of the second semiconductor memory module 1' to the memory chips 3 of the third rank 700 and of the fourth rank 800 of the second semiconductor memory module 1'. If an active level of the control signal CS GATE EN is
register. Each of the ?rst 10, second 20, third 30 and fourth 40
20
register has a respective ?rst input 11, 21, 31, 41 coupled to the controller device 50 for receiving a respective chip select signal CS0, CS2, CS4, CS6, CS8, a respective second input 12, 22, 32, 42 coupled to the controller device 50 for receiving
another respective chip select signal CS1, CS3, CS5, CS7,
applied to each of the fourth input 17, 27, 37, 47 of the respective ?rst 10, 30 and second 20, 40 registers of the
and at least one third input 13, 23, 33, 43 coupled to the controller device 50 for receiving command/address signals
respective ?rst 1 and second 1' semiconductor memory mod ules, then the transmission of command/address signals CA applied to respective at least one third inputs 13, 23, 33, 43 is dependent on the respective chip select signals CS0 to CS7. If at least one of the chip select signals CS0 and CS1
25
coupled respectively to the ?rst input 11 and the second input
30
CA.
Each of the ?rst 10, second 20, third 30 and fourth 40
register has a respective fourth input 17, 27, 37, 47 for receiv ing a control signal CS GATE EN, Wherein the control signal CS GATE EN is coupled to the fourth inputs 17, 27, 37 and 47
12 of the ?rst register 10 of the ?rst semiconductor memory module 1 is active, then the command/address signals CA are
in parallel. Furthermore, each of the ?rst 10, second 20, third 30 and
fourth 40 register has a respective ?rst output 14, 24, 34, 44,
transmitted via the at least one third output 16 to the memory
a respective second output 15, 25, 35, 45 and at least one
chips 3 of the ?rst rank 100 and of the second rank 200 of the ?rst semiconductor memory module 1. If both chip select signals CS0 and CS1 are inactive, then the transmission of command/address signals CA via the at least one third output 16 to the memory chips 3 of the ?rst rank 100 and of the second rank 200 is blocked. If at least one of the chip select signals CS2 and CS3
respective third output 16, 26, 36, 46. Chip select inputs of 35
memory chips (not shoWn in FIG. 4) of the ?rst rank 100 are coupled to the ?rst output 14 of the ?rst register 10 for the
transmission of the chip select signal CSO, chip select inputs 40
coupled respectively to the ?rst input 21 and the second input
of the memory chips (not shoWn in FIG. 4) of the second rank 200 are coupled to the second output 15 of the ?rst register 10 for the transmission of the chip select signal CS1, chip select inputs of the memory chips of the third rank 300 are coupled
22 of the second register 20 of the ?rst semiconductor memory module 1 is active, then the command/address sig
to the ?rst output 24 of the second register 20 for the trans
nals CA are transmitted via the at least one third output 26 to
memory chips (not shoWn in FIG. 4) of the fourth rank 400 are coupled to the second output 25 of the second register 20 for
the memory chips 3 of the third rank 300 and of the fourth rank 400 of the ?rst semiconductor memory module 1. If both chip select signals CS2 and CS3 are inactive, then the trans mission of command/address signals CA via the at least one third output 26 to the memory chips 3 of the third rank 3 00 and of the fourth rank 400 is blocked. If at least one of the chip select signals CS4 and CS5
mission of the chip select signal CS2, chip select inputs of the 45
the transmission of the chip select signal CS3, chip select inputs of the memory chips (not shoWn in FIG. 4) of the ?fth rank 500 are coupled to the ?rst output 34 of the third register 50
sixth rank 600 are coupled to the second output 35 of the third
coupled respectively to the ?rst input 31 and the second input
register 30 for the transmission of the chip select signal CS5, chip select inputs of the memory chips (not shoWn in FIG. 4)
32 of the ?rst register 30 of the second semiconductor memory module 1' is active, then the command/address sig nals CA are transmitted via the at least one third output 36 to
the memory chips 3 of the ?rst rank 500 and of the second rank 600 of the second semiconductor memory module 1'. If both chip select signals CS4 and CS5 are inactive, then the transmission of command/ address signals CA via the at least one third output 36 to the memory chips 3 of the ?rst rank 500 and of the second rank 600 is blocked. If at least one of the chip select signals CS6 and CS7
coupled to the respective ?rst input 41 and the second input 42 of the second register 40 of the second semiconductor memory module 1' is active, then the command/address sig
30 for the transmission of the chip select signal CS4, chip select inputs of the memory chips (not shoWn in FIG. 4) of the
of the seventh rank 700 are coupled to the ?rst output 44 of the 55
60
fourth register 40 for the transmission of the chip select signal CS6, and chip select inputs of the memory chips (not shoWn in FIG. 4) of the eighth rank 800 are coupled to the second output 45 of the fourth register 40 for the transmission of the
chip select signal CS7. Command/address inputs of memory chips (not shoWn in FIG. 4) of the ?rst rank 100 and of the second rank 200 are coupled inparallel to the at least one third output 16 of the ?rst
register 10 for the transmission of command/ address signals to the memory chips (not shoWn in FIG. 4) of the ?rst rank 100 65
and of the second rank 200.
nals CA are transmitted via the at least one third output 46 to
Command/address inputs of memory chips (not shoWn in
the memory chips 3 of the third rank 700 and of the fourth
FIG. 4) of the third rank 300 and of the fourth rank 400 are
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12
coupled in parallel to the at least one third output 26 of the second register 20 for the transmission of command/address
to the memory chips 3 of the ?fth rank 500 and of the sixth rank 600. If both chip select signals CS4 and CS5 are inactive, then the transmission of command/ address signals CA via the at least one third output 36 to the memory chips 3 of the ?fth rank 500 and of the sixth rank 600 is blocked. If at least one of the chip select signals CS6 and CS7
signals to the memory chips (not shoWn in FIG. 4) of the third rank 300 and ofthe fourth rank 400.
Command/ address inputs of memory chips (not shoWn in FIG. 4) of the ?rst rank 500 and of the second rank 600 are coupled in parallel to the at least one third output 36 of the third register 30 for the transmission of command/address
coupled to the respective ?rst input 41 and the second input 42 of the fourth register 40 is active, then the command/address
signals to the memory chips (not shoWn in FIG. 4) of the ?fth
signals CA are transmitted via the at least one third output 46 to the memory chips 3 of the seventh rank 700 and of the eighth rank 800. If both chip select signals CS6 and CS7 are
rank 500 and ofthe sixth rank 600.
Command/ address inputs of memory chips (not shoWn in
inactive, then the transmission of command/ address signals
FIG. 4) of the seventh rank 700 and of the eighth rank 800 are coupled in parallel to the at least one third output 46 of the fourth register 40 for the transmission of command/address
signals to the memory chips (not shoWn in FIG. 4) of the seventh rank 700 and of the eighth rank 800. If an inactive level of the control signal CS GATE EN is
applied to each of the fourth inputs 17, 27, 37, 47 of the respective ?rst 10, second 20, third 30, fourth 40, ?fth 50, sixth 60, seventh 70 and eighth 80 registers, then the com mand/address signals CA applied to the at least one third input 13 of the ?rst register 10 are transmitted via the at least one third output 16 of the ?rst register 10 to the memory chips 3 of the ?rst rank 100 and of the second rank 200, the com mand/address signals CA applied to the at least one third input 23 of the second register 20 are transmitted via the at least one third output 26 of the second register 20 to the memory chips 3 of the third rank 300 and of the fourth rank
20
25
400, the command/address signals CA applied to the at least one third input 33 of the third register 30 are transmitted via the at least one third output 36 of the third register 30 to the
30
memory chips 3 of the ?fth rank 500 and of the sixth rank 600, the command/address signals CA applied to the at least one third input 43 of the fourth register 40 are transmitted via the at least one third output 46 of the fourth register 40 to the memory chips 3 of the seventh rank 700 and of the eighth rank
sixth 60, seventh 70 and eighth 80 registers, then the trans mission of command/address signals CA applied to respec tive at least one third inputs 13, 23, 33, 43 is dependent on the respective chip select signals CS0 to CS7. If at least one of the chip select signals CS0 and CS1 coupled respectively to the ?rst input 11 and the second input 12 of the ?rst register 10 is active, then the command/address signals CA are transmitted via the at least one third output 16 to the memory chips 3 of the ?rst rank 100 and of the second rank 200. If both chip select signals CS0 and CS1 are inactive, then the transmission of command/ address signals CA via the at least one third output 16 to the memory chips 3 of the ?rst rank 100 and of the second rank 200 is blocked. If at least one of the chip select signals CS2 and CS3
coupled respectively to the ?rst input 21 and the second input 22 of the second register 20 is active, then the command/
A respective ?rst rank 100, 500 and a respective second rank 200, 600 of memory chips (not shoWn in FIG. 5) are disposed on the respective ?rst surface S1, S1' of the respec tive circuit substrate 2, 2'. A respective third rank 300, 700 and a respective fourth rank 400, 800 of memory chips (not shoWn in FIG. 5) are disposed on the respective second surface S2, S2' of the respective circuit substrate 2, 2'.
Typically, memory chips (not shoWn in FIG. 5) are coupled 35
800. If an active level of the control signal CS GATE EN is
applied to each of the fourth input 17, 27, 37, 47 of the respective ?rst 10, second 20, third 30, fourth 40, ?fth 50,
CA via the at least one third output 46 to the memory chips 3 of the seventh rank 700 and of the eighth rank 800 is blocked. FIG. 5 depicts schematically a cross-sectional vieW of the semiconductor memory module 1 of the electronic apparatus of FIG. 4. The semiconductor memory module 1 includes a ?rst circuit substrate 2 and a second circuit substrate 2', each having a ?rst surface S1, S1' and a second surface S2, S2'. A ?rst register 10 is disposed on the ?rst surface S1 of the ?rst circuit substrate 2, a second register 20 is disposed on the second surface S2 of the ?rst circuit substrate 2, a third register 30 is disposed on the ?rst surface S1' of the second circuit substrate 2' and a fourth register 40 is disposed on the second surface S2' of the second circuit substrate 2'.
40
to respective circuit substrates by solder balls 80 to provide an electrical connection betWeen the memory chips and the cir cuit substrates. A connector 70 provides a connection betWeen the ?rst circuit substrate 2 and the second circuit substrate 2' for the transmission of electrical signals. The connector 70 includes a plug 70B disposed on the ?rst surface S1' of the second circuit substrate 2' and a socket 70A disposed on the second surface S2 of the ?rst circuit substrate 2. An edge connector 8 disposed on one end of the ?rst circuit
45
substrate 2 provides electrical connection betWeen the elec tronic apparatus and a bus system (not shoWn in FIG. 5) for the transmission of electrical signals betWeen an external device such as the controller device depicted in FIG. 4 and the electronic apparatus via a bus system.
50
What is claimed is: 1. A semiconductor memory module comprising: a circuit substrate; a ?rst, a second, a third and a fourth rank of memory chips 55
each rank including a plurality of memory chips and each being disposed on said circuit substrate;
address signals CA are transmitted via the at least one third
a ?rst register and a second register each disposed on said
output 26 to the memory chips 3 of the third rank 300 and of the fourth rank 400. If both chip select signals CS2 and CS3 are inactive, then the transmission of command/address sig
circuit substrate, said ?rst register and said second reg ister each comprising: a ?rst input for receiving [a] an associated ?rst chip
60
nals CA via the at least one third output 26 to the memory
select signal having one of an active or an inactive
chips 3 of the third rank 300 and of the fourth rank 400 is blocked. If at least one of the chip select signals CS4 and CS5
level;
coupled respectively to the ?rst input 31 and the second input 32 of the third register 30 is active, then the command/address signals CA are transmitted via the at least one third output 36
a second input for receiving [a other] an associated second chip select signal having one of an active or an 65
inactive level; at least one third input for receiving command/address
signals;
US RE43,162 E 14
13
5. The semiconductor memory module according to claim
a ?rst output coupled to transmit said associated ?rst chip select signal to said memory chips of said ?rst
4, Wherein said electrical signals comprise said associated
?rst chip select signals, said [other] associated second chip
rank [and] or said third rank, said?rst output of said ?rst register coupled to transmit said associated?rst chip select signal to said memory chips ofsaid?rst rank and said ?rst output of said second register coupled to transmit said associated ?rst chip select signal to said memory chips ofsaid third rank; a second output coupled to transmit said [other] associ ated second chip select signal to saidmemory chips of
select signals and said command/address signals. 6. The semiconductor memory module according to claim
1, Wherein each of said ?rst register and said second register comprises a fourth input for receiving a control signal having one of an active and an inactive level;
said at least one third output of said ?rst register coupled to transmit said command/address signals, if said control signal is active and if at least one of said associated?rst
said second rank [and] or said fourth rank, said sec
at
ond output of said ?rst register coupled to transmit
chip select signal received at said ?rst input of said ?rst
said associated second chip select signal to said memory chips ofsaid second rank and said second output ofsaid second register coupled to transmit said associated second chip select signal to said memory
register and said [other] associated second chip select signal received at said second input of said ?rst register
chips ofsaidfourth rank, and
?rst chip select signal received at said ?rst input of said ?rst register and said [other] associated second chip select signal received at said second input of said ?rst register are inactive;
is active, and to block said command/ address signals, if said control signal is active and if both said associated
least one third output for outputting command/ad dress signals, Wherein said at least one third output of said ?rst register is coupled to transmit said com
20
mand/address signals to said memory chips of said ?rst rank and to said memory chips of said second rank, if at least one of said associated?rst chip select signal received at said ?rst input of said ?rst register
and said [other] associated second chip select signal
said at least one third output of said ?rst register coupled to transmit said command/address signals, if said control
signal is inactive; 25
received at said second input of said ?rst register is active, and to block a transmission of said command/
address signals to said memory chips of said ?rst rank and to said memory chips of said second rank, if both said associated?rst chip select signal received at said ?rst input of said ?rst register and said [other] asso ciated second chip select signal received at said sec ond input of said ?rst register are inactive; and said at least one third output of said second register is coupled to transmit said command/ address signals to said memory chips of said third rank and to said memory chips of said fourth rank, if at least one of said associated?rst chip select signal received at said
30
35
40
7. The semiconductor memory module according to claim 1, Wherein said semiconductor module has a socket disposed on said circuit substrate, said semiconductor memory module
a ?fth, a sixth, a seventh, and an eighth rank of memory 45
chips each including a plurality of memory chips and each being disposed on said other circuit substrate; a third register and a fourth register each disposed on said
other circuit substrate, said third register and said fourth
register each comprising:
2. The semiconductor memory module according to claim 1, Wherein said circuit substrate has a ?rst surface and a
said second register are inactive; and said at least one third output of said second register coupled to transmit said command/address signals if said control
further comprising: another circuit substrate having a plug disposed thereon;
block a transmission of said command/address sig nals to said memory chips of said third rank and to
said memory chips of said fourth rank, if both said associated?rst chip select signal received at said ?rst input of said second register and said [other] associ ated second chip select signal received at said second input of said second register are inactive.
?rst chip select signal received at said ?rst input of said second register and said [other] associated second chip select signal received at said second input of said second register is active, and to block said command/address signals, if said control signal is active and if both said associated ?rst chip select signal received at said ?rst input of said second register and said [other] associated second chip select signal received at said second input of
signal is inactive.
?rst input of said second register and said [other] associated second chip select signal received at said second input of said second register is active, and to
said at least one third output of said second register coupled to transmit said command/address signals, if said con trol signal is active and if at least one of said associated
50
a ?rst input for receiving [a] an associated third chip
second surface, Wherein said ?rst register and said memory
select signal having one of an active or an inactive
chips of said ?rst rank are disposed on said ?rst surface and said memory chips of said second rank are stacked upon said
level;
memory chips of said ?rst rank, and Wherein said second register and said memory chips of said third
a second input for receiving [a] an associated fourth chip select signal having one of an active or an inactive 55
level;
rank are disposed on said second surface and said memory chips of said fourth rank are stacked upon said
at least one third input for receiving command/address
memory chips of said third rank. 3. The semiconductor memory module according to claim 1, Wherein said circuit substrate comprises an edge connector
a ?rst output coupled to transmit said associated third
signals; 60
chip select signal to said memory chips of said ?fth rank [and] or said seventh rank, said ?rst output of
having contacts for transmitting electrical signals betWeen
said third register coupled to transmit said associated
said circuit substrate and an external device.
third chip select signal to said memory chips ofsaid ?fth rank and said?rst output of said fourth register
4. The semiconductor memory module according to claim 3, Wherein ends of said contacts are coupled via respective conductive lines disposed on said circuit substrate to said ?rst input, to said second input and to said at least one third input
of each of said ?rst register and said second register.
coupled to transmit said associated third chip select 65
signal to said memory chips ofsaid seventh rank, a second output coupled to transmit said associated
fourth chip select signal to said memory chips of said
US RE43,162 E 15
16 said at least one third output of said fourth register coupled to transmit said command/address signals, if said con trol signal is active and if at least one of said associated third chip select signal received at said ?rst input of said
sixth rank [and] or said eighth rank, said second out put of said third register coupled to transmit said associated fourth chip select signal to said memory
chips ofsaid sixth rank and said second output ofsaid fourth register coupled to transmit said associated second chip select signal to said memory chips ofsaid
fourth register and said associated fourth chip select signal received at said second input of said fourth regis ter is active, and to block said command/address signals, if said control signal is active and if both said associated third chip select signal received at said ?rst input of said fourth register and said associated fourth chip select signal received at said second input of said fourth regis
eighth rank, and at least one third output, wherein said socket of said
circuit board and said plug of said other circuit board are coupled and provide an electrical connection for the transmission of said associated ?rst chip select
ter are inactive; and
[signal] signals, said [other] associated second chip
said at least one third output of said fourth register coupled to transmit said command/address signals if said control
select [signal] signals, said associated third chip select [signal] signals, said associated fourth chip select [signal] signals and said command/address [signal] signals betWeen said circuit board and said
signal is inactive. 1 0. The semiconductor memory module according to claim
1, Wherein said memory chips comprise dynamic random
other circuit board;
access memory chips. 1 1. The semiconductor memory module according to claim
said at least one third output of said third register is
coupled to transmit said command/ address signals, if at least one of said associated third chip select signal received at said ?rst input of said third register and said associated fourth chip select signal received at said second input of said third register is active, and to block said command/address signals, if both said associated third chip select signal received at said ?rst input of said third register and said associated fourth chip select signal received at said second input of said third register are inactive; and
20
25
13. An electronic apparatus comprising:
said at least one third output of said fourth register is
30
a controller device; a bus system; at least one semiconductor memory module comprising: a circuit substrate; a ?rst, a second, a third and a fourth rank of memory
coupled to transmit said command/ address signals, if at least one of said associated third chip select signal received at said ?rst input of said fourth register and said associated fourth chip select signal received at said second input of said fourth register is active, and to block said command/address signals, if both said associated third chip select signal received at said ?rst input of said fourth register and said associated fourth chip select signal received at said second input of said fourth register are inactive. 8. The semiconductor memory module according to claim
dual inline memory module.
chips each rank including a plurality of memory chips and each being disposed on said circuit substrate; a ?rst register and a second register each disposed on said circuit substrate, said ?rst register and said sec 35
receiving [a] an associated ?rst chip select signal having one of an active or an inactive level;
a second input coupled to said controller device for 40
device via said bus system for receiving command/
address signals; 45
said fourth register, saidmemory chips of said seventh rank and said memory chips of said eighth rank are disposed on said second surface.
9. The semiconductor memory module according to claim 50
one of an active and an inactive level;
said at least one third output of said third register coupled to transmit said command/address signals, if said con trol signal is active and if at least one of said associated third chip select signal received at said ?rst input of said
55
60
ciated second chip select signal to said memory chips of said second rank [and] or said fourth rank,
said second output of said first register coupled to transmit said associated second chip select signal only to said memory chips ofsaid second rank and said second output ofsaid second register coupled to transmit said associated second chip select sig
nal only to said memory chips ofsaidfourth rank;
nal received at said second input of said third register are
inactive; trol signal is inactive;
rank [and] or said third rank, said ?rst output of said first register coupled to transmit said associ ated?rst chip select signal to said memory chips of said?rst rank and said?rst output ofsaid second register coupled to transmit said associated ?rst chip select signal to said memory chips ofsaid third
rank;
third register and said associated fourth chip select sig said at least one third output of said third register coupled to transmit said command/address signals, if said con
a ?rst output coupled to transmit said associated?rst chip select signal to said memory chips of said ?rst
a second output coupled to transmit said [other] asso
third register and said associated fourth chip select sig nal received at said second input of said third register is active, and to block said command/address signals, if said control signal is active and if both said associated third chip select signal received at said ?rst input of said
receiving [a other] an associated second chip select signal having one of an active or an inactive level; at least one third input coupled to said controller
second surface, Wherein said third register, said memory chips of said ?fth rank and said memory chips of said sixth
7, Wherein each of said third register and said fourth register comprises a fourth input for receiving a control signal having
ond register each comprising: a ?rst input coupled to said controller device for
7, Wherein said other circuit substrate has a ?rst surface and a
rank are disposed on said ?rst surface, and Wherein
1, Wherein said memory chips comprise synchronous dynamic random access memory chips. 12. The semiconductor memory module according to claim 1, Wherein said semiconductor memory module comprises a
65
and at least one third output for outputting command/ address signals, Wherein said at least one third output of said ?rst register is coupled to transmit said command/ address signals to said memory
US RE43,162 E 17
18
chips of said ?rst rank and to said memory chips of
?rst register and said [other] associated second chip
said second rank, if at least one of said associated
select signal received at said second input of said ?rst register are inactive;
?rst chip select signal received at said ?rst input of said ?rst register and said [other] associated second chip select signal received at said second input of
said at least one third output of said ?rst register coupled to transmit said command/address signals, if said control
signal is inactive;
said ?rst register is active, and to block a transmis sion of said command/address signals to said memory chips of said ?rst rank and to said memory
said at least one third output of said second register coupled to transmit said command/address signals, if said con trol signal is active and if at least one of said associated
chips of said second rank, if both said associated ?rst chip select signal received at said ?rst input of said ?rst register and said [other] associated second chip select signal received at said second input of
?rst chip select signal received at said ?rst input of said second register and said [other] associated second chip select signal received at said second input of said second register is active, and to block said command/address signals, if said control signal is active and if both said associated ?rst chip select signal received at said ?rst input of said second register and said [other] associated second chip select signal received at said second input of
said ?rst register are inactive; and said at least one third output of said second register is
coupled to transmit said command/address signals to said memory chips of said third rank and to said memory chips of said fourth rank, if at least one of
said associated ?rst chip select signal received at said ?rst input of said second register and said
20
[other] associated second chip select signal
signal is inactive. 19. The electronic apparatus according to claim 13,
received at said second input of said second register is active, and to block a transmission of said com
mand/address signals to said memory chips of said third rank and to said memory chips of said fourth
Wherein said semiconductor module has a socket disposed on 25
received at said ?rst input of said second register
a ?fth, a sixth, a seventh, and an eighth rank of memory
and said [other] associated second chip select sig 30
other circuit substrate, said third register and said fourth
register each comprising:
surface, Wherein said ?rst register and said memory chips of
a ?rst input coupled to said controller device for receiv 35
ing [a] an associated third chip select signal having one of an active or an inactive level;
memory chips of said ?rst rank, and Wherein said second register and said memory chips of said third rank are disposed on said second surface and said memory chips of said fourth rank are stacked upon said
chips each including a plurality of memory chips and each being disposed on said other circuit substrate; a third register and a fourth register each disposed on said
Wherein said circuit substrate has a ?rst surface and a second
said ?rst rank are disposed on said ?rst surface and said memory chips of said second rank are stacked upon said
said circuit substrate, said semiconductor memory module
further comprising: another circuit substrate having a plug disposed thereon;
rank, if both said associated?rst chip select signal nal received at said second input of said second register are inactive. 14. The electronic apparatus according to claim 13,
said second register are inactive; and said at least one third output of said second register coupled to transmit said command/address signals if said control
a second input coupled to said controller device for
receiving [a] an associated fourth chip select signal having one of an active or an inactive level; 40
memory chips of said third rank. 15. The electronic apparatus according to claim 13, Wherein said circuit substrate comprises an edge connector
at least one third input coupled to said controller device
via said bus system for receiving command/address
signals; a ?rst output coupled to transmit said associated third
having contacts for transmitting electrical signals betWeen
chip select signal to said memory chips of said ?fth rank [and] or said seventh rank, said ?rst output of
said circuit substrate and an external device.
16. The electronic apparatus according to claim 15,
said third register coupled to transmit said associated
Wherein ends of said contacts are coupled via respective con ductive lines disposed on said circuit substrate to said ?rst input, to said second input and to said at least one third input
third chip select signal only to said memory chips of said??h rank and said?rst output of said fourth
of each of said ?rst register and said second register. 17. The electronic apparatus according to claim 16,
register coupled to transmit said associated third chip 50
Wherein said electrical signals comprise said associated?rst chip select signals, said [other] associated second chip select signals and said command/address signals. 18. The electronic apparatus according to claim 13, Wherein each of said ?rst register and said second register comprises a fourth input for receiving a control signal having
a second output coupled to transmit said associated
55
associated fourth chip select signal only to said
60
chip select signal received at said ?rst input of said ?rst
?rst chip select signal received at said ?rst input of said
memory chips ofsaid eighth rank; and at least one third output, Wherein said socket of said
circuit board and said plug of said other circuit board are coupled and provide an electrical connection for
register and said [other] associated second chip select signal received at said second input of said ?rst register is active, and to block said command/ address signals, if said control signal is active and if both said associated
fourth chip select signal to said memory chips of said sixth rank [and] or said eighth rank, said second out put of said third register coupled to transmit said memory chips of said sixth rank and said second output ofsaidfourth register coupled to transmit said associated second chip select signal only to said
one of an active and an inactive level;
said at least one third output of said ?rst register coupled to transmit said command/address signals, if said control signal is active and if at least one of said associated?rst
selectsignal only to saidmemory chips ofsaidseventh rank,
the transmission of said associated ?rst chip select 65
[signal] signals, said [other] associated second chip select [signal] signals, said associated third chip select [signal] signals, said associated fourth chip
US RE43,162 E 19
20
select [signal] signals and said command/address [signal] signals between said circuit board and said other circuit board;
22. The electronic apparatus according to claim 13,
Wherein said memory chips comprise dynamic random access memory chips.
said at least one third output of said third register is
23. The electronic apparatus according to claim 13,
coupled to transmit said command/ address signals, if at least one of said associated third chip select signal received at said ?rst input of said third register and said associated fourth chip select signal received at said second input of said third register is active, and to block said command/address signals, if both said associated third chip select signal received at said ?rst input of said third register and said associated fourth chip select signal received at said second input of said third register are inactive; and
Wherein said memory chips comprise synchronous dynamic random access memory chips.
24. The electronic apparatus according to claim 13, Wherein said semiconductor memory module comprises a dual inline memory module. 25. A method of operating a semiconductor memory mod
ule, said method comprising: providing a semiconductor memory module comprising: a circuit substrate; a ?rst, a second, a third and a fourth rank of memory
said at least one third output of said fourth register is
chips each rank including a plurality of memory chips and each being disposed on said circuit substrate;
coupled to transmit said command/ address signals, if at least one of said associated third chip select signal received at said ?rst input of said fourth register and said associated fourth chip select signal received at said second input of said fourth register is active, and to block said command/address signals, if both said associated third chip select signal received at said ?rst input of said fourth register and said associated fourth chip select signal received at said second input of said
20
fourth register are inactive.
25
a ?rst register and a second register each disposed on said circuit substrate, said ?rst register and said sec
a ?rst input for receiving [a] an associated ?rst chip select signal having one of an active or an inactive
level; a second input for receiving [a other] an associated
20. The electronic apparatus according to claim 19, Wherein said other circuit substrate has a ?rst surface and a
30
said fourth register, saidmemory chips of said seventh rank and said memory chips of said eighth rank are disposed 35
said third rank, a second output coupled to transmit said [other] asso 40
45
and at least one third output for outputting command/
nal received at said second input of said third register are
address signals;
inactive; 50
fourth register and said associated fourth chip select signal received at said second input of said fourth regis ter is active, and to block said command/address signals, if said control signal is active and if both said associated third chip select signal received at said ?rst input of said fourth register and said associated fourth chip select signal received at said second input of said fourth regis
transmitting said command/ address signals to said 55
60
signal is inactive.
memory chips of said ?rst rank and to said memory chips of said second rank via said at least one third output of said ?rst register if at least one of said
associated ?rst chip select signal received at said ?rst input of said ?rst register and said [other] asso ciated second chip select signal received at said second input of said ?rst register is active, and to block a transmission of said command/ address sig nals to said memory chips of said ?rst rank and to
ter are inactive; and
said at least one third output of said fourth register coupled to transmit said command/ address signals if said control
determining if one of said associated?rst chip select signals and one of said [other] associated second
chip select signals is active;
trol signal is inactive; said at least one third output of said fourth register coupled to transmit said command/address signals, if said con trol signal is active and if at least one of said associated third chip select signal received at said ?rst input of said
to transmit said associated second chip select sig
nal only to said memory chips ofsaidfourth rank;
third register and said associated fourth chip select sig said at least one third output of said third register coupled to transmit said command/address signals, if said con
ciated second chip select signal to said memory chips of said second rank [and] or said fourth rank,
said second output of said first register coupled to transmit said associated second chip select signal only to said memory chips ofsaid second rank and said second output ofsaid second register coupled
third register and said associated fourth chip select sig nal received at said second input of said third register is active, and to block said command/address signals, if said control signal is active and if both said associated third chip select signal received at said ?rst input of said
second register coupled to transmit said associated
?rst chip select signal only to said memory chips of
one of an active and an inactive level;
said at least one third output of said third register coupled to transmit said command/address signals, if said con trol signal is active and if at least one of said associated third chip select signal received at said ?rst input of said
a ?rst output coupled to transmit said associated?rst chip select signal to said memory chips of said ?rst
rank [and] or said third rank, said ?rst output of said first register coupled to transmit said associ ated?rst chip select signal only to said memory chips ofsaid?rst rank and said?rst output or said
on said second surface.
21. The electronic apparatus according to claim 19, Wherein each of said third register and said fourth register comprises a fourth input for receiving a control signal having
second chip select signal having one of an active or an inactive level; at least one third input for receiving command/ad
dress signals;
second surface, Wherein said third register, said memory chips of said ?fth rank and said memory chips of said sixth rank are disposed on said ?rst surface, and Wherein
ond register each comprising:
65
said memory chips of said second rank, if both said associated ?rst chip select signal received at said ?rst input of said ?rst register and said [other] asso ciated second chip select signal received at said second input of said ?rst register are inactive; and
US RE43,162 E 21
22 second chip select signal received at said second input of said second register are inactive; and said at least one third output of said second register coupled
transmitting said command/address signals via said at least one third output of said second register to said memory chips of said third rank and to said memory chips of said fourth rank, if at least one of
said associated ?rst chip select signal received at said ?rst input of said second register and said
to transmit said command/address signals if said control
signal is inactive.
5
31. The method according to claim 25, Wherein said semi
[other] associated second chip select signal
conductor module has a socket disposed on said circuit sub
received at said second input of said second register
strate, said semiconductor memory module further compris
is active, and to block a transmission of said com
ing: another circuit substrate having a plug disposed thereon;
mand/address signals to said memory chips of said third rank and to said memory chips of said fourth
a ?fth, a sixth, a seventh, and an eighth rank of memory
rank, if both said associated?rst chip select signal
chips each including a plurality of memory chips and each being disposed on said other circuit substrate;
received at said ?rst input of said second register
and said [other] associated second chip select sig nal received at said second input of said second register are inactive. 26. The method according to claim 25, Wherein said circuit
a third register and a fourth register each disposed on said 15
other circuit substrate, said third register and said fourth
register each comprising: a ?rst input for receiving [a] an associated third chip
substrate has a ?rst surface and a second surface, Wherein said
select signal having one of an active or an inactive
?rst register and said memory chips of said ?rst rank are disposed on said ?rst surface and said memory chips of said second rank are stacked upon said memory chips of said ?rst
level; 20
select signal having one of an active or an inactive
rank, and Wherein said second register and said memory chips of said third rank are disposed on said second surface and said memory chips of said fourth rank are stacked upon said
a second input for receiving [a] an associated fourth chip
level; at least one third input for receiving command/address
signals; 25
a ?rst output coupled to transmit said associated third
chip select signal to said memory chips of said ?fth rank [and] or said seventh rank, said ?rst output of
memory chips of said third rank. 27. The method according to claim 25, Wherein said circuit substrate comprises an edge connector having contacts for
said third register coupled to transmit said associated
transmitting electrical signals betWeen said circuit substrate
third chip select signal only to said memory chips of said ?fth rank and said first output of said fourth
and an external device.
28. The method according to claim 27, Wherein ends of said
register coupled to transmit said associated third chip
contacts are coupled via respective conductive lines disposed
selectsignal only to saidmemory chips ofsaidseventh rank,
on said circuit substrate to said ?rst input, to said second input and to said at least one third input of each of said ?rst register
and said second register. 29. The method according to claim 28, Wherein said elec
a second output coupled to transmit said associated 35
trical signals comprise said chip select signals, said other chip select signals and said command/address signals.
associated fourth chip select signal only to said
30. The method according to claim 25, Wherein each of said
?rst register and said second register comprises a fourth input
40
for receiving a control signal having one of an active and an
at least one third output, Wherein said socket of said 45
chip select signal received at said ?rst input of said ?rst
[signal] signals, said [other] associated second chip 50
?rst chip select signal received at said ?rst input of said ?rst register and said [other] associated second chip select signal received at said second input of said ?rst register are inactive; said at least one third output of said ?rst register coupled to transmit said command/address signals, if said control
?rst chip select signal received at said ?rst input of said second register and said [other] associated second chip select signal received at said second input of said second register is active, and to block said command/address signals, if said control signal is active and if both said associated ?rst chip select signal received at said ?rst input of said second register and said [other] associated
select [signal] signals, said associated third chip select [signal] signals, said associated fourth chip select [signal] signals and said command/address [signal] signals betWeen said circuit board and said other circuit board; said at least one third output of said third register is coupled to transmit said command/ address signals, if at least one
55
signal is inactive; said at least one third output of said second register coupled to transmit said command/address signals, if said con trol signal is active and if at least one of said associated
circuit board and said plug of said other circuit board are coupled and provide an electrical connection for
the transmission of said associated ?rst chip select
register and said [other] associated second chip select signal received at said second input of said ?rst register is active, and to block said command/ address signals, if said control signal is active and if both said associated
memory chips of said sixth rank and said second output ofsaidfourth register coupled to transmit said associated second chip select signal only to said
memory chips ofsaid eighth rank; and
inactive level; said at least one third output of said ?rst register coupled to transmit said command/address signals, if said control signal is active and if at least one of said associated?rst
fourth chip select signal to said memory chips of said sixth rank [and] or said eighth rank, said second out put of said third register coupled to transmit said
60
65
of said associated third chip select signal received at said ?rst input of said third register and said associated fourth chip select signal received at said second input of said third register is active, and to block said command/ address signals, if both said associated third chip select signal received at said ?rst input of said third register and said associated fourth chip select signal received at said second input of said third register are inactive; and said at least one third output of said fourth register is coupled to transmit said command/address signals, if at least one of said associated third chip select signal received at said ?rst input of said fourth register and said associated fourth chip select signal received at said sec
US RE43,162 E 24
23 ond input of said fourth register is active, and to block said command/address signals, if both said associated third chip select signal received at said ?rst input of said fourth register and said associated fourth chip select signal received at said second input of said fourth regis
a second inputfor receiving an associated second chip select signal having one ofan active or an inactive
level; at least one third input for receiving command/address
signals; a first output coupled to transmit said associated ?rst
ter are inactive.
32. The method according to claim 31, Wherein said other
chip select signal to said memory chips ofsaid?rst
rank;
circuit substrate has a ?rst surface and a second surface,
Wherein said third register, said memory chips of said ?fth
a second output coupled to transmit said associated
rank and said memory chips of said sixth rank are disposed on
second chip select signal to said memory chips ofsaid second rank; and
said ?rst surface, and Wherein
said fourth register, saidmemory chips of said seventh rank and said memory chips of said eighth rank are disposed
at least one third output for outputting command/ad dress signals coupled to transmit said command/ad
dress signals to said memory chips ofsaid?rst rank and to said memory chips ofsaid second rank, ifat least one signal ofa group ofsignals consisting of(]) said associated?rst chip select signal received at said
on said second surface.
33. The method according to claim 3 1, Wherein each of said
third register and said fourth register comprises a fourth input for receiving a control signal having one of an active and an
first input ofsaidfirst register and (2) said associated
inactive level; said at least one third output of said third register coupled to transmit said command/address signals, if said con trol signal is active and if at least one of said associated third chip select signal received at said ?rst input of said
20
third register and said associated fourth chip select sig nal received at said second input of said third register is active, and to block said command/address signals, if said control signal is active and if both said associated third chip select signal received at said ?rst input of said
25
ister are inactive; and
a second register disposed on said circuit substrate, said 30
said at least one third output of said third register coupled
signal having one ofan active or an inactive level; a second inputfor receiving an associated second chip
to transmit said command/address signals, if said con
trol signal is inactive;
fourth register and said associated fourth chip select signal received at said second input of said fourth regis ter is active, and to block said command/address signals, if said control signal is active and if both said associated third chip select signal received at said ?rst input of said fourth register and said associated fourth chip select signal received at said second input of said fourth regis
select signal having one ofan active or an inactive 35
signals; a first output coupled to transmit said associated ?rst
chip select signal to said memory chips ofsaid third 40
second chip select signal to said memory chips ofsaid
fourth rank; and at least one third output coupled to transmit said com 45
50
chips. memory chips comprise synchronous dynamic random 55
60
said second register are inactive. 38. The semiconductor memory module according to claim 37, wherein said circuit substrate has a?rst surface and a
second surface, wherein said first register and said memory chips ofsaidfirst rank are disposed on saidfirst surface and
a?rst, a second, a third and afourth rank ofmemory chips each rank including a plurality of memory chips and each being disposed on said circuit substrate; a first register disposed on said circuit substrate, saidfirst signal having one ofan active or an inactive level;
said memory chips ofsaidfourth rank, ifboth said associated?rst chip select signal received at saidfirst input ofsaid second register and said associated sec ond chip select signal received at said second input of
36. The method according to claim 25, Wherein said semi conductor memory module comprises a dual inline memory module. 37. A semiconductor memory module comprising:
a first input for receiving an associated?rst chip select
received at saidfirst input ofsaid second register and (2) said associated second chip select signal received at said second input of said second register is active, and to blocka transmission ofsaid command/address signals to said memory chips ofsaid third rankand to
35. The method according to claim 25, Wherein said
register comprising:
mand/address signals to said memory chips ofsaid third rank and to said memory chips ofsaidfourth rank, ifat least one signal ofa group ofsignals con
sisting of(]) said associated?rst chip select signal
signal is inactive.
a circuit substrate;
rank; a second output coupled to transmit said associated
said at least one third output of said fourth register coupled to transmit said command/ address signals if said control
access memory chips.
level; at least one third input for receiving command/address
ter are inactive; and
34. The method according to claim 25, Wherein said memory chips comprise dynamic random access memory
second register comprising: a first input for receiving an associated?rst chip select
inactive;
said at least one third output of said fourth register coupled to transmit said command/address signals, if said con trol signal is active and if at least one of said associated third chip select signal received at said ?rst input of said
chips ofsaid second rank, ifboth said associated?rst chip select signal received at said?rst input ofsaid first register and said associated second chip select signal received at said second input of saidfirst reg
third register and said associated fourth chip select sig nal received at said second input of said third register are
second chip select signal received at said second input of said first register is active, and to block a transmission ofsaid command/address signals to said memory chips ofsaid?rst rank and to said memory
said memory chips ofsaid second rank are stacked upon said
memory chips of said first rank, and wherein said second 65
register andsaidmemory chips ofsaid third rankare disposed on said second surface and said memory chips ofsaidfourth rank are stacked upon said memory chips ofsaid third ranlc
US RE43,162 E 25
26 a second input for receiving an associated fourth chip
39. The semiconductor memory module according to claim 3 7, wherein said circuit substrate comprises an edge connec
select signal having one ofan active or an inactive
level;
tor having contacts for transmitting electrical signals between said circuit substrate and an external device.
at least one third input for receiving command/address
40. The semiconductor memory module according to claim 39, wherein ends of said contacts are coupled via respective conductive lines disposed on said circuit substrate to saidfirst
a first output coupled to transmit said associated third
signals; chip select signal to said memory chips ofsaid?fth
rank;
input, to said second input and to said at least one third input
a second output coupled to transmit said associated
of each ofsaidfirst register and said second register
fourth chip select signal to said memory chips ofsaid
4]. The semiconductor memory module according to claim
sixth rank; and
40, wherein said electrical signals comprise said associated ?rst chip select signals, said associated second chip select signals and said command/address signals.
at least one third output coupled to transmit said com
mand/address signals to said ?fth and sixth rank of memory chips, ifat least one signal ofa group of
42. The semiconductor memory module according to claim
signals consisting of (I) said associated third chip
3 7, wherein said first register and said second register each further comprises a fourth inputfor receiving a control signal
select signal received at said?rst input ofsaid third register and (2) said associated fourth chip select signal received at said second input of said third
having one ofan active and an inactive level;
wherein, when said control signal is active, said first reg ister couples said at least one third output ofsaid?rst register to transmit said command/address signals to
said?rst and second rankofmemory chips when at least one signal ofa group ofsignals consisting of(]) said associated ?rst chip select signal received at said first input ofsaidfirst register and (2) said associated second chip select signal received at said second input ofsaid first register is active and blocks said command/address signals from being transmitted to said first and second rank of memory chips when both said associated ?rst chip select signal received at saidfirst input ofsaidfirst register and said associated second chip select signal received at said second input of said first register are inactive, and, when said control signal is inactive, said first register couples said at least one third output ofsaid first register to transmit said command/address signals to saidfirst and second rank of memory chips; and wherein, when said control signal is active, said second register couples said at least one third output of said
register is active and to block said command/address 20
signalsfrom being transmitted to said?fth and sixth rank ofmemory chips, ifboth said associated third chip select signal received at said?rst input ofsaid third register and said associated fourth chip select signal received at said second input of said third
25
register are inactive; and a fourth register disposed on said other circuit substrate
comprising: a first inputfor receiving an associated third chip select signal having one ofan active or an inactive level; 30
select signal having one ofan active or an inactive
level; at least one third input for receiving command/address
signals; 35
rank and said seventh rank; a second output coupled to transmit said associated
fourth chip select signal to said memory chips ofsaid 40
sixth rank and said eighth rank; and at least one third output coupled to transmit said com
mand/address signals to said seventh and eighth rank
first input ofsaid second register and (2) said associated second chip selectsignal received at said second input of said second register is active and blocks said command/
a first output coupled to transmit said associated third
chip select signal to said memory chips ofsaid?fth
second register to transmit said command/address sig
nals to said third andfourth rank ofmemory chips when at least one signal ofa group ofsignals consisting of(]) said associated ?rst chip select signal received at said
a second input for receiving an associated fourth chip
45
address signalsfrom being transmitted to said third and fourth rank of memory chips when both said associated
ofmemory chips, ifat least one signal ofa group of signals consisting of (I) said associated third chip select signal received at saidfirst input ofsaidfourth register and (2) said associated fourth chip select signal received at said second input of saidfourth
?rst chip select signal received at saidfirst input ofsaid
register is active and to block said command/address
second register and said associated second chip select signal received at said second input ofsaid second reg
signals from being transmitted to said seventh and 50
ister are inactive, and, when said control signal is inac tive, said second register couples said at least one third output ofsaid second register to transmit said command/
select signal received at said second input of said fourth register are inactive; wherein said socket ofsaid circuit board and saidplug of
address signals to said third andfourth rank ofmemory
chips. 43. The semiconductor memory module according to claim 3 7, wherein said semiconductor module has a socket disposed on said circuit substrate, said semiconductor memory module
said other circuit board are coupled and provide an electrical connection for the transmission of said asso
ciated?rst chip select signals, said associated second
chip select signals.
further comprising: another circuit substrate having a plug disposed thereon; a ?fth, a sixth, a seventh, and an eighth rank of memory
chips each including a plurality of memory chips and
eighth rank ofmemory chips, ifboth said associated third chip select signal received at said?rst input of said fourth register and said associated fourth chip
60
44. The semiconductor memory module according to claim 43, wherein said other circuit substrate has afirst surface and a second surface, wherein said third register, said memory
each being disposed on said other circuit substrate;
chips ofsaid?fth rank and said memory chips ofsaid sixth
a third register disposed on said other circuit substrate
rank are disposed on said first surface, and wherein said
comprising: a first inputfor receiving an associated third chip select signal having one ofan active or an inactive level;
65 fourth register, said memory chips of said seventh rank and said memory chips ofsaid eighth rank are disposed on said
second surface.
US RE43,162 E 27
28 nals to said seventh and eighth rank ofmemory chips when at least one signal ofa group ofsignals consisting of(]) said associated?rst chip select signal received at saidfirst input ofsaidfourth register and (2) said asso ciated second chip select signal received at said second input of said fourth register is active and blocks said command/address signals from being transmitted to said seventh and eighth rankofmemory chips when both said associated ?rst chip select signal received at said
45. The semiconductor memory module according to claim
43, wherein said third register and said fourth register each comprises a fourth inputfor receiving a control signal having one ofan active and an inactive level;
wherein, when said control signal is active, said third reg- 5 ister couples said at least one third output ofsaid third register to transmit said command/address signals to
said?fth and sixth rank ofmemory chips when at least one signal ofa group ofsignals consisting of(]) said associated ?rst chip select signal received at sald?rst input of said third register and (2) said associated second chip select signal received at said second input of .
.
.
.
.
first input of said fourth register and said associated second chip selectsignal received atsaid second input of
10
.
.
.
.
.
saidfourth register are inactive, and, when said control signal is inactive, said fourth register couples said at
said third register is active and blocks said command/ address signalsfrom being transmitted to said?fth and 15 sixth rank ofmemory chips when both said associated
least one third Output ofsaidfourth register to transmit Said Command/address Signals l0 Said Sevenlh and eighth milk ofmemol’y ChlPS' '
?rst chip select signal received at said?rst input ofsaid third register and said associated second chip select
3746'hThe femlcsnducwr mehryfory moduhe ailcordmg Z0 cljlm 1 W erem Sal memory 0 1P3 comprlse ynamlc m” 0m
signal received at said second input ofsaid third register
(1026;325:662:Orig/cg;153cm}, memor module accordin [0 claim
are inactive, and, when said control signal is inactive, 20 .
.
.
.
.
said third register couples said at least one third output .
.
.
.
.
' 37,
_
wherein
_
_
_
said memory
chips
_
g
comprise synchronous
dynamic random access memory chips.
ofsaid third register to transmit said command/address 'lt slgnfl S 0 ml~dthd'th an Slx .mn k .OfmemOry ch"d .lps’ an wherein, when said control signal is active, saidfourth
48 The Semiconductor memory module according to claim ~~ . . 37, wherein saidsemiconductor memory module comprisesa dual inline memo module register couples said at least one third output ofsaid 25 W '
fourth register to transmit said command/address sig
*
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