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UNITED STATES DISTRICT COURT FOR THE EASTERN DISTRICT OF TEXAS MARSHALL DIVISION LONE STAR SILICON INNOVATIONS LLC, Plaintiff,
Civil Action No. 2:16-cv-1170
v.
JURY TRIAL DEMANDED
TOSHIBA CORPORATION, TOSHIBA AMERICA, INC., TOSHIBA AMERICA ELECTRONICS COMPONENTS, INC., SANDISK CORPORATION, and WESTERN DIGITAL CORPORATION, Defendants.
COMPLAINT FOR PATENT INFRINGEMENT Plaintiff, Lone Star Silicon Innovations LLC, complains against Defendants Toshiba Corporation, Toshiba America, Inc., Toshiba America Electronics Components, Inc., SanDisk Corporation, and Western Digital Corporation (collectively “Defendants”) as follows: NATURE OF ACTION 1.
This is an action for patent infringement of United States Patent Nos. 5,912,188;
6,023,085; 6,388,330; and Reissue No. 39,518 (collectively, the “Patents in Suit”) under the Patent Laws of the United States, 35 U.S.C. § 1, et seq. THE PARTIES 2.
Plaintiff Lone Star Silicon Innovations LLC (“Lone Star”) is a corporation
organized and existing under the laws of the State of Texas with its principle place of business at
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8105 Rasor Blvd., Suite 210, Plano, Texas, 75024. Lone Star is in the business of licensing patented technology. Lone Star is the assignee of the Patents in Suit. 3.
Toshiba Corporation (“Toshiba”) is a Japanese multinational company with its
principal place of business at 1-1, Shibaura 1-chome, Minato-ku, Tokyo 105-8001, Japan. Toshiba Corporation conducts business in and is doing business in Texas and in this District and elsewhere in the United States, including, without limitation, using, promoting, offering to sell, importing and/or selling memory devices and/or devices that incorporate memory devices that embody the patented technology, and enabling end-user purchasers to use such devices in this District. 4.
Toshiba America, Inc. (“Toshiba America”) is a corporation organized under the
laws of the state of Delaware with its principal place of business at 1251 Avenue of the Americas, Suite 4110, New York, NY 10020. Toshiba America’s registered agent for service of process in the State of Texas is CT Corporation System, located at 1999 Bryan St., Ste. 900, Dallas, TX 75201. Upon information and belief, Toshiba America is a wholly-owned subsidiary of Toshiba. Defendant Toshiba America conducts business in and is doing business in Texas and in the District and elsewhere in the United States, including, without limitation, using, promoting, offering to sell, importing and/or selling memory devices and/or devices that incorporate memory devices that embody patented technology, and enabling end-user purchasers to use such devices in this District. 5.
Toshiba America Electronic Components, Inc. (“TAEC”) is a corporation
organized under the laws of the State of California with principal places of business at 9740 Irvine Blvd, Suite D700, Irvine, CA 92618. TAEC’s registered agent for service of process in the State of Texas is CT Corporation System, located at 1999 Bryan St., Ste. 900, Dallas, TX 75201.
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Upon information and belief, TAEC is a wholly-owned subsidiary of Toshiba America. TAEC conducts business in and is doing business in Texas and in the District and elsewhere in the United States, including, without limitation, using, promoting, offering to sell, importing and/or selling memory devices and/or devices that incorporate memory devices that embody patented technology, and enabling end-user purchasers to use such devices in this District. 6.
Upon information and belief, Toshiba Corporation controls and is the majority
owner of Toshiba America and TAEC and these defendants are joint tortfeasors with one another with respect to the matters alleged herein. 7.
SanDisk Corporation (“SanDisk”) is a corporation organized under the laws of the
State of Delaware having a principal place of business at 951 Sandisk Drive, Milpitas, California 95035. SanDisk’s registered agent for service of process in the State of Texas is CT Corporation System, 1999 Bryan St., Suite 900, Dallas, Texas 75201. SanDisk conducts business in and is doing business in Texas and in this District and elsewhere in the United States, including, without limitation, using, promoting, offering to sell, importing and/or selling memory devices and/or devices that incorporate memory devices that embody the patented technology, and enabling end-user purchasers to use such devices in this District. 8.
Western Digital Corporation (“Western Digital”) is a corporation organized under
the laws of the State of Delaware having a principal place of business at 3355 Michelson Drive, Suite 100, Irvine, California 92612. Western Digital, by itself and through its subsidiaries, conducts business in and is doing business in Texas and in this District and elsewhere in the United States, including, without limitation, using, promoting, offering to sell, importing and/or selling memory devices and/or devices that incorporate memory devices that embody the patented technology, and enabling end-user purchasers to use such devices in this District.
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9.
Upon information and belief, in May 2016, SanDisk was acquired by Western
Digital pursuant to a merger agreement dated October 21, 2015 (the “Merger Agreement”). Upon information and belief, pursuant to the Merger Agreement, SanDisk continues as a wholly owned subsidiary of Western Digital Technologies, Inc., which is a wholly owned subsidiary of Western Digital. Western Digital refers to SanDisk as one of its brands. 10.
Upon information and belief, subsequent to the acquisition, Western Digital and
SanDisk are joint tortfeasors with one another with respect to the matters alleged herein. JURISDICTION AND VENUE 11.
This action arises under the Patent Laws of the United States, Title 35 of the
United States Code. This Court has subject matter jurisdiction over this action pursuant to 28 U.S.C. §§ 1331 and 1338(a). 12.
On information and belief, Defendants are subject to this Court’s specific and
general personal jurisdiction pursuant to due process and/or the Texas Long Arm Statute, due at least to their substantial business conducted in this forum, directly and/or through intermediaries, including (i) having solicited business in the State of Texas, transacted business within the State of Texas and attempted to derive financial benefit from residents of the State of Texas, including benefits directly related to the instant patent infringement causes of action set forth herein; (ii) having placed their products and services into the stream of commerce throughout the United States and having been actively engaged in transacting business in Texas and in this District; and (iii) either alone or in conjunction with others, having committed acts of infringement within Texas and in this District. On information and belief, within this district Defendants, directly and/or through intermediaries, have advertised (including through websites), offered to sell, sold and/or distributed infringing products, and/or have induced the sale and use of infringing
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products in the United States and in Texas. Each Defendant has, directly or through its distribution network, purposefully and voluntarily placed such products in the stream of commerce knowing and expecting them to be purchased and used by consumers in Texas. Each Defendant has either committed direct infringement in Texas or committed indirect infringement based on acts of direct infringement in Texas. Further, on information and belief, Defendants are subject to this Court’s general jurisdiction, including from regularly doing or soliciting business, engaging in other persistent courses of conduct, and/or deriving substantial revenue from goods and services provided to individuals in Texas and in this District. 13.
On information and belief, Defendants do one or more of the following with
memory devices and/or devices that incorporate memory devices that embody the patented technology that they or their foundries manufacture: (a) make these devices in the United States for sale to customers, including customers in Texas; (b) import these devices into the United States for sale to consumers, including consumers in Texas; (c) sell them or offer them for sale in the United States, including to customers in Texas; and/or (d) sell them to customers who incorporate them into products that such customers import, sell or offer for sale in the United States, including in Texas. 14.
Venue lies in this District pursuant to 28 U.S.C. §§ 1391(b), 1391(c) and 1400(b)
because each Defendant is subject to personal jurisdiction in this District, resides in, has regularly conducted business in this District and/or has committed acts of patent infringement in this District. Without limitation, on information and belief, within this District Defendants, directly and/or through intermediaries, have advertised (including through websites), offered to sell, sold and/or distributed infringing products, and/or have induced the sale and use of infringing products.
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THE PATENTS IN SUIT 15.
On June 15, 1999, U.S. Patent No. 5,912,188 (“the ’188 patent”), entitled
“Method Of Forming A Contact Hole In An Interlevel Dielectric Layer Using Dual Etch Stops,” a copy of which is attached hereto as Exhibit A, was duly and legally issued. The ’188 patent issued from U.S. patent application Serial Number 08/905,686 filed August 4, 1997 and discloses and relates to the design of and processes for fabricating semiconductor memory devices. The inventors assigned all right, title, and interest in the ’188 patent to Advanced Micro Devices, Inc. (hereinafter “AMD”). AMD assigned its entire right, title, and interest in the ’188 patent to Lone Star, and Lone Star is the sole owner of all rights, title and interest in and to the ’188 patent including the right to sue for and collect past, present and future damages and to seek and obtain injunctive or any other relief for infringement of the ’188 patent. 16.
On February 8, 2000, U.S. Patent No. 6,023,085 (“the ’085 patent”), entitled
“Core Cell Structure And Corresponding Process For NAND-Type High Performance Flash Memory Device,” a copy of which is attached hereto as Exhibit B, was duly and legally issued. The ‘085 patent issued from U.S. patent application Serial Number 08/993,910 filed December 18, 1997 and discloses and relates to the design of and processes for fabricating NAND-type flash memory semiconductor devices. The inventors assigned all right, title, and interest in the ’085 patent to AMD. AMD assigned its entire right, title, and interest in the ’085 patent to Lone Star, and Lone Star is the sole owner of all rights, title and interest in and to the ’085 patent including the right to sue for and collect past, present and future damages and to seek and obtain injunctive or any other relief for infringement of the ’085 patent. 17.
On May 14, 2002, U.S. Patent No. 6,388,330 (“the ’330 patent”), entitled “Low
Dielectric Constant Etch Stop Layers In Integrated Circuit Interconnects,” a copy of which is
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attached hereto as Exhibit C, was duly and legally issued. The ’330 patent issued from U.S. patent application Serial Number 09/776,012 filed February 1, 2001 and discloses and relates to the design of and processes for fabricating semiconductor devices. The inventors assigned all right, title, and interest in the ’330 patent to AMD. AMD assigned its entire right, title, and interest in the ’330 patent to Lone Star, and Lone Star is the sole owner of all rights, title and interest in and to the ’330 patent including the right to sue for and collect past, present and future damages and to seek and obtain injunctive or any other relief for infringement of the ’330 patent. 18.
On March 13, 2007, U.S. Reissue Patent No. 39,518 (“the ’518 patent”), entitled
“Run To Run Control Process For Controlling Critical Dimensions,” a copy of which is attached hereto as Exhibit D, was duly and legally issued. The ’518 patent issued from U.S. patent application Serial Number 09/908,390, filed July 18, 2001, and discloses and relates to the design of and processes for fabricating semiconductor memory devices. The ’518 patent is a reissue of U.S. Patent No. 5,926,690, which originally issued from an application filed May 28, 1997. The inventors assigned all right, title, and interest in the ’518 patent to AMD. AMD assigned its entire right, title, and interest in the ’518 patent to Lone Star, and Lone Star is the sole owner of all rights, title and interest in and to the ’518 patent including the right to sue for and collect past, present and future damages and to seek and obtain injunctive or any other relief for infringement of the ’518 patent. DEFENDANTS’ INFRINGING PRODUCTS AND METHODS The Toshiba Defendants 19.
Defendants Toshiba Corporation, Toshiba America and TAEC (collectively “the
Toshiba Defendants”) make, use, sell, offer for sale and/or import into the United States NAND Flash memory devices and storage products incorporating such devices. These NAND Flash
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memory devices are electrically re-writeable, non-volatile semiconductor memory devices that retain content when power is turned off. The Toshiba Defendants’ NAND Flash memory devices are integrated into a variety of applications that are imported, sold, and used in the United States, including mobile devices, computers, wearable devices, industrial robots, audiovisual systems, automotive applications, and networking and other commercial and consumer applications. The Toshiba Defendants’ NAND Flash memory devices are also incorporated into removable storage devices, such as SD and microSD memory cards, wireless LAN memory cards, SDHC and SDXC memory cards, and USB Flash drives. The Toshiba Defendants also provide enterprise and client solid state drives (“SSDs”) incorporating their NAND Flash memory, which are components of notebooks, desktops, workstations and other consumer computing products, as well as servers and storage devices. The Toshiba Defendants also offer products which incorporate their NAND Flash memory with control functionality. For example, the Toshiba Defendants’ e-MMC products combine NAND Flash control functionality such as Error Code Correction, wear leveling, and bad block management. NAND Flash memory devices manufactured by Toshiba Corporation are also incorporated into a variety of NAND Flash storage products made, used, sold, offered for sale and/or imported by SanDisk. 20.
Despite not having a license to the ’188 patent or ’518 patent, the Toshiba
Defendants have used the semiconductor fabrication methods claimed therein in making Flash memory devices and storage products. Despite not having a license to the ’085 patent and ’330 patent, the Toshiba Defendants’ Flash memory devices and storage products adopt the designs claimed therein.
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Defendant SanDisk Corporation and Western Digital 21.
SanDisk makes, uses, sells, offers for sale and/or imports into the United States
NAND Flash memory devices. These Flash storage devices contain electrically re-writeable, non-volatile semiconductor memory devices that retain content when power is turned off. SanDisk’s Flash memory devices are utilized in a variety of storage applications, including SSDs, embedded products, removable memory cards, USB drives, wireless media drives, digital media players, and wafers and components. They are imported, sold, and used in the United States in various forms, such as in mobile devices, computers, digital camcorders, digital cameras, e-readers, game consoles, GPS devices, other commercial and consumer applications. Subsequent to the acquisition of SanDisk, Western Digital has sold and offered for sale SanDisk Flash memory devices. 22.
Despite not having a license to the ’188 patent or ’518 patent, SanDisk has used
the semiconductor fabrication methods claimed therein in making Flash memory devices and storage products. Despite not having a license to the ’085 patent and ’330 patent, SanDisk Flash memory devices and storage products adopt the designs claimed therein. Toshiba/SanDisk Joint Venture for Production of NAND Flash Memory 23.
Upon information and belief, since at least 1999 SanDisk and Toshiba
Corporation have collaborated as joint venturers with respect to their NAND Flash memory products. Through multiple joint ventures, SanDisk and Toshiba collaborate in the research, development, and manufacture of NAND Flash memory wafers, which are fabricated at Toshiba Corporation’s facilities in Yokkaichi, Japan, using semiconductor manufacturing equipment owned or leased by the joint venture.
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24.
Upon information and belief, SanDisk and Toshiba currently operate jointly
through three business ventures: Flash Partners Ltd., formed in 2004, which operates primarily in Toshiba’s Fab 3 facility; Flash Alliance Ltd., formed in 2006, which operates primarily in Toshiba’s Fab 4 facility; and Flash Forward Ltd., formed in 2010, which operates primarily in Toshiba’s Fab 5 facility. Collectively, these joint ventures provide SanDisk and Toshiba with NAND wafers for use in their end products and the products of their respective customers. Upon information and belief, in October 2015, SanDisk entered into an agreement with Toshiba related to the construction and operation of Toshiba’s “New Fab 2” fabrication facility, and SanDisk and the Toshiba Defendants began production of NAND Flash wafers in the New Fab 2 in January 2016. 25.
Upon information and belief, SanDisk and Toshiba Corporation co-own the joint
venture entities, through which they each contribute funds to pay the costs of the joint ventures’ operations and purchase a portion of the joint ventures’ NAND Flash wafer supply. Upon information and belief, SanDisk purchases substantially all of its NAND Flash supply through these joint venture relationships with Toshiba Corporation. 26.
Toshiba Corporation and SanDisk are joint tortfeasors with respect to their
respective NAND Flash memory devices developed and manufactured through their joint venture relationship, and storage products incorporating those memory devices, which Defendants use, sell, offer for sale, and/or import into the United States and supply to various customers or resellers who in turn use, sell, offer for sale, and /or import them into the United States. 27.
The causes of action alleged against the Defendants herein arise out of the same
transaction, occurrence, or series of transactions or occurrences, such that the Toshiba
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Defendants, SanDisk, and Western Digital are properly joined as Defendants. Upon information and belief, all or substantially all of the products accused of infringement in this action, and the associated manufacturing methods, were developed jointly by Toshiba Corporation and SanDisk, and the Defendants have and will continue to jointly utilize the fabrication processes and facilities involved in producing the accused products. The Patents in Suit are directed to methods used in the manufacture of NAND Flash wafers made through the joint venture relationship and to design features of the memory circuits fabricated on those wafers. Thus the same operative facts underlie the claims of patent infringement asserted against each Defendant. Because the alleged acts of infringement against the Toshiba Defendants, SanDisk, and Western Digital involve the same accused processes and product features, and because the NAND Flash memory devices and storage products made, used, sold, offered for sale, and/or imported by the Toshiba Defendants, SanDisk, and Western Digital are produced using the same processes and facilities and have the identical accused product features, the facts underlying Lone Star’s claims of infringement against Defendants, therefore, are closely linked and the claims arise out of the same transaction, occurrence, or series of transactions or occurrences. FIRST CAUSE OF ACTION – INFRINGEMENT OF THE ’188 PATENT 28.
Plaintiff hereby repeats and re-alleges the allegations contained in paragraphs 1 to
27, as if fully set forth herein. 29.
Defendants directly and/or through their subsidiaries, affiliates, agents, and/or
business partners, have in the past and continue to directly infringe the ’188 patent pursuant to 35 U.S.C. § 271(g) by importing, using, selling or offering to sell NAND Flash memory semiconductor devices in the United States made using the methods claimed in the ’188 patent, including at least claims 1-5 and 7-10. On information and belief, NAND Flash memory
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semiconductor devices manufactured by Defendants and/or other related entities that they control, are made using a process that practices the claims of the ’188 patent including practicing the steps of: (a) providing a semiconductor substrate; (b) forming a gate over the substrate; (c) forming a source/drain region in the substrate; (d) providing a source/drain contact electrically coupled to the source/drain region; (e) forming an interlevel dielectric layer that includes first, second and third dielectric layers over the source/drain contact; (f) forming an etch mask over the interlevel dielectric layer; (g) applying a first etch which is highly selective of the first dielectric layer with respect to the second dielectric layer through an opening in the etch mask using the second dielectric layer as an etch stop, to form a first hole in the first dielectric layer that extends to the second dielectric layer without extending to the third dielectric layer; (h) applying a second etch which is highly selective of the second dielectric layer with respect to the third dielectric layer through the opening in the etch mask using the third dielectric layer as an etch stop, to form a second hole in the second dielectric layer that extends to the third dielectric layer without extending to the source/drain contact; and (i) applying a third etch which is highly selective of the third dielectric layer with respect to the source/drain contact through the opening in the etch mask, form a third hole in the third dielectric layer that extends to the source/drain contact, such that the first, second and third holes in combination provide a contact hole in the interlevel dielectric layer. 30.
Defendants have been and are engaged in one or more of these direct infringing
activities related to their NAND Flash memory devices manufactured using their 15 nanometer process node and NAND Flash memory devices manufactured using their 19 nanometer process node, and any other NAND Flash memory devices made by a substantially similar process (“the ’188 Accused NAND Flash Products”). With regard to the Toshiba Defendants, the ’188
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Accused NAND Flash Products are sold as NAND Flash wafers, NAND Flash chips, or included as components of NAND Flash storage products, such products including at least SLC NAND Flash Memory (used in products such as mobile phones, printers, game consoles, servers, digital TVs, industrial equipment, and SSDs), NAND Flash Memories with an Integrated Controller, NAND Flash media cards, and USB Flash Memory. With regard to SanDisk and Western Digital, the ’188 Accused NAND Flash Products are sold in a variety of forms, including enterprise and client NAND Flash solid state drives, embedded NAND Flash products, removable NAND Flash products, and as memory wafers and memory components. 31.
Defendants, directly and/or through their subsidiaries, affiliates, agents, and/or
business partners, have been and are now indirectly infringing the ’188 patent, including at least claims 1-5 and 7-10, pursuant to 35 U.S.C. § 271(b) by actively inducing acts of direct infringement performed by others. Defendants have actual notice of the ’188 patent and the infringement alleged herein at least upon the service of this Complaint. Upon information and belief, Defendants have numerous lawyers and other active agents of Defendants and of their owned and controlled subsidiaries who regularly review patents and published patent applications relevant to technology in the fields of the Patents in Suit, specifically including patents directed to semiconductor memory devices issued to competitors such as AMD, the original assignee of the ’188 patent. Upon information and belief, the Toshiba Defendants themselves have been issued over 46,000 patents held in the name of one of the Toshiba Defendants or the related entity, Kabushiki Kaisha Toshiba, including more than 150 patents prosecuted in the USPTO in the same classifications as the ’188 patent, giving the Toshiba Defendants intimate knowledge of the art in fields relevant to this civil action. Upon information and belief, SanDisk itself has been issued over 3,900 patents, including numerous patents
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prosecuted in the USPTO in the same classifications as the ’188 patent, giving SanDisk intimate knowledge of the art in fields relevant to this civil action. The timing, circumstances and extent of Defendants obtaining actual knowledge of the ’188 patent prior to the commencement of this lawsuit will be confirmed during discovery. 32.
Upon gaining knowledge of the ’188 patent, it was, or became, apparent to
Defendants that the manufacture, sale, importing, offer for sale, and use of their ’188 Accused NAND Flash Products results in infringement of the ’188 patent. Upon information and belief, Defendants have continued and will continue to engage in activities constituting inducement of infringement, notwithstanding their knowledge, or willful blindness thereto, that the activities they induce result in infringement of the ’188 patent. 33.
The ’188 Accused NAND Flash Products are intended for integration into
products known to be sold widely in the United States. As joint venturers, Defendants Toshiba Corporation and SanDisk make NAND Flash semiconductor devices using methods claimed in the ’188 patent, which devices infringe when they are imported into, or sold, used, or offered for sale in, the United States. Defendants indirectly infringe by inducing customers (such as makers of mobile devices, desktop computers and other devices that use NAND Flash memory) to import products that integrate NAND Flash semiconductor devices made using the methods claimed in the ’188 patent, or to sell or use such products, or offer them for sale, in the United States. For example, Defendants induce third-party manufacturers, original equipment manufacturers (OEMs), importers, resellers, and other customers who purchase devices manufactured at the overseas facilities pursuant to the joint venture relationship, to import devices made using the methods claimed in the ’188 patent, or to sell or use such devices, or offer them for sale in the United States without authority.
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34.
Defendants encourage customers, resellers, OEMs, or others to import into the
United States and sell and use in the United States the ’188 Accused NAND Flash Products made using the methods claimed in the ’188 patent with knowledge and the specific intent to cause the acts of direct infringement performed by these third parties. On information and belief, after Defendants obtained knowledge of the ’188 patent, the ’188 Accused NAND Flash Products have been and will continue to be imported into the United States and sold in large volumes by themselves and by others, such as customers, distributors, and resellers. Defendants are aware that the ’188 Accused NAND Flash Products are always made using the same fabrication methods under Defendants’ direction and control such that Defendants’ customers will infringe one or more claims of the ’188 patent by incorporating such NAND Flash semiconductor devices in other products, and that subsequent importation, sale and use of such products in the United States would be a direct infringement of the ’188 patent. Therefore, Defendants are aware that their customers will infringe the ’188 patent by importing, selling and using the products supplied by Defendants. 35.
Defendants directly benefit from and actively and knowingly encourage
customers, resellers, and users’ importation of these products into the United States and sale and use within the United States. Defendants actively encourage customers and downstream users, OEMs, and resellers to import, use, and sell in the United States the ’188 Accused NAND Flash Products that they manufacture and supply, including through advertising, marketing and sales activities directed at United States sales. On information and belief, Defendants are aware of the size and importance of the United States market for customers of Defendants’ products, and also distribute or supply these products intended for importation, use, and sale in the United States. Defendants routinely market their infringing NAND Flash memory products to third parties for
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inclusion in products that are sold to customers in the United States, as well as directly to enduser customers. Defendants have publicly stated that their Flash products are targeted for applications such as mobile phones, SSDs, tablets, computers, industrial and automotive applications, and removable storage devices, all of which are widely sold and used in the United States. Defendants have numerous direct sales, distributors, and reseller outlets for these products in the United States. Defendants’ marketing efforts show that they have specifically intended to and have induced direct infringement in the United States. 36.
Defendants also provide OEMs, manufacturers, importers, resellers, customers,
and end users instructions, user guides, and technical specifications on how to incorporate the ’188 Accused NAND Flash Products into electronics products that are made, used, sold, offered for sale in and/or imported into the United States. When OEMs, manufacturers, importers, resellers, customers, and end users follow such instructions, user guides, and technical specifications and embed the products in end products and make, use, offer to sell, sell, and/or import them into the United States, they directly infringe one or more claims of the ’188 patent. Defendants know that by providing such instructions, user guides, and technical specifications, OEMs, manufacturers, importers, resellers, customers, and end users follow them, and therefore directly infringe one or more claims of the ’188 patent. Defendants thus know that their actions actively induce infringement. 37.
Defendants have engaged and will continue to engage in additional activities to
specifically target the United States market for the ’188 Accused NAND Flash products and actively induce OEMs, manufacturers, importers, resellers, customers, and end users to directly infringe one or more claims of the ’188 patent in the United States. For example, Defendants have showcased their NAND Flash memory technologies at various industry events, including
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CES and the Flash Memory Summit, and through written materials distributed in the United States, in an effort to encourage various OEMs, manufacturers, importers, resellers, customers, and end users to include the infringing technology in their computers, mobile devices, removable storage devices and other products. These events are attended by the direct infringers mentioned above and generally by companies that make, use, offer to sell, sell, and/or import into the United States products that use NAND Flash memory components such as those made by Defendants. 38.
Defendants derive significant revenue by selling their NAND Flash memory
products to third parties who directly infringe the ’188 patent in the United States. Defendants’ extensive sales and marketing efforts, sales volume, and partnerships all evidence their intent to induce companies to infringe one or more claims of the ’188 patent by using, offering to sell, selling, or importing products that incorporate the ’188 Accused NAND Flash Products in the United States. Defendants have had specific intent to induce infringement or have been willfully blind to the direct infringement they are inducing. 39.
Defendants’ direct and indirect infringement of the ’188 patent has injured Lone
Star, and Lone Star is entitled to recover damages adequate to compensate for such infringement pursuant to 35 U.S.C. § 284. Unless they cease their infringing activities, Defendants will continue to injure Lone Star by infringing the ‘188 patent. 40.
On information and belief, Defendants acted egregiously and with willful
misconduct in that their actions constituted direct or indirect infringement of a valid patent, and this was either known or so obvious that Defendants should have known about it. Defendants continue to infringe the ’188 patent by making, using, selling, offering for sale and importing in the United States the ’188 Accused NAND Flash Products and to induce the direct infringement
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of others performing these acts, or they have acted at least in reckless disregard of Lone Star’s patent rights. On information and belief, Defendants will continue their infringement notwithstanding actual knowledge of the ’188 patent and without a good faith basis to believe that their activities do not infringe any valid claim of the ’188 patent. All infringement of the ’188 patent following Defendants’ knowledge of the ’188 patent is willful and Lone Star is entitled to treble damages and attorneys’ fees and costs incurred in this action under 35 U.S.C. §§ 284 and 285. SECOND CAUSE OF ACTION – INFRINGEMENT OF THE ’085 PATENT 41.
Plaintiff hereby repeats and re-alleges the allegations contained in paragraphs 1 to
27, as if fully set forth herein. 42.
Defendants, directly and/or through their subsidiaries, affiliates, agents, and/or
business partners, have in the past and continue to directly infringe the ’085 patent, including at least claims 1, 3, 4 and 6, pursuant to 35 U.S.C. § 271(a) by making, using, selling, offering to sell, and/or importing NAND Flash memory devices that embody the inventions claimed in the ’085 patent, within the United States and within this District. In violation of the ’085 patent, for example, Defendants’ accused NAND Flash memory devices: include (a) a core region including a stacked gate flash memory cell structure and a select gate transistor, and a periphery region including a low voltage transistor and a high voltage transistor; and (b) the select gate transistor and the low voltage transistor both have a gate oxide layer and a gate electrode layer; and (c) a thickness of the gate oxide layer of the select gate transistor and the low voltage transistor are substantially the same; and (d) a thickness of the gate electrode layer of the select gate transistor and the low voltage transistor are substantially the same.
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43.
Defendants have been and are engaged in one or more of these direct infringing
activities related to their NAND Flash memory devices manufactured using their 15 nanometer process node and NAND Flash memory devices manufactured using their 19 nanometer process node, and any other NAND Flash memory devices made by a substantially similar process (“the ’085 Accused NAND Flash Products”). With regard to the Toshiba Defendants, the ’085 Accused NAND Flash Products are sold as NAND Flash wafers, NAND Flash chips, or included as components of NAND Flash storage products, such products including at least SLC NAND Flash Memory (used in products such as mobile phones, printers, game consoles, servers, digital TVs, industrial equipment, and SSDs), NAND Flash Memories with an Integrated Controller, NAND Flash media cards, and USB Flash Memory. With regard to SanDisk and Western Digital, the ’085 Accused NAND Flash Products are sold in a variety of forms, including enterprise and client NAND Flash solid state drives, embedded NAND Flash products, removable NAND Flash products, and as memory wafers and memory components. 44.
Defendants, directly and/or through their subsidiaries, affiliates, agents, and/or
business partners, have been and are now indirectly infringing the ’085 patent, including at least claims 1, 3, 4 and 6, pursuant to 35 U.S.C. § 271(b) by actively inducing acts of direct infringement performed by others. Defendants have actual notice of the ’085 patent and the infringement alleged herein at least upon the service of this Complaint. Upon information and belief, Defendants have numerous lawyers and other active agents of Defendants and of their owned and controlled subsidiaries who regularly review patents and published patent applications relevant to technology in the fields of the Patents in Suit, specifically including patents directed to semiconductor memory devices issued to competitors such as AMD, the original assignee of the ’085 patent. Upon information and belief, the Toshiba Defendants
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themselves have been issued over 46,000 patents held in the name of one of the Toshiba Defendants or the related entity, Kabushiki Kaisha Toshiba, including over 650 patents prosecuted in the USPTO in the same classifications as the ’085 patent, giving the Toshiba Defendants intimate knowledge of the art in fields relevant to this civil action. The Toshiba Defendants have had previous actual notice of the ’085 patent prior to the filing of this Complaint at least through their efforts to patent related technologies. The ’085 patent is listed on the face of U.S. Patent No. 6,214,665 (“the ’665 patent”) issued to Kabushiki Kaisha Toshiba on April 10, 2001, indicating that it was among the references reference cited against and considered by the USPTO and Kabushiki Kaisha Toshiba during prosecution of the ’665 patent. Accordingly, the Toshiba Defendants have had actual notice of the ’085 patent since at least the issue date of the ’665 patent. The ’085 patent is also listed on the face of U.S. Patent No. 7,109,547, issued to Kabushi Kaisha Toshiba on September 19, 2006, and on the face of U.S. Patent No. 7,579,647, issued to Kabushi Kaisha Toshiba on August 25, 2009, and on the face of U.S. Patent No. 7,307,307, issued to Kabushi Kaisha Toshiba on December 11, 2007, demonstrating that the Toshiba Defendants had further notice of the ’085 patent well prior to the commencement of this legal action. Upon information and belief, SanDisk itself has been issued over 3,900 patents, including over 100 patents prosecuted in the USPTO in the same classifications as the ’085 patent, giving SanDisk intimate knowledge of the art in fields relevant to this civil action. The timing, circumstances and extent of Defendants obtaining actual knowledge of the ’085 patent prior to the commencement of this lawsuit will be confirmed during discovery. 45.
Upon gaining knowledge of the ’085 patent, it was, or became, apparent to
Defendants that the manufacture, sale, importing, offer for sale and use of their ’085 Accused
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NAND Flash Products results in infringement of the ’085 patent. Upon information and belief, Defendants have continued and will continue to engage in activities constituting inducement of infringement, notwithstanding their knowledge, or willful blindness thereto, that the activities they induce result in infringement of the ’085 patent. 46.
The ’085 Accused NAND Flash Products are intended for integration into
products known to be sold widely in the United States. As joint venturers, Defendants Toshiba Corporation and SanDisk make NAND Flash semiconductor devices that embody the inventions claimed in the ’085 patent, which devices infringe when they are imported into, or sold, used, or offered for sale in, the United States. Defendants indirectly infringe by inducing customers (such as makers of mobile devices, desktop computers and other devices that use Flash memory) to import products that integrate Flash semiconductor devices embodying inventions claimed in the ’085 patent, or to sell or use such products, or offer them for sale, in the United States. For example, Defendants induce third-party manufacturers, OEMs, importers, resellers, and other customers who purchase devices manufactured at the overseas facilities pursuant to the joint venture relationship, to import devices embodying inventions claimed in the ’085 patent, or to sell or use such devices, or offer them for sale in the United States without authority. 47.
Defendants encourage customers, resellers, OEMs, or others to import into the
United States and sell and use in the United States the ’085 Accused NAND Flash Products embodying inventions claimed in the ’085 patent with knowledge and the specific intent to cause the acts of direct infringement performed by these third parties. On information and belief, after Defendants obtained knowledge of the ’085 patent, the ’085 Accused NAND Flash Products have been and will continue to be imported into the United States and sold in large volumes by themselves and by others, such as customers, distributors, and resellers. Defendants are aware
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that the ’085 Accused NAND Flash Products are integral components of the computer and mobile products incorporating them, that the infringing NAND Flash Products are built into the computer and other products, and cannot be removed or disabled by a purchaser of the consumer products containing the infringing Flash memory devices, such that Defendants’ customers will infringe one or more claims of the ’085 patent by incorporating such Flash semiconductor devices in other products, and that subsequent importation, sale and use of such products in the United States would be a direct infringement of the ’085 patent. Therefore, Defendants are aware that their customers will infringe one or more claims of the ’085 patent by selling, offering for sale, importing and/or using the products as-sold and as-marketed by Defendants. 48.
Defendants directly benefit from and actively and knowingly encourage
customers, resellers, and users’ importation of these products into the United States and sale and use within the United States. Defendants actively encourage customers and downstream users, OEMs, and resellers to import, use, and sell in the United States the ’085 Accused NAND Flash Products that they manufacture and supply, including through advertising, marketing and sales activities directed at United States sales. On information and belief, Defendants are aware of the size and importance of the United States market for customers of Defendants’ products, and also distribute or supply these products intended for importation, use, and sale in the United States. Defendants routinely market their infringing NAND Flash memory products to third parties for inclusion in products that are sold to customers in the United States, as well as directly to enduser customers. Defendants have publicly stated that their Flash products are targeted for applications such as mobile phones, SSDs, tablets, computers, industrial and automotive applications, and removable storage devices, all of which are widely sold and used in the United States. Defendants have numerous direct sales, distributors, and reseller outlets for these
22
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products in the United States. Defendants’ marketing efforts show that they have specifically intended to and have induced direct infringement in the United States. 49.
Defendants also provide OEMs, manufacturers, importers, resellers, customers,
and end users instructions, user guides, and technical specifications on how to incorporate the ’085 Accused NAND Flash Products into electronics products that are made, used, sold, offered for sale in and/or imported into the United States. When OEMs, manufacturers, importers, resellers, customers, and end users follow such instructions, user guides, and technical specifications and embed the products in end products and make, use, offer to sell, sell, and/or import into the United States, they directly infringe one or more claims of the ’085 patent. Defendants know that by providing such instructions, user guides, and technical specifications, OEMs, manufacturers, importers, resellers, customers, and end users follow them, and therefore directly infringe one or more claims of the ’085 patent. Defendants thus know that their actions actively induce infringement. 50.
Defendants have engaged and will continue to engage in additional activities to
specifically target the United States market for the ’085 Accused NAND Flash products and actively induce OEMs, manufacturers, importers, resellers, customers, and end users to directly infringe one or more claims of the ’085 patent in the United States. For example, Defendants have showcased their NAND Flash memory technologies at various industry events, including CES and the Flash Memory Summit, and through written materials distributed in the United States, in an effort to encourage various OEMs, manufacturers, importers, resellers, customers, and end users to include the infringing technology in their computers, mobile devices, removable storage devices and other products. These events are attended by the direct infringers mentioned above and generally by companies that make, use, offer to sell, sell, and/or import into the
23
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United States products that use NAND Flash memory components such as those made by Defendants. 51.
Defendants derive significant revenue by selling the ’085 Accused NAND Flash
Products to third parties who directly infringe the ’085 patent in the United States. Defendants’ extensive sales and marketing efforts, sales volume, and partnerships all evidence their intent to induce companies to infringe one or more claims of the ’085 patent by, using, offering to sell, selling, or importing products that incorporate the ’085 Accused NAND Flash Products, in the United States. Defendants have had specific intent to induce infringement or have been willfully blind to the direct infringement they are inducing. 52.
Upon information and belief, Defendants have continued and will continue to
engage in activities constituting contributory infringement of the ’085 patent, including at least claims 1, 3, 4 and 6, pursuant to 35 U.S.C. § 271(c). Defendants contributorily infringe with knowledge that the ’085 Accused NAND Flash Products, or the use thereof, infringe the ’085 patent. Defendants knowingly and intentionally contributed to the direct infringement of the ’085 patent by others, by supplying these NAND Flash memory chipset products, that embody a material part of the claimed invention of the ’085 patent, that are known by the Defendants to be specially made or adapted for use in an infringing manner. For example, and without limitation, the ’085 Accused NAND Flash Products are used in end products, including solid state drives, thumb drives, computers, laptops and mobile telephones. The ’085 Accused NAND Flash Products are not staple articles or commodities of commerce suitable for non-infringing use and are especially made for or adapted for use in infringing the ’085 patent. There are no substantial uses of the ’085 Accused NAND Flash Products that do not infringe the ’085 patent. By contributing a material part of the infringing computing products sold, offered for sale, imported
24
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and used by their customers, resellers and users, Defendants have been and are now indirectly infringing the ’085 patent under 35 U.S.C. § 271(c). 53.
Defendants’ direct and indirect infringement of the ’085 patent has injured Lone
Star, and Lone Star is entitled to recover damages adequate to compensate for such infringement pursuant to 35 U.S.C. § 284. Unless they cease their infringing activities, Defendants will continue to injure Lone Star by infringing the ’085 patent. 54.
On information and belief, Defendants acted egregiously and with willful
misconduct in that their actions constituted direct or indirect infringement of a valid patent, and this was either known or so obvious that Defendants should have known about it. Defendants continue to infringe the ’085 patent by making, using, selling, offering for sale and importing in the United States the ’085 Accused NAND Flash Products and to induce the direct infringement of others performing these acts, or they have acted at least in reckless disregard of Lone Star’s patent rights. On information and belief, Defendants will continue their infringement notwithstanding actual knowledge of the ’085 patent and without a good faith basis to believe that their activities do not infringe any valid claim of the ’085 patent. All infringement of the ’085 patent following Defendants’ knowledge of the ’085 patent is willful and Lone Star is entitled to treble damages and attorneys’ fees and costs incurred in this action under 35 U.S.C. §§ 284 and 285. THIRD CAUSE OF ACTION – INFRINGEMENT OF THE ’330 PATENT 55.
Plaintiff hereby repeats and re-alleges the allegations contained in paragraphs 1 to
27, as if fully set forth herein. 56.
Defendants, directly and/or through their subsidiaries, affiliates, agents, and/or
business partners, have in the past and continue to directly infringe the ’330 patent pursuant to 35
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U.S.C. § 271(a) by making, using, selling, offering to sell, and/or importing NAND Flash memory semiconductor devices that embody the inventions claimed in the ’330 patent, within the United States and within this District, including at least claims 1 and 5. In violation of the ’330 patent, Defendants’ accused NAND Flash memory devices include: (a) a semiconductor substrate having a semiconductor device provided thereon; (b) a first dielectric layer formed over the semiconductor substrate having a first opening; (c) a first conductor core filling the first opening and connected to the semiconductor device; (d) an etch stop layer of silicon nitride formed over the first dielectric layer and the first conductor core, the etch stop layer having a dielectric constant below 5.5; (e) a second dielectric layer formed over the etch stop layer and having a second opening open to the first conductor core; and (f) a second conductor core filling the second opening and connected to the first conductor core. 57.
Defendants have been and are engaged in one or more of these direct infringing
activities related to their NAND Flash memory devices manufactured using their 15 nanometer process node and NAND Flash memory devices manufactured using their 19 nanometer process node, and any other NAND Flash memory devices made by a substantially similar process (“the ’330 Accused NAND Flash Products”). With regard to the Toshiba Defendants, the ’330 Accused NAND Flash Products are sold as NAND Flash wafers, NAND Flash chips, or included as components of NAND Flash storage products, such products including at least SLC NAND Flash Memory (used in products such as mobile phones, printers, game consoles, servers, digital TVs, industrial equipment, and SSDs), NAND Flash Memories with an Integrated Controller, NAND Flash media cards, and USB Flash Memory. With regard to SanDisk and Western Digital, the ’330 Accused NAND Flash Products are sold in a variety of forms, including
26
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enterprise and client NAND Flash solid state drives, embedded NAND Flash products, removable NAND Flash products, and as memory wafers and memory components. 58.
Defendants, directly and/or through their subsidiaries, affiliates, agents, and/or
business partners, have been and are now indirectly infringing the ’330 patent under 35 U.S.C. § 271(b) by actively inducing acts of direct infringement performed by others. Defendants have actual notice of the ’330 patent and the infringement alleged herein at least upon the service of this Complaint, including at least claims 1 and 5. Upon information and belief, Defendants have numerous lawyers and other active agents of Defendants and of their owned and controlled subsidiaries who regularly review patents and published patent applications relevant to technology in the fields of the Patents in Suit, specifically including patents directed to semiconductor memory devices issued to competitors such as AMD, the original assignee of the ’330 patent. Upon information and belief, the Toshiba Defendants themselves have been issued over 46,000 patents held in the name of one of the Toshiba Defendants or the related entity, Kabushiki Kaisha Toshiba, including over 300 patents prosecuted in the USPTO in the same classifications as the ’330 patent, giving the Toshiba Defendants intimate knowledge of the art in fields relevant to this civil action. Upon information and belief, SanDisk itself has been issued over 3,900 patents, including numerous patents prosecuted in the USPTO in the same classifications as the ’330 patent, giving SanDisk intimate knowledge of the art in fields relevant to this civil action. The timing, circumstances and extent of Defendants obtaining actual knowledge of the ’330 patent prior to the commencement of this lawsuit will be confirmed during discovery. 59.
Upon gaining knowledge of the ’330 patent, it was, or became, apparent to
Defendants that the manufacture, sale, importing, offer for sale, and use of their ’330 Accused
27
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NAND Flash Products result in infringement of the ’330 patent. Upon information and belief, Defendants have continued and will continue to engage in activities constituting inducement of infringement, notwithstanding their knowledge, or willful blindness thereto, that the activities they induce result in infringement of the ’330 patent under 35 U.S.C. § 271(b). 60.
The ’330 Accused NAND Flash Products are intended for integration into
products known to be sold widely in the United States. As joint venturers, Defendants Toshiba Corporation and SanDisk make NAND Flash devices that embody the inventions claimed in the ’330 patent, which devices infringe when they are imported into, or sold, used, or offered for sale in, the United States. Defendants indirectly infringe by inducing customers (such as makers of mobile devices, desktop computers and other devices that use NAND Flash memory) to import products that integrate NAND Flash devices embodying inventions claimed in the ’330 patent, or to sell or use such products, or offer them for sale, in the United States. For example, Defendants induce third-party manufacturers, OEMs, importers, resellers, and other customers who purchase devices manufactured at the overseas facilities pursuant to the joint venture relationship, to import devices embodying inventions claimed in the ’330 patent, or to sell or use such devices, or offer them for sale in the United States without authority. 61.
Defendants encourage customers, resellers, OEMs, or others to import into the
United States and sell and use in the United States the ’330 Accused NAND Flash Products embodying inventions claimed in the ’330 patent with knowledge and the specific intent to cause the acts of direct infringement performed by these third parties. On information and belief, after Defendants obtained knowledge of the ’330 patent, the ’330 Accused NAND Flash Products have been and will continue to be imported into the United States and sold in large volumes by themselves and by others, such as customers, distributors, and resellers. Defendants are aware
28
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that the ’330 Accused NAND Flash Products are integral components of the computer and mobile products incorporating them, that the infringing NAND Flash Products are built into the computer and other products, and cannot be removed or disabled by a purchaser of the consumer products containing the infringing NAND Flash memory devices, such that Defendants’ customers will infringe one or more claims of the ’330 patent by incorporating such NAND Flash devices in other products, and that subsequent importation, sale and use of such products in the United States would be a direct infringement of the ’330 patent. Therefore, Defendants are aware that their customers will infringe one or more claims of the ’330 patent by selling, offering for sale, importing and/or using the products as-sold and as-marketed by Defendants. 62.
Defendants directly benefit from and actively and knowingly encourage
customers, resellers, and users’ importation of these products into the United States and sale and use within the United States. Defendants actively encourage customers and downstream users, OEMs, and resellers to import, use, and sell in the United States the ’330 Accused NAND Flash Products that they manufacture and supply, including through advertising, marketing, and sales activities directed at United States sales. On information and belief, Defendants are aware of the size and importance of the United States market for customers of Defendants’ products, and also distribute or supply these products intended for importation, use, and sale in the United States. Defendants routinely market their infringing NAND Flash memory products to third parties for inclusion in products that are sold to customers in the United States, as well as directly to enduser customers. Defendants have publicly stated that their NAND Flash products are targeted for applications such as mobile phones, SSDs, tablets, computers, industrial and automotive applications and removable storage devices, all of which are widely sold and used in the United States. Defendants have numerous direct sales, distributors, and reseller outlets for these
29
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products in the United States. Defendants’ marketing efforts show that they have specifically intended to and have induced direct infringement in the United States. 63.
Defendants also provide OEMs, manufacturers, importers, resellers, customers,
and end users instructions, user guides, and technical specifications on how to incorporate the ’330 Accused NAND Flash Products into electronics products that are made, used, sold, offered for sale in and/or imported into the United States. When OEMs, manufacturers, importers, resellers, customers, and end users follow such instructions, user guides, and technical specifications and embed the products in end products and make, use, offer to sell, sell, and/or import into the United States, they directly infringe one or more claims of the ’330 patent. Defendants know that by providing such instructions, user guides, and technical specifications, OEMs, manufacturers, importers, resellers, customers, and end users follow them, and therefore directly infringe one or more claims of the ’330 patent. Defendants thus know that their actions actively induce infringement. 64.
Defendants have engaged and will continue to engage in additional activities to
specifically target the United States market for the ’330 Accused NAND Flash Products and actively induce OEMs, manufacturers, importers, resellers, customers, and end users to directly infringe one or more claims of the ’330 patent in the United States. For example, Defendants have set up a global sales network that includes the United States to encourage various OEMs, manufacturers, importers, resellers, customers, and end users to include their infringing technology in their computers, mobile devices, removable storage devices and other products. 65.
Defendants derive significant revenue by selling the ’330 Accused NAND Flash
Products to third parties who directly infringe the ’330 patent in the United States. Defendants’ extensive sales and marketing efforts, sales volume, and partnerships all evidence their intent to
30
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induce companies to infringe one or more claims of the ’330 patent by, using, offering to sell, selling, or importing products that incorporate the ’330 Accused NAND Flash Products, in the United States. Defendants have had specific intent to induce infringement or have been willfully blind to the direct infringement they are inducing. 66.
Upon information and belief, Defendants have continued and will continue to
engage in activities constituting contributory infringement of the ’330 patent under 35 U.S.C. § 271(c), including at least claims 1 and 5. Defendants contributorily infringe with knowledge that the ’330 Accused NAND Flash Products, or the use thereof, infringe the ’330 patent. Defendants knowingly and intentionally contributed to the direct infringement of the ’330 patent by others, by supplying these NAND Flash memory chipset products, that embody a material part of the claimed invention of the ’330 patent, that are known by the Defendants to be specially made or adapted for use in an infringing manner. For example, and without limitation, the ’330 Accused NAND Flash Products are used in end products, including computers, laptops, tablets and mobile telephones. The ’330 Accused NAND Flash Products are not staple articles or commodities of commerce suitable for non-infringing use and are especially made for or adapted for use in infringing the ’330 patent. There are no substantial uses of the ’330 Accused NAND Flash Products that do not infringe the ’330 patent. By contributing a material part of the infringing computing products sold, offered for sale, imported and used by their customers, resellers and users, Defendants have been and are now indirectly infringing the ’330 patent under 35 U.S.C. § 271(c). 67.
Defendants’ direct and indirect infringement of the ’330 patent has injured Lone
Star, and Lone Star is entitled to recover damages adequate to compensate for such infringement
31
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pursuant to 35 U.S.C. § 284. Unless they cease their infringing activities, Defendants will continue to injure Lone Star by infringing the ’330 patent. 68.
On information and belief, Defendants acted egregiously and with willful
misconduct in that their actions constituted direct or indirect infringement of a valid patent, and this was either known or so obvious that Defendants should have known about it. Defendants continue to infringe the ’330 patent by making, using, selling, offering for sale and importing in the United States the ’330 Accused NAND Flash Products and to induce the direct infringement of others performing these acts, or they have acted at least in reckless disregard of Lone Star’s patent rights. On information and belief, Defendants will continue their infringement notwithstanding actual knowledge of the ’330 patent and without a good faith basis to believe that its activities do not infringe any valid claim of the ’330 patent. All infringement of the ’330 patent following Defendants’ knowledge of the ’330 patent is willful and Lone Star is entitled to treble damages and attorneys’ fees and costs incurred in this action under 35 U.S.C. §§ 284 and 285. FOURTH CAUSE OF ACTION – INFRINGEMENT OF THE ’518 PATENT 69.
Plaintiff hereby repeats and re-alleges the allegations contained in paragraphs 1 to
27, as if fully set forth herein. 70.
Defendants directly and/or through their subsidiaries, affiliates, agents, and/or
business partners, have in the past and continue to directly infringe the ’518 patent pursuant to 35 U.S.C. § 271(g) by importing, using, selling or offering to sell NAND Flash memory semiconductor devices in the United States made using the methods claimed in the ’518 patent, including at least claims 1-9, 13 and 15-17. On information and belief, NAND Flash memory semiconductor devices manufactured by Defendants and/or other related entities that they
32
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control, are made using a process that practices the claims of the ’518 patent including practicing the steps of: (a) patterning, exposing, and developing a photoresist layer on a wafer in a photolithography process that forms a plurality of structures on the integrated circuit including a gate; (b) measuring a DICD critical dimension of the gate following developing of the photoresist layer in a Develop Inspection Critical Dimensions (DICD) operation; (c) etching the wafer including etching of the gate; (d) measuring a FICD critical dimension of the gate following etching of the wafer in a Final Inspection Critical Dimensions (FICD) operation; (e) feeding forward the DICD critical dimension to a process model; (f) feeding back the FICD critical dimension to the process model; and (g) controlling a photoresist deposit and etch process recipe parameter in the process model according to the DICD critical dimension and the FICD critical dimension of the gate to improve critical dimension uniformity. 71.
Defendants have been and are engaged in one or more of these direct infringing
activities related to their NAND Flash memory devices manufactured using their 15 nanometer process node and NAND Flash memory devices manufactured using their 19 nanometer process node, and any other NAND Flash memory devices made by a substantially similar process (“the ’518 Accused NAND Flash Products”). With regard to the Toshiba Defendants, the ’518 Accused NAND Flash Products are sold as NAND Flash wafers, NAND Flash chips, or included as components of NAND Flash storage products, such products including at least SLC NAND Flash Memory (used in products such as mobile phones, printers, game consoles, servers, digital TVs, industrial equipment, and SSDs), NAND Flash Memories with an Integrated Controller, NAND Flash media cards, and USB Flash Memory. With regard to SanDisk and Western Digital, the ’518 Accused NAND Flash Products are sold in a variety of forms, including
33
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enterprise and client NAND Flash solid state drives, embedded NAND Flash products, removable NAND Flash products, and as memory wafers and memory components. 72.
Defendants, directly and/or through their subsidiaries, affiliates, agents, and/or
business partners, have been and are now indirectly infringing the ’518 patent, including at least claims 1-9, 13 and 15-17, pursuant to 35 U.S.C. § 271(b) by actively inducing acts of direct infringement performed by others. Defendants have actual notice of the ’518 patent and the infringement alleged herein at least upon the service of this Complaint. Upon information and belief, Defendants have numerous lawyers and other active agents of Defendants and of their owned and controlled subsidiaries who regularly review patents and published patent applications relevant to technology in the fields of the Patents in Suit, specifically including patents directed to semiconductor memory devices issued to competitors such as AMD, the original assignee of the ’518 patent. Upon information and belief, the Toshiba Defendants themselves have been issued over 46,000 patents held in the name of one of the Toshiba Defendants or the related entity, Kabushiki Kaisha Toshiba, including dozens of patents prosecuted in the USPTO in the same classifications as the ’518 patent, giving the Toshiba Defendants intimate knowledge of the art in fields relevant to this civil action. Upon information and belief, SanDisk itself has been issued over 3,900 patents, including numerous patents prosecuted in the USPTO in the same classifications as the ’518 patent, giving SanDisk intimate knowledge of the art in fields relevant to this civil action. The timing, circumstances and extent of Defendants obtaining actual knowledge of the ’518 patent prior to the commencement of this lawsuit will be confirmed during discovery. 73.
Upon gaining knowledge of the ’518 patent, it was, or became, apparent to
Defendants that the manufacture, sale, importing, offer for sale, and use of their ’518 Accused
34
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NAND Flash Products results in infringement of the ’518 patent. Upon information and belief, Defendants have continued and will continue to engage in activities constituting inducement of infringement, notwithstanding their knowledge, or willful blindness thereto, that the activities they induce result in infringement of the ’518 patent. 74.
The ’518 Accused NAND Flash Products are intended for integration into
products known to be sold widely in the United States. As joint venturers, Defendants Toshiba Corporation and SanDisk make NAND Flash semiconductor devices using methods claimed in the ’518 patent, which devices infringe when they are imported into, or sold, used, or offered for sale in, the United States. Defendants indirectly infringe by inducing customers (such as makers of mobile devices, desktop computers and other devices that use NAND Flash memory) to import products that integrate NAND Flash semiconductor devices made using the methods claimed in the ’518 patent, or to sell or use such products, or offer them for sale, in the United States. For example, Defendants induce third-party manufacturers, OEMs, importers, resellers, and other customers who purchase devices manufactured at the overseas facilities pursuant to the joint venture relationship, to import devices made using the methods claimed in the ’518 patent, or to sell or use such devices, or offer them for sale in the United States without authority. 75.
Defendants encourage customers, resellers, OEMs, or others to import into the
United States and sell and use in the United States the ’518 Accused NAND Flash Products made using the methods claimed in the ’518 patent with knowledge and the specific intent to cause the acts of direct infringement performed by these third parties. On information and belief, after Defendants obtained knowledge of the ’518 patent, the ’518 Accused NAND Flash Products have been and will continue to be imported into the United States and sold in large volumes by themselves and by others, such as customers, distributors, and resellers. Defendants
35
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are aware that the ’518 Accused NAND Flash Products are always made using the same fabrication methods under Defendants’ direction and control such that Defendants’ customers will infringe one or more claims of the ’518 patent by incorporating such NAND Flash semiconductor devices in other products, and that subsequent importation, sale and use of such products in the United States would be a direct infringement of the ’518 patent. Therefore, Defendants are aware that their customers will infringe the ’518 patent by importing, selling and using the products supplied by Defendants. 76.
Defendants directly benefit from and actively and knowingly encourage
customers, resellers, and users’ importation of these products into the United States and sale and use within the United States. Defendants actively encourage customers and downstream users, OEMs, and resellers to import, use, and sell in the United States the ’518 Accused NAND Flash Products that they manufacture and supply, including through advertising, marketing and sales activities directed at United States sales. On information and belief, Defendants are aware of the size and importance of the United States market for customers of Defendants’ products, and also distribute or supply these products intended for importation, use, and sale in the United States. Defendants routinely market their infringing NAND Flash memory products to third parties for inclusion in products that are sold to customers in the United States, as well as directly to enduser customers. Defendants have publicly stated that their Flash products are targeted for applications such as mobile phones, SSDs, tablets, computers, industrial and automotive applications and removable storage devices, all of which are widely sold and used in the United States. Defendants have numerous direct sales, distributors, and reseller outlets for these products in the United States. Defendants’ marketing efforts show that they have specifically intended to and have induced direct infringement in the United States.
36
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77.
Defendants also provide OEMs, manufacturers, importers, resellers, customers,
and end users instructions, user guides, and technical specifications on how to incorporate the ’518 Accused NAND Flash Products into electronics products that are made, used, sold, offered for sale in and/or imported into the United States. When OEMs, manufacturers, importers, resellers, customers, and end users follow such instructions, user guides, and technical specifications and embed the products in end products and make, use, offer to sell, sell, and/or import them into the United States, they directly infringe one or more claims of the ’518 patent. Defendants know that by providing such instructions, user guides, and technical specifications, OEMs, manufacturers, importers, resellers, customers, and end users follow them, and therefore directly infringe one or more claims of the ’518 patent. Defendants thus know that their actions actively induce infringement. 78.
Defendants have engaged and will continue to engage in additional activities to
specifically target the United States market for the ’518 Accused NAND Flash products and actively induce OEMs, manufacturers, importers, resellers, customers, and end users to directly infringe one or more claims of the ’518 patent in the United States. For example, Defendants have showcased their NAND Flash memory technologies at various industry events, including CES and the Flash Memory Summit, and through written materials distributed in the United States, in an effort to encourage various OEMs, manufacturers, importers, resellers, customers, and end users to include the infringing technology in their computers, mobile devices, removable storage devices and other products. These events are attended by the direct infringers mentioned above and generally by companies that make, use, offer to sell, sell, and/or import into the United States products that use NAND Flash memory components such as those made by Defendants.
37
Case 2:16-cv-01170 Document 1 Filed 10/14/16 Page 38 of 40 PageID #: 38
79.
Defendants derive significant revenue by selling their NAND Flash memory
products to third parties who directly infringe the ’518 patent in the United States. Defendants’ extensive sales and marketing efforts, sales volume, and partnerships all evidence their intent to induce companies to infringe one or more claims of the ’518 patent by, using, offering to sell, selling, or importing products that incorporate the ’518 Accused NAND Flash Products in the United States. Defendants have had specific intent to induce infringement or have been willfully blind to the direct infringement they are inducing. 80.
Defendants’ direct and indirect infringement of the ’518 patent has injured Lone
Star, and Lone Star is entitled to recover damages adequate to compensate for such infringement pursuant to 35 U.S.C. § 284. Unless they cease their infringing activities, Defendants will continue to injure Lone Star by infringing the ’518 patent. 81.
On information and belief, Defendants acted egregiously and with willful
misconduct in that their actions constituted direct or indirect infringement of a valid patent, and this was either known or so obvious that Defendants should have known about it. Defendants continue to infringe the ’518 patent by making, using, selling, offering for sale and importing in the United States the ’518 Accused NAND Flash Products and to induce the direct infringement of others performing these acts, or they have acted at least in reckless disregard of Lone Star’s patent rights. On information and belief, Defendants will continue their infringement notwithstanding actual knowledge of the ’518 patent and without a good faith basis to believe that their activities do not infringe any valid claim of the ’518 patent. All infringement of the ’518 patent following Defendants’ knowledge of the ’518 patent is willful and Lone Star is entitled to treble damages and attorneys’ fees and costs incurred in this action under 35 U.S.C. §§ 284 and 285.
38
Case 2:16-cv-01170 Document 1 Filed 10/14/16 Page 39 of 40 PageID #: 39
PRAYER FOR RELIEF WHEREFORE, Plaintiffs prays for: 1.
Judgment that the ’188, ’085, ’330 and ’518 patents are each valid and
enforceable; 2.
Judgment that the ’188, ’085, ’330 and ’518 patents are infringed by Defendants;
3.
Judgment that Defendants’ acts of patent infringement relating to the patents are
4.
An award of damages arising out of Defendants’ acts of patent infringement,
willful;
together with pre-judgment and post-judgment interest; 5.
Judgment that the damages so adjudged be trebled in accordance with 35 U.S.C.
6.
An award of Plaintiff’s attorneys’ fees, costs and expenses incurred in this action
§ 284;
in accordance with 35 U.S.C. § 285; and 7.
Such other and further relief as the Court may deem just and proper. JURY DEMAND
Plaintiff demands trial by jury of all issues triable of right by a jury. RESERVATION OF RIGHTS Plaintiff’s investigation is ongoing, and certain material information remains in the sole possession of Defendants or third parties, which will be obtained via discovery herein. Plaintiff expressly reserves the right to amend or supplement the causes of action set forth herein in accordance with Rule 15 of the Federal Rules of Civil Procedure.
39
Case 2:16-cv-01170 Document 1 Filed 10/14/16 Page 40 of 40 PageID #: 40
Respectfully submitted, Date: October 14, 2016
/s/ Timothy P. Maloney Timothy P. Maloney (IL 6216483) Joseph F. Marinelli (IL 6270210) Nicole L. Little (IL 6297047) David A. Gosse (IL 6299892) FITCH, EVEN, TABIN & FLANNERY LLC 120 South LaSalle Street, Suite 1600 Chicago, Illinois 60603 Telephone: (312) 577-7000 Facsimile: (312) 577-7007
[email protected] [email protected] [email protected] [email protected] Jennifer P. Ainsworth WILSON, ROBERTSON & CORNELIUS, P.C. 909 ESE Loop 323, Suite 400 Tyler, Texas 75701 (903) 509-5000 Main (903) 509-5001 Direct (903) 509-5092 Fax email:
[email protected] Counsel for Plaintiff
40
JS 44 (Rev. 0/16)
Case 2:16-cv-01170 Document 1-1 Filed 10/14/16 Page 1 of 2 PageID #: 41
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Lone Star Silicon Innovations LLC
Toshiba Corporation; Toshiba America, Inc.; Toshiba America Electronics Components, Inc.; SanDisk Corporation; Western Digital Corporation
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CHECK YES only if demanded in complaint: u Yes u No JURY DEMAND: DOCKET NUMBER 2:16-cv-1116, 2:16-cv-1117
SIGNATURE OF ATTORNEY OF RECORD
/s/ Timothy P. Maloney
10/14/2016 FOR OFFICE USE ONLY RECEIPT #
AMOUNT
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Case 2:16-cv-01170 Document 1-1 Filed 10/14/16 Page 2 of 2 PageID #: 42
JS 44 Reverse (Rev. 0/16)
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Case 2:16-cv-01170 Document 1-2 Filed 10/14/16 Page 1 of 12 PageID #: 43
EXHIBIT A
Case 2:16-cv-01170 Document 1-2 Filed Page 2 of #: 44 IIIIII10/14/16 IIIIIIII Ill lllll lllll lllll lllll lllll12 lllll PageID lllll lllll 111111111111111111 US005912188A
United States Patent
[19J
Gardner et al.
[11]
Patent Number:
[45]
Date of Patent:
5,912,188 Jun.15,1999
[54]
METHOD OF FORMING A CONTACT HOLE IN AN INTERLEVEL DIELECTRIC LAYER USING DUAL ETCH STOPS
Primary Examiner-William Powell Attorney, Agent, or Firm----Skjerven, Morrill, MacPherson, Franklin & Friel, L.L.P.
[75]
Inventors: Mark I. Gardner, Cedar Creek; Daniel Kadosh; Frederick N. Hause, both of Austin, all of Tex.
[57]
[73]
Assignee: Advanced Micro Devices, Inc., Sunnyvale, Calif.
[21]
Appl. No.: 08/905,686
[22]
Filed:
[51] [52] [58]
Aug. 4, 1997 6
Int. Cl. ..................................................... HOlL 21/00 U.S. Cl. .......................... 438/740; 438/637; 438/675; 438/733; 438/738 Field of Search ..................................... 438/576, 578, 438/586, 618, 630, 637, 638, 649, 675, 682,692,733,738,740,743,744 References Cited
[56]
U.S. PATENT DOCUMENTS 4,717,449 1/1988 Erie et al. ............................... 437/195 4,943,539 7/1990 Wilson et al. .......................... 437/195 5,110,712 5/1992 Kessler et al. .......................... 430/312 5,162,260 11/1992 Leibovitz et al. ...................... 437/195 5,275,972 1/1994 Ogawa et al. ...................... 438/740 X 5,451,543 9/1995 Woo et al. .............................. 437/195 5,472,825 12/1995 Sayka ...................................... 430/311 5,612,254 3/1997 Mu et al. ................................ 437/195
OIBER PUBLICATIONS Wolf, Stanley, Silicon Processing for the VLSI Era, vol. 2: Process Integration, Lattice Press, Sunset Beach, California, 1990, pp. 101-111; 189-199; 240-259; 276-283. Higelin, G. et al., "Double Level Interconnection System For Submicron CMOS Applications," VLSI Multilevel Interconnection Conference, Jun. 13-14, 1988, pp. 29-34.
ABSTRACT
A method of forming a contact hole in an interlevel dielectric layer using dual etch stops includes the steps of providing a semiconductor substrate, forming a gate over the substrate, forming a source/drain region in the substrate, providing a source/drain contact electrically coupled to the source/drain region, forming an interlevel dielectric layer that includes first, second and third dielectric layers over the source/drain contact, forming an etch mask over the interlevel dielectric layer, applying a first etch which is highly selective of the first dielectric layer with respect to the second dielectric layer through an opening in the etch mask using the second dielectric layer as an etch stop, thereby forming a first hole in the first dielectric layer that extends to the second dielectric layer without extending to the third dielectric layer, applying a second etch which is highly selective of the second dielectric layer with respect to the third dielectric layer through the opening in the etch mask using the third dielectric layer as an etch stop, thereby forming a second hole in the second dielectric layer that extends to the third dielectric layer without extending to the source/drain contact, and applying a third etch which is highly selective of the third dielectric layer with respect to the source/drain contact through the opening in the etch mask, thereby forming a third hole in the third dielectric layer that extends to the source/drain contact, wherein the first, second and third holes in combination provide the contact hole. In this manner, the contact hole is formed in the interlevel dielectric without any appreciable gouging of the underlying materials.
30 Claims, 4 Drawing Sheets
148 144 146 132
130
142 140
Case 2:16-cv-01170 Document 1-2 Filed 10/14/16 Page 3 of 12 PageID #: 45
U.S. Patent
Jun.15,1999
130 126
128 106 132 102
N+
N+
5,912,188
Sheet 1 of 4
N+
N+ 136
134
138 104
FIG. 1A
1461
144
130
128
142
N+
N+
N+
140
P-
P-
FIG. 18
144
N+
N+
N+
FIG. 1C
N+
Case 2:16-cv-01170 Document 1-2 Filed 10/14/16 Page 4 of 12 PageID #: 46
U.S. Patent
Jun.15,1999
5,912,188
Sheet 2 of 4
148 144
N+
N+
N+
P-
N+ P-
FIG. 1D
144 142
N+ P-
P-
FIG. 1E
142 132
N+
N+ P-
140
N+
134
136 PFIG. 1F
138
Case 2:16-cv-01170 Document 1-2 Filed 10/14/16 Page 5 of 12 PageID #: 47
U.S. Patent
Jun.15,1999
Sheet 3 of 4
5,912,188
144 130
142 140
FIG. 1G
150
156
154
132
N+
N+ P- 134
136 PFIG. 1H
150
FIG. 11
138
Case 2:16-cv-01170 Document 1-2 Filed 10/14/16 Page 6 of 12 PageID #: 48
U.S. Patent
Jun.15,1999
Sheet 4 of 4
170
N+ FIG. 1J
5,912,188
Case 2:16-cv-01170 Document 1-2 Filed 10/14/16 Page 7 of 12 PageID #: 49 5,912,188
1
2
METHOD OF FORMING A CONTACT HOLE IN AN INTERLEVEL DIELECTRIC LAYER USING DUAL ETCH STOPS
the etch is highly anisotropic and forms contact holes with straight vertical sidewalls that taper slightly. The etch rate depends on several factors including pressure, power, feed gas composition, and film characteristics. For instance, thermally grown silicon dioxide etches more slowly than chemical vapor deposited silicon dioxide. In addition, the etch can be highly selective of silicon dioxide with respect to underlying silicon.
BACKGROUND OF THE INVENTION
5
1. Field of the Invention The present invention relates to integrated circuit manufacturing, and more particularly to forming a contact Dry etch equipment requires the availability of effective hole in an interlevel dielectric layer. 10 end-point detection tools for reducing the degree of 2. Description of Related Art overetching, increasing throughput and achieving run-to-run An insulated-gate field-effect transistor (IGFE1), such as reproducibility. Four common methods for determining the a metal-oxide semiconductor field-effect transistor end-point of dry etch processes are 1) laser interferometry (MOSFET), uses a gate to control an underlying surface and reflectivity, 2) optical emission spectroscopy, 3) direct channel joining a source and a drain. The channel, source 15 observation through a viewing port on the chamber by a and drain are located in a semiconductor substrate, with the human operator, and 4) mass spectroscopy. End-point detecsource and drain being doped oppositely to the substrate. tion of contact holes can be difficult because the total area The gate is separated from the semiconductor substrate by a being etched is quite small compared to other layers. thin insulating layer such as a gate oxide. The operation of Furthermore, in many integrated circuits, individual the IGFET involves application of an input voltage to the 20 devices in various areas are arranged in different configugate, which sets up a transverse electric field in the channel rations and densities. For example, some integrated circuits in order to modulate the longitudinal conductance of the include devices having a wide range of functionality with channel. the variability of functionality being reflected in a variability Refractory metal silicides are frequently used to provide 25 of layout configuration. One implication arising from the low resistance contacts for the gate, source and drain. With variability of configuration is that some areas of the intethis approach, a thin layer of refractory metal is deposited grated circuit are densely populated with devices while other over the structure, and heat is applied to form a silicide areas include only relatively isolated devices. wherever the refractory metal is adjacent to silicon Applicant has observed that when silicon dioxide is dry (including single crystal silicon and polysilicon). Thereafter, an etch is applied that removes unreacted refractory metal to 30 etched, the etch rate of contact holes is often slower in densely populated areas of the substrate (with a high density prevent bridging, silicide contacts for the gate, source and of contact holes) than in sparsely populated areas of the drain. substrate (with a low density of contact holes). The differThe devices must be selectively interconnected to form circuit patterns. As one approach, a first interlevel dielectric 35 ence in etch rates may result from poorly-understood aspects of the chemistry of the plasma etching, such as increasing is formed over the substrate, first contact holes (or vias) are the rate of reactive ion etching in areas having a low density etched in the first interlevel dielectric to expose the silicide of contact holes and therefore less of the silicon dioxide contacts, first metal plugs are formed in the first contact layer exposed to the etch. Irrespective of the causes, since holes, and a metal-1 pattern is formed over the first interlevel dielectric that selectively interconnects the first metal plugs. 40 etched silicon beneath certain contact holes may be detected before other contact holes are completely etched, an Thereafter, a second interlevel dielectric is formed over the overetch becomes necessary to ensure complete formation metal-1 pattern, second contact holes are etched in the of all the contact holes. Unfortunately, the overetching can second interlevel dielectric to expose the metal-1 pattern, cause appreciable gouging of the underlying materials second metal plugs are formed in the second contact holes, and a metal-2 pattern is formed over the second interlevel 45 beneath the contact holes. For instance, the overetching can damage the silicon surface of source/drain regions, damage dielectric that selectively interconnects the second metal or remove thin silicide contacts, remove substantial portions plugs. Additional interlevel dielectrics and metal patterns of oxide spacers adjacent to the gate, and/or remove sub(such as metal-3, metal-4 and metal-5) can be formed in a stantial portions of field oxides such as trench oxides or similar manner. LOCOS in the substrate. The gouging increases the potential Forming contact holes in the first interlevel dielectric is a 50 for excessive leakage current as well as device failure. key step in the fabrication of multilevel interconnect strucOne solution known in the art is to form an interlevel tures. The minimum size of the contact holes is usually dielectric layer with a thick silicon dioxide layer on a thin determined by the minimum resolution of the optical lithogsilicon nitride layer. A first etch is applied which is highly raphy tool. When contact holes are larger than about 2.0 microns, wet etching is often used. However, the isotropic 55 selective of silicon dioxide with respect to silicon nitride to form holes in the silicon dioxide layer using the silicon nature of wet chemical etching makes it generally unsuitable nitride layer as an etch stop. This allows the first etch to have for patterning submicron contact holes. Since the first intera sufficiently long duration without damaging the underlying level dielectric is typically silicon dioxide, dry etching for materials. Thereafter, a second etch is briefly applied which silicon dioxide is often used to form submicron contact is highly selective of silicon nitride to complete formation of holes. 60 the contact hole. A drawback to this approach, however, is Dry etching silicon dioxide typically involves a plasma that the second etch is usually highly selective of silicon as etching procedure in which a plasma generates reactive gas well. As a result, substantial damage to an underlying silicon species that chemically etch the material in direct proximity surface may arise. to the plasma. The ability to achieve anisotropic etching requires bombardment of the silicon dioxide with energetic 65 Accordingly, a need exists for a method of forming a contact hole in an interlevel dielectric without appreciably ions. Other parameters such as the chemical nature of the gouging the underlying materials. plasma also influence the degree of anisotropy. In general,
Case 2:16-cv-01170 Document 1-2 Filed 10/14/16 Page 8 of 12 PageID #: 50 5,912,188 3
4
SUMMARY OF THE INVENTION dielectric layer that contacts the conductive plug. If desired, the conductive plug can provide a local interconnect to a An object of the invention is to provide a contact hole in second source/drain contact exposed by the contact hole. an interlevel dielectric without any appreciable gouging of the underlying materials. Generally speaking, this is accomThe source/drain contact can be a silicide contact formed plished by forming an interlevel dielectric with first, second 5 on the source/drain region, or alternatively the source/drain and third dielectric layers, etching a first hole in the first contact can be the source/drain region itself. dielectric layer using the second dielectric layer as an etch These and other objects, features and advantages of the stop, etching a second hole in the second dielectric layer invention will be further described and more readily apparusing the third dielectric layer as an etch stop, and etching ent from a review of the detailed description of the preferred a third hole in the third dielectric layer. 10 embodiments which follows. In accordance with one aspect of the invention, a method of forming a contact hole in an interlevel dielectric layer BRIEF DESCRIPTION OF THE DRAWINGS using dual etch stops includes the steps of providing a semiconductor substrate, forming a gate over the substrate, The following detailed description of the preferred forming a source/drain region in the substrate, providing a 15 embodiments can best be understood when read in conjuncsource/drain contact electrically coupled to the source/drain tion with the following drawings, in which: region, forming an interlevel dielectric layer that includes FIGS. lA-lJ show cross-sectional views of successive first, second and third dielectric layers over the source/drain process steps for forming a contact hole in an interlevel contact, forming an etch mask over the interlevel dielectric dielectric layer in accordance with an embodiment of the layer, applying a first etch which is highly selective of the 20 invention. first dielectric layer with respect to the second dielectric layer through an opening in the etch mask using the second DETAILED DESCRIPTION OF THE dielectric layer as an etch stop, thereby forming a first hole PREFERRED EMBODIMENTS in the first dielectric layer that extends to the second dielectric layer without extending to the third dielectric layer, 25 In the drawings, depicted elements are not necessarily applying a second etch which is highly selective of the drawn to scale and like or similar elements may be desigsecond dielectric layer with respect to the third dielectric nated by the same reference numeral throughout the several layer through the opening in the etch mask using the third views. dielectric layer as an etch stop, thereby forming a second In FIG. lA, a silicon substrate suitable for integrated hole in the second dielectric layer that extends to the third 30 circuit manufacture is provided. The substrate includes a Pdielectric layer without extending to the source/drain type epitaxial surface layer on a P+ base layer (not shown). contact, and applying a third etch which is highly selective The epitaxial surface layer has a boron background concenof the third dielectric layer with respect to the source/drain tration on the order of lxl0 15 atoms/cm 3 , a <100> orientacontact through the opening in the etch mask, thereby tion and a resistivity of 12 ohm-cm. Active regions 102 and forming a third hole in the third dielectric layer that extends 35 104 of the substrate are shown. Trench oxide 106 composed to the source/drain contact, wherein the first, second and of silicon dioxide (Si0 2 ) is formed in the substrate and third holes in combination provide the contact hole. provides dielectric isolation between active regions 102 and Preferably, the first, second and third etches are anisotro104. Active regions 102 and 104 are subjected to a well pic etches that form the contact hole with straight sidewalls, implant, a punchthrough implant, and a threshold adjust and the interlevel dielectric layer is planarized by chemical- 40 implant. The well implant provides a more uniform backmechanical polishing before forming the etch mask. It is also ground doping, the punchthrough implant provides greater preferred that the gate have a greater thickness than a robustness to punchthrough voltages, and the threshold combined thickness of the second and third dielectric layers, voltage implant shifts the threshold voltage to a desired and that the first dielectric layer have a greater thickness than value such as 0.4 to 0.7 volts. Gate oxides 110 and 112 the gate. 45 composed of silicon dioxide are formed on the top surface As exemplary materials, the gate is polysilicon, the etch of active regions 102 and 104, respectively, using tube growth at a temperature of 700 to 1000° C. in an 0 2 mask is photoresist, the first and third dielectric layers are containing ambient. Thereafter, a polysilicon layer with a silicon dioxide or silicon oxyfluoride, and the second dielecthickness of 2000 angstroms is deposited over the structure tric layer is silicon nitride, silicon oxynitride, hydrogen silsesquioxane, fluorinated polyimide, poly- 5 0 by chemical vapor deposition and patterned using photolithography and an etch step to form polysilicon gates 114 and phenylquinoxaline, polyquinoline, or methysilsesquixane polymer. 116 on gate oxides 110 and 112, respectively. Polysilicon gates 114 and 116 each have a length of 3500 angstroms Advantageously, the first etch can have a long duration to between opposing sidewalls. ensure that the first hole is completely etched through a thick first dielectric layer without etching the third dielectric layer, 55 Lightly doped source and drain regions 120 and 122 are the second etch can be highly selective of the source/drain implanted into active region 102 and lightly doped source contact without etching the source/drain contact, and the and drain regions 124 and 126 are implanted into active third etch can have a brief duration and can be unselective region 104 by subjecting the structure to ion implantation of of the source/drain contact to ensure that the third hole is phosphorus, at a dose of lxl013 to 5xl0 14 atoms/cm 2 and an completely etched through a thin third dielectric layer with- 60 energy of 2 to 35 kiloelectron-volts, using polysilicon gate out any appreciable gouging to the source/drain contact. 114 as an implant mask for active region 102 and using Moreover, even if the third etch is highly selective of other polysilicon gate 116 as an implant mask for active region materials (such as oxide spacers or field oxide) beneath the 104. Lightly doped source and drain regions 120, 122, 124 contact hole, the brief duration of the third etch prevents any and 126 are doped N- with a phosphorus concentration of 17 appreciable gouging to these materials as well. 65 lxl0 to lxl0 18 atoms/cm 3 and form channel junctions Thereafter, a conductive plug can be formed in the contact substantially aligned with the opposing sidewalls of polyhole, and a metal-1 pattern can be formed on the first silicon gates 114 and 116. Thereafter, an oxide layer with a
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thickness of 1500 angstroms is conformally deposited over In FIG. lE, a long anisotropic reactive ion etch is applied the exposed surfaces by plasma enhanced chemical vapor that is highly selective of silicon dioxide with respect to deposition at a temperature of 300 to 450° C., and an silicon nitride using photoresist layer 148 as an etch mask and using nitride layer 142 as an etch stop. The etch forms anisotropic reactive ion etch is applied that is highly selective of silicon dioxide with respect to silicon to form oxide 5 holes in oxide layer 144 that extend to nitride layer 142. The etch removes only a negligible amount of nitride layer 142, spacers 128 and 130 adjacent to the opposing sidewalls of polysilicon gates 114 and 116, respectively. The anisotropic and the materials beneath nitride layer 142 are protected and etch also removes portions of the gate oxides outside polyunaffected. Nitride layer 142 allows a long overetch to silicon gates 114 and 116 and oxide spacers 128 and 130. assure that the holes are completely formed in all regions of Next, heavily doped source and drain regions 132 and 134 oxide layer 144 beneath the openings in photoresist layer 10 are implanted into active region 102 and heavily doped 148. Although the etch is highly selective of trench oxide source and drain regions 136 and 138 are implanted into 106 and oxide spacers 128 and 130, nitride layer 142 active region 104 by subjecting the structure to ion implanprevents the etch from reaching these regions. tation of arsenic, at a dose of lxl0 15 to 5xl0 15 atoms/cm 2 In FIG. lF, the etch chemistry is changed and a brief and an energy of 10 to 80 kiloelectron-volts, using polysilianisotropic reactive ion etch is applied that is highly seleccon gate 114 and oxide spacers 128 as an implant mask for 15 tive of silicon nitride with respect to silicon dioxide using active region 102 and using polysilicon gate 116 and oxide photoresist layer 148 as an etch mask and using oxide layer spacers 130 as an implant mask for active region 104. 140 as an etch stop. The etch forms holes in nitride layer 142 Heavily doped source and drain regions 132, 134, 136 and that extend to oxide layer 140. The etch removes only a 138 are doped N+ with an arsenic concentration of lxl0 18 to lxl020 atoms/cm 3 . The device is then annealed to remove 20 negligible amount of oxide layer 140, and the materials beneath oxide layer 140 are protected and unaffected. crystalline damage and to drive-in and activate the Although the etch is highly selective of heavily doped implanted dopants by applying a rapid thermal anneal on the source and drain regions 132, 134, 136 and 138, oxide layer order of 950 to 1050° C. for 10 to 30 seconds. As a result, 140 prevents the etch from reaching these regions. a first N-channel IGFET is formed with a source (consisting of source regions 120 and 132) and a drain ( consisting of 25 In FIG. lG, the etch chemistry is changed again and a drain regions 122 and 134) controlled by polysilicon gate brief anisotropic reactive ion etch is applied that is highly 114, and a second N-channel IGFET is formed with a source selective of silicon dioxide with respect to silicon nitride ( consisting of source regions 124 and 136) and a drain using photoresist layer 148 as an etch mask. The etch forms ( consisting of drain regions 126 and 138) controlled by holes in oxide layer 140 that extend to trench oxide 106, polysilicon gate 116. 30 heavily doped source and drain regions 132, 134, 136 and In FIG. lB, oxide layer 140 with a thickness of 50 to 200 138, and the left-side oxide spacer 130. Trench oxide 106 angstroms is conformally deposited over the exposed surand heavily doped source and drain regions 132, 134, 136 faces by plasma enhanced chemical vapor deposition at a and 138 are intended to be exposed, however the left-side temperature of 300 to 450° C. Oxide layer 140 contacts oxide spacer 130 is exposed due to misalignment of the trench oxide 106, polysilicon gates 114 and 116, oxide 35 overlying opening in photoresist layer 148. Advantageously, spacers 128 and 130, and heavily doped source and drain the etch is brief and non-selective of silicon, and therefore regions 132, 134, 136 and 138. Thereafter, nitride layer 142 removes only a negligible amount of heavily doped source composed of silicon nitride (Si 3 N4 ) with a thickness of 100 and drain regions 132, 134, 136 and 138. Moreover, to 300 angstroms is conformally deposited on oxide layer although the etch is highly selective of silicon dioxide, since 140 by plasma enhanced chemical vapor deposition at a 40 the etch is brief it removes only slight amounts of trench temperature of 300 to 800° C. Nitride layer 142 does not oxide 106 and the exposed oxide spacer 130. The holes in contact any material beneath oxide layer 140. Thereafter, oxide layer 140, nitride layer 142 and oxide layer 144 in oxide layer 144 with a thickness of 12,000 to 15,000 combination provide contact holes in interlevel dielectric angstroms is conformally deposited on nitride layer 142 by layer 146. The contact holes have straight sidewalls that are plasma enhanced chemical vapor deposition at a temperature 45 substantially vertical. Of importance, the contact holes are of 300 to 450° C. Oxide layer 144 does not contact any formed without any appreciable gouging to the materials material beneath nitride layer 142. As is seen, the top beneath oxide layer 140. surfaces of oxide layer 140, nitride layer 142 and oxide layer In FIG. lH, photoresist layer 148 is stripped, a titanium 144 are substantially non-planar and reflect the topography layer with a thickness of 100 to 350 angstroms is deposited of polysilicon gates 114 and 116 and oxide spacers 128 and 50 on the exposed surfaces, a rapid thermal anneal on the order 130. The combination of oxide layer 140, nitride layer 142 of 700° C. for 30 seconds is applied in a nitrogen ambient and oxide layer 144 forms an interlevel dielectric layer 146 to form titanium silicide contacts 150, 152, 154, and 156 on between polysilicon gates 114 and 116 and a metal-1 pattern heavily doped source and drain regions 132, 134, 136 and to be subsequently formed. 138, respectively, the unreacted titanium (including titanium In FIG. lC, oxide layer 144 is planarized by applying 55 nitride) on the silicon dioxide and silicon nitride is stripped, chemical-mechanical polishing. As a result, oxide layer 144 and a rapid thermal anneal on the order of 750 to 800° C. for has a planar top surface about 10,000 angstroms above 30 seconds is applied to lower the resistivity of the titanium polysilicon gates 114 and 116. silicide contacts. In FIG. lD, photoresist layer 148 is deposited on oxide In FIG. 11, a thin titanium layer and then a thin titanium layer 144. A photolithographic system, such as a step and 60 nitride layer are sputter deposited over the structure to form repeat optical projection system which generates deep ultraan adhesion liner that covers the top surface of oxide layer violet light from a mercury-vapor lamp, uses a reticle to 144, the sidewalls of the contact holes, titanium silicide irradiate photoresist layer 148 with an image pattern. contacts 150, 152, 154 and 156 and trench oxide 106, a thick Thereafter, the irradiated portions of photoresist layer 148 tungsten layer is sputter deposited on the adhesion liner and are removed, and photoresist layer 148 includes openings 65 fills the remaining space in the contact holes, and structure is planarized by applying chemical-mechanical polishing to that define contact holes to be subsequently formed in remove the adhesion liner and tungsten above the contact interlevel dielectric layer 146.
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holes. As a result, conductive plugs 160, 162 and 164 are drain region, and a source/drain contact can be a source formed in the contact holes and are aligned with the top contact or a drain contact. surface of oxide layer 144. Conductive plugs 160, 162 and Preferably, the gate has a greater thickness than a com164 each include the adhesion liner (shown as a single layer) bined thickness of the second and third dielectric layers, and and the tungsten. In addition, conductive plug 160 includes 5 that the first dielectric layer has a greater thickness than the titanium silicide contact 150, conductive plug 160 includes gate. More preferably, the first dielectric layer accounts for titanium silicide contacts 152 and 154, and conductive plug at least 95 percent of the thickness of the interlevel dielectric 164 includes titanium silicide contact 156. Conductive plugs layer. The precise thickness of the second and third dielectric 160 and 164 have diameters of 3500 to 4500 angstroms. layers will depend on the etch selectivities and the desired Conductive plug 162 is considerably larger and provides a 10 safety margins. Preferably, the etch selectivities of the local interconnect between heavily doped drain region 134 highly selective etches are at least 10: 1. It is desirable to have a thin second dielectric layer so that a brief second etch and heavily doped source region 136. can be used, and to have a thin third dielectric layer so that In FIG. 11, an aluminum layer with a thickness of 6000 a brief third etch can be used. It is especially desirable to angstroms is sputter deposited over the structure and patterned using photolithography and an etch step to form a 15 have a thin second dielectric layer if it has a higher dielectric constant than the first dielectric layer, since reducing the metal-1 pattern that includes aluminum lines 170, 172 and dielectric constant of the interlevel dielectric layer reduces 174 in contact with conductive plugs 160, 162 and 164, interlevel capacitance and increases switching speeds. For respectively. Aluminum lines 170, 172 and 174 have lininstance, silicon dioxide has a dielectric constant of 3.9 and ewidths of 4000 to 6000 angstroms. silicon nitride has a dielectric constant of 7.5, therefore a Accordingly, a multilevel structure is formed first and 20 silicon nitride layer sandwiched between silicon dioxide second N-channel IGFETs, a metal-1 pattern, and an interlayers should be as thin as possible. level dielectric layer therebetween. Conductive plugs in the The first, second and third etches are preferably anisotrocontact holes interconnect the metal-1 pattern to source/ pic etches so that the contact holes have straight sidewalls drain regions of the IGFETs. Advantageously, there is no that do not undercut the etch mask. However, when the appreciable gouging of the materials beneath the contact 25 second and third dielectric layers are thin, the second and holes. third etches can be brief wet chemical etches that cause little or no undercutting. The present invention includes numerous variations to the embodiment described above. For instance, the interlevel As can be appreciated, the misalignment of the photoresist layer in the embodiment described above is not necesdielectric layer can include first (upper), second (intermediate) and third (lower) dielectric layers of various 30 sary or even desirable, but illustrates that such misalignment results in only slight damage to the exposed oxide spacer. materials as long as the first etch is highly selective of the Therefore, alignment tolerances may be relaxed to yield a first dielectric layer with respect to the second dielectric more forgiving and less expensive process without unduly layer (such that the etch rate of the first dielectric layer is far increasing the potential for device failure. greater than the etch rate of the second dielectric layer), and The invention is particularly well-suited for contact holes the second etch is highly selective of the second dielectric 35 over N-channel MOSFETs, P-channel MOSFETs and other layer with respect to the third dielectric layer (such that the types of IGFETs, particularly for high-performance microetch rate of the second dielectric layer is far greater than the processors where high circuit density is essential. Although etch rate of the third dielectric layer). Preferably, the third a single pair of N-channel devices with an overlying interetch is highly selective of the third dielectric layer with level dielectric layer and metal-1 pattern have been shown respect to the source/drain contact (such that the etch rate of 40 for purposes of illustration, it is understood that in actual the third dielectric layer is far greater than the etch rate of the practice, many devices are fabricated on a single semiconsource/drain contact). For instance, when the first and third ductor wafer as widely practiced in the art. Accordingly, the dielectric layers are silicon dioxide or silicon oxyfluoride, invention is well-suited for use in an integrated circuit chip, suitable materials for the second dielectric layer include as well as an electronic system including a microprocessor, silicon nitride, silicon oxynitride, hydrogen silsesquioxane, 45 a memory and a system bus. fluorinated polyimide, poly-phenylquinoxaline, Those skilled in the art will readily implement the steps polyquinoline, and methysilsesquixane polymer. Various necessary to provide the structures and methods disclosed conductors and dielectrics can be used for the gate and gate herein, and will understand that the process parameters, insulator, respectively. Similarly, the conductive plug and metal-1 pattern can include various metals and related 50 materials, and dimensions are given by way of example only and can be varied to achieve the desired structure as well as compounds. For instance, the conductive plug can include modifications which are within the scope of the invention. tungsten, tantalum, titanium, titanium nitride, molybdenum, Variations and modifications of the embodiments disclosed polysilicon, or a silicide, and the metal-1 pattern can include herein may be made based on the description set forth aluminum, aluminum alloys, copper, gold, silver, tungsten herein, without departing from the scope and spirit of the or molybdenum. 55 invention as set forth in the following claims. The source/drain regions of the substrate can provide What is claimed is: source/drain contacts for the conductive plugs, as described 1. A method of forming a contact hole in an interlevel above. Alternatively, silicide contacts can be formed on the dielectric layer using dual etch stops, comprising: source/drain regions before forming the interlevel dielectric providing a semiconductor substrate; layer, in which case the silicide contacts provide the source/ 60 forming a gate over the substrate, drain contacts. In either case, the source/drain contacts are forming a source/drain region in the substrate; electrically coupled to the source/drain regions, are subproviding a source/drain contact electrically coupled to jected to the third etch, are exposed by the contact holes, and the source/drain region; are adjacent to the conductive plugs formed in the contact forming an interlevel dielectric layer that includes first, holes. Note, when used in this context, "source/drain 65 second and third dielectric layers over the source/drain regions" include source regions and drain regions. contact; Therefore, a source/drain region can be a source region or a
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forming an etch mask over the interlevel dielectric layer; forming an etch mask over the interlevel dielectric layer; applying a first etch which is highly selective of the first applying a first anisotropic etch which is highly selective dielectric layer with respect to the second dielectric of the first dielectric layer with respect to the second layer through an opening in the etch mask using the dielectric layer through an opening in the etch mask second dielectric layer as an etch stop, thereby forming 5 using the second dielectric layer as an etch stop, a first hole in the first dielectric layer that extends to the thereby forming a first hole in the first dielectric layer second dielectric layer without extending to the third that extends to the second dielectric layer without dielectric layer; extending to the third dielectric layer; applying a second anisotropic etch which is highly selecapplying a second etch which is highly selective of the tive of the second dielectric layer with respect to the second dielectric layer with respect to the third dielec- 10 tric layer through the opening in the etch mask using third dielectric layer through the opening in the etch the third dielectric layer as an etch stop, thereby formmask using the third dielectric layer as an etch stop, ing a second hole in the second dielectric layer that thereby forming a second hole in the second dielectric extends to the third dielectric layer without extending layer that extends to the third dielectric layer without 15 to the source/drain contact; and extending to the source/drain contact; and applying a third etch which is highly selective of the third applying a third anisotropic etch which is highly selective dielectric layer with respect to the source/drain contact of the third dielectric layer with respect to the source/ through the opening in the etch mask, thereby forming drain contact through the opening in the etch mask, a third hole in the third dielectric layer that extends to thereby forming a third hole in the third dielectric layer the source/drain contact, wherein the first, second and 20 that extends to the source/drain contact, wherein the third holes in combination provide a contact hole in the first, second and third holes in combination provide a interlevel dielectric layer. contact hole in the interlevel dielectric layer. 2. The method of claim 1, wherein the gate has a greater 12. The method of claim 11, wherein the second anisothickness than a combined thickness of the second and third tropic etch is highly selective of the source/drain contact 25 dielectric layers. with respect to the third dielectric layer. 3. The method of claim 1, wherein the first, second and 13. The method of claim 11, wherein the source/drain third etches are anisotropic etches and the contact hole has contact is the source/drain region. straight sidewalls. 14. The method of claim 11, wherein the source/drain 4. The method of claim 1, wherein the second etch is contact is a silicide contact on the source/drain region. highly selective of the source/drain contact with respect to 30 15. The method of claim 11, wherein the interlevel the third dielectric layer. dielectric layer consists of the first, second and third dielec5. The method of claim 1, wherein the source/drain tric layers. contact is the source/drain region. 16. The method of claim 11, wherein the first and third 6. The method of claim 1, wherein the source/drain dielectric layers are the same material. 35 contact is a silicide contact on the source/drain region. 17. The method of claim 16, wherein the first and third 7. The method of claim 1, wherein the first and third dielectric layers are selected from the group consisting of dielectric layers are selected from the group consisting of silicon dioxide and silicon oxyfluoride, and the second silicon dioxide and silicon oxyfluoride, and the second dielectric layer is selected from the group consisting of dielectric layer is selected from the group consisting of silicon nitride, silicon oxynitride, hydrogen silsesquioxane, silicon nitride, silicon oxynitride, hydrogen silsesquioxane, 40 fluorinated polyimide, poly-phenylquinoxaline, fluorinated polyimide, poly-phenylquinoxaline, polyquinoline, and methysilsesquixane polymer. polyquinoline, and methysilsesquixane polymer. 18. The method of claim 11, wherein the gate is polysili8. The method of claim 1, wherein the gate is polysilicon con and the etch mask is photoresist. and the etch mask is photoresist. 19. The method of claim 11, including forming a conduc9. The method of claim 1, including manufacturing an 45 tive plug in the contact hole that contacts the source/drain integrated circuit chip that includes the interlevel dielectric contact. layer. 20. The method of claim 19, including forming a metal-1 10. The method of claim 1, including manufacturing an pattern on the first dielectric layer that contacts the conducelectronic system that includes a microprocessor, a memory tive plug. and a system bus, and that further includes the interlevel 50 21. A method of forming a contact hole in an interlevel dielectric layer. dielectric layer using dual etch stops, comprising the 11. A method of forming a contact hole in an interlevel sequence set forth: dielectric layer using dual etch stops, comprising: providing a semiconductor substrate; providing a semiconductor substrate; forming a gate oxide over the substrate; 55 forming a gate insulator over the substrate; forming a polysilicon gate on the gate oxide; forming a gate on the gate insulator; forming a source/drain region in the substrate and proforming a source/drain region in the substrate; viding a source/drain contact electrically coupled to the source/drain region, wherein a distance between a top providing a source/drain contact electrically coupled to surface of the polysilicon gate and the substrate is the source/drain region; 60 greater than a distance between a top surface of the forming an interlevel dielectric layer that includes first, source/drain contact and the substrate; second and third dielectric layers over the source/drain forming an interlevel dielectric layer that consists of first, contact, including forming the first dielectric layer on second and third dielectric layers over the source/drain the second dielectric layer and forming the second contact, including forming the first dielectric layer on dielectric layer on the third dielectric layer, wherein the 65 gate has a greater thickness than a combined thickness the second dielectric layer, forming the second dielecof the second and third dielectric layers; tric layer on the third dielectric layer, and forming the
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third dielectric layer on the source/drain contact, 23. The method of claim 21, wherein the source/drain wherein the first and third dielectric layers are the same contact is the source/drain region. material, the polysilicon gate has a greater thickness 24. The method of claim 21, wherein the source/drain than a combined thickness of the second and third contact is a silicide contact on the source/drain region. dielectric layers, and the first dielectric layer has a 5 25. The method of claim 21, wherein the first and third greater thickness than the polysilicon gate; dielectric layers are the same material. forming a photoresist layer on the interlevel dielectric 26. The method of claim 25, wherein the first and third layer; dielectric layers are selected from the group consisting of applying a first anisotropic etch which is highly selective silicon dioxide and silicon oxyfluoride. of the first dielectric layer with respect to the second 10 27. The method of claim 26, wherein the second dielectric dielectric layer through an opening in the photoresist layer is selected from the group consisting of silicon nitride, layer using the photoresist layer as an etch mask and the silicon oxynitride, hydrogen silsesquioxane, fluorinated second dielectric layer as an etch stop, thereby forming polyimide, polyphenylquinoxaline, polyquinoline, and a first hole in the first dielectric layer that extends to the methysilsesquixane polymer. second dielectric layer without extending to the third 15 28. The method of claim 21, including planarizing the dielectric layer; interlevel dielectric by applying chemical-mechanical polapplying a second anisotropic etch which is highly selecishing before forming the photoresist layer. tive of the second dielectric layer with respect to the 29. The method of claim 21, including the following steps third dielectric layer through the opening in the pho- 20 in the sequence set forth: toresist layer using the photoresist layer as an etch stripping the photoresist layer after forming the contact mask and the third dielectric layer as an etch stop, hole; thereby forming a second hole in the second dielectric forming a conductive plug in the contact hole that conlayer that extends to the third dielectric layer without tacts the source/drain contact; and extending to the source/drain contact; and 25 forming a metal-1 pattern on the first dielectric layer that applying a third anisotropic etch which is highly selective contacts the conductive plug. of the third dielectric layer with respect to the source/ 30. The method of claim 29, wherein: drain contact through the opening in the photoresist the contact hole exposes the source/drain contact, a layer using the photoresist layer as an etch mask, dielectric isolation region in the substrate, and a second thereby forming a third hole through the third dielectric 30 source/drain contact electrically coupled to a second layer that extends to the source/drain contact, wherein source/drain region in the substrate; and the first, second and third holes in combination provide a contact hole with straight sidewalls in the interlevel the conductive plug provides a local interconnect between dielectric layer. the source/drain contact and the second source/drain 22. The method of claim 21, wherein the second aniso- 35 contact. tropic etch is highly selective of the source/drain contact with respect to the third dielectric layer. * * * * *
Case 2:16-cv-01170 Document 1-3 Filed 10/14/16 Page 1 of 19 PageID #: 55
EXHIBIT B
Case 2:16-cv-01170 Document 1-3 Filed Page 2 of PageID #: 56 IIIIII10/14/16 IIIIIIII Ill lllll lllll lllll lllll lllll19 lllll lllll lllll 111111111111111111 US006023085A
United States Patent
[19J
Fang [54]
CORE CELL STRUCTURE AND CORRESPONDING PROCESS FOR NANOTYPE HIGH PERFORMANCE FLASH MEMORY DEVICE Hao Fang, Cupertino, Calif.
[75]
Inventor:
[73]
Assignee: Advanced Micro Devices, Inc., Sunnyvale, Calif.
[21]
Appl. No.: 08/993,910
[22]
Filed:
[51] [52]
Int. Cl.7 ................................................... HOlL 29/788 U.S. Cl. .......................... 257/315; 257/314; 257/261; 257/326; 438/266 Field of Search ..................................... 257/315, 314, 257/261, 326; 438/266; 365/185.28
[58]
Dec. 18, 1997
References Cited
[56]
U.S. PATENT DOCUMENTS 4,823,175 4/1989 Fontana .................................. 357/23.5 5,290,725 3/1994 Tanaka et al. ............................ 437/52 5,300,802 4/1994 Komori et al. ......................... 257/316 5,321,287 6/1994 Uemura et al. ......................... 257/316 5,508,957 4/1996 Momodomi et al. .............. 365/185.17 5,574,685 11/1996 Hsu .................................... 365/185.18 5,668,034 9/1997 Sery et al. .............................. 438/266 5,907,171 5/1999 Santin et al. ... ... ... ... ... .... ... ... ... 257/315
[11]
Patent Number:
6,023,085
[45]
Date of Patent:
Feb.8,2000
6-151871
5/1994
Japan ..................................... 257/315
OTHER PUBLICATIONS
"A 4--Mb NAND EEPROM with Tight Programmed V, Distribution", Masaki Momodomi, Tomoharu Tanaka, Yoshihisa Iwata, Yoshiyuki Tanaka, Hideko Oodaira, Yasuo Itoh, Riichiro Shirota, Kazunori Ohuchhi and Fujio Masuoka,IEEE Journal of Solid-State Circuits, vol. 26, No. 4, Apr. 1991.
Primary Examiner-Sheila V. Clark Assistant Examiner---H. D. Tran Attorney, Agent, or Firm-Amin, Eschweiler & Turocy,
LLP [57]
ABSTRACT
A method of forming a NAND-type flash memory device (200) includes forming a stacked gate flash memory structure (346) for one or more flash memory cells in a core region (305) and forming a transistor structure having a first gate oxide (336) and a gate conductor (338) for both a select gate transistor (344) in the core region (305) and a low voltage transistor (342) in a periphery region (328). In addition, a NAND-type flash memory device (200) includes a core region (305) comprising a stacked gate flash memory cell structure (346) and a select gate transistor (344) and a periphery region (328, 332) comprising a low voltage transistor (342) and a high voltage transistor (350), wherein a structure of the select gate transistor (344) and the low voltage transistor (342) are substantially the same.
FOREIGN PATENT DOCUMENTS 6-151784
328'
5/1994
Japan ..................................... 257/315
7 Claims, 10 Drawing Sheets
Case 2:16-cv-01170 Document 1-3 Filed 10/14/16 Page 3 of 19 PageID #: 57
U.S. Patent
Feb.8,2000
6,023,085
Sheet 1 of 10
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13
12
12
11
11
FIGURE 1A (PRIOR ART)
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FIGURE 1C (PRIOR ART)
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FIGURE 18
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Case 2:16-cv-01170 Document 1-3 Filed 10/14/16 Page 4 of 19 PageID #: 58
U.S. Patent
Feb.8,2000
1ao.!. Select TransistorBLN-1
6,023,085
Sheet 2 of 10
24
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BLN-1
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FIGURE 2A
I Sel
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S
Case 2:16-cv-01170 Document 1-3 Filed 10/14/16 Page 5 of 19 PageID #: 59
U.S. Patent
Feb.8,2000
6,023,085
Sheet 3 of 10
Poly2
Poly2
ONO
0
ONO
95A Tunnel oxide
Poly1
s
0
180A Select gate oxide
Poly1
s P-well
P-well
FIGURE 3A
FIGURE 38 0
1so.!. LV gate ox1ae
Poly2
s
D
400A HV gate ox1ae
Poly2
s
P-substrate
FIGURE 3C
P-substrate
FIGURE 3D
BEGINNING OF PROCESS STEPS 100,
CORE MASK AND IMPLANT
102 110
SELECT GATE PRE-CLEAN AND OXIDATION
112
TOX MASK, BOE ETCH AND PR CLEAN TUNNEL OXIDE AND POLY1
120
DEPOSITION
'-!.P~O~LY.:.,:1:....:::M~AS:;;:,:K~A::.;:N~D...:ET~C!.!.HJ--1 2 4 126
CHANNEL STOP IMPLANT AND PR CLEAN
128
ONO DEPOSITION, MASK AND ETCH
132
1 ST GATE PRE-CLEAN AND OXIDATION
134 CHANNEL VT MASK AND IMPLANT 136
GOX MASK, BOE ETCH AND PR CLEAN
138
2ND GATE OXIDE, POLY2 AND W-SILICIDE 2ND GATE MASK AND ETCH SELF-ALIGNED MASK AND ETCH
FIGURE 4
REMAINING PROCESS STEPS
145 146
Case 2:16-cv-01170 Document 1-3 Filed 10/14/16 Page 6 of 19 PageID #: 60
d
103t=;;
t
t
t
t
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t, e 1 0 5
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122
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50
119
= N .... = Ul ~
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Case 2:16-cv-01170 Document 1-3 Filed 10/14/16 Page 7 of 19 PageID #: 61
d • 116' 122
122,--118
122
108 119
FIGURE SE
L_5F
106
FIGURE SF 122
12 106
FIGURE 5G 130
130
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FIGURE SH
106
r:JJ.
•
Case 2:16-cv-01170 Document 1-3 Filed 10/14/16 Page 8 of 19 PageID #: 62
• r:JJ. •
FIGURE 5I
106
104
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106
142
142
Case 2:16-cv-01170 Document 1-3 Filed 10/14/16 Page 9 of 19 PageID #: 63
U.S. Patent
6,023,085
Sheet 7 of 10
Feb.8,2000
ONO, GOX & SAE masks
20; 160A Select Transistor BLN- 1
Contact
BLN
BLN+1
2~---l______ _
KJ -I
1:8i~f r-[~ns/pf-~ :i\r ~_' ) : ' 8
-,_~ore
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I '---+--+.;-+--1-+-.;.....+-+-+-+-1----1-.:.-l--1---11wL4 2021'------+--i-+-+---+-+-,-+----11--+-+-+-+--++-+_JIWL5 ~I
95A Tunne1-i-+--+--<1--1-----1-ioxide cell :
~+-<:
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FIGURE 6A
FIGURE 68
Gox' &
SAE masks
Case 2:16-cv-01170 Document 1-3 Filed 10/14/16 Page 10 of 19 PageID #: 64
U.S. Patent
Feb.8,2000
6,023,085
Sheet 8 of 10
Poly2 95,A. Tunnel oxide
ONO
Poly1
160A
Poly2
Select gate 1----~ oxide
P-well
P-well
FIGURE 7A
FIGURE 78 160.!.
s
400.!.
Poly2
LV gate ox1ae
Poly2
HV gate ox1ae
s P-substrate
P-substrate
FIGURE 7C
FIGURE 7D
BEGINNING OF PROCESS STEPS
302
CORE MASK AND IMPLANT
310
TUNNEL OXIDE AND POLY1 DEPOSITION POLY1 MASK AND ETCH
____ 314 318
CHANNEL STOP IMPLANT AND PR CLEAN
20
ONO DEPOSITION, MASK AND ETCH
23
1ST GATE PRE-CLEAN AND OXIDATION
324 CHANNEL VT MASK AND IMPLANT
326
GOX MASK, BOE ETCH AND PR CLEAN
34
2ND GATE OXIDE, POLY2 AND W-SILICIDE 2ND GATE MASK AND ETCH SELF-ALIGNED MASK AND ETCH
FIGURE 8
REMAINING PROCESS STEPS
(no Poly1 contact)
339 40
Case 2:16-cv-01170 Document 1-3 Filed 10/14/16 Page 11 of 19 PageID #: 65
d
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f
f
f
f
f
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FIGURE 9C
t 308
t
t 316n
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t
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t 316n 308
Case 2:16-cv-01170 Document 1-3 Filed 10/14/16 Page 12 of 19 PageID #: 66
~
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FIGURE 9G 342
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338 337
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FIGURE 9H
308
Case 2:16-cv-01170 Document 1-3 Filed 10/14/16 Page 13 of 19 PageID #: 67 6,023,085
1
2
the row of cells (see, e.g., prior art FIG. lb). In addition, as highlighted above, the drain regions 14a of the respective cells in a vertical column are connected together by a conductive bit line (BL). The channel 15 of the cell 14 5 conducts current between the source 14b and the drain 14a FIELD OF THE INVENTION in accordance with an electric field developed in the channel 15 by the stacked gate structure 14c. The present invention generally relates to integrated cirAccording to conventional operation, the flash memory cuits and, in particular, to a flash memory structure and a cell 14 operates in the following manner. The cell 14 is method of flash memory fabrication wherein a new core cell 10 programmed by applying a relatively high voltage VG (e.g., structure eliminates a stacked gate structure for the select approximately 18 volts) to the control gate 17d and congate transistors while eliminating a core dual oxide manunecting the drain, source and P-well to ground. A resulting facturing step. The elimination of the core dual oxide step high electric field across the tunnel oxide 17a leads to a substantially simplifies the process, eliminates associated phenomena called "Fowler-Nordheim" tunneling. During tunnel oxide reliability concerns and shrinks the size of the 15 this process, electrons in the core cell channel region tunnel select gate transistor by eliminating the need for a polyl through the gate oxide into the floating gate 17b and become contact. trapped in the floating gate 17b since the floating gate 17b BACKGROUND OF THE INVENTION is surrounded by insulators (the interpoly dielectric 17c and the tunnel oxide 17a). As a result of the trapped electrons, Semiconductor devices typically include multiple indi20 the threshold voltage of the cell 14 increases by about 3 to vidual components formed on or within a substrate. Such 5 volts. This change in the threshold voltage ( and thereby the devices often comprise a high density section and a low channel conductance) of the cell 14 created by the trapped density section. For example, as illustrated in prior art FIG. electrons is what causes the cell to be programmed. la, a memory device such as a flash memory 10 comprises To read the memory cell 14, a predetermined voltage VG one or more high density core regions 11 and a low density 25 that is greater than the threshold voltage of an erased cell, peripheral portion 12 on a single substrate 13. The high but less than the threshold voltage of a programmed cell, is density core regions 11 typically consist of at least one MxN applied to the control gate 17d with a voltage applied array of individually addressable, substantially identical between the source 14b and the drain 14a. If the cell 14 floating-gate type memory cells and the low density peripheral portion 12 typically includes input/output (1/0) circuitry 30 conducts, then the cell 14 has not been programmed (the cell 14 is therefore at a first logic state, e.g., a zero "O"). and circuitry for selectively addressing the individual cells Likewise, if the cell 14 does not conduct, then the cell 14 has (such as decoders for connecting the source, gate and drain been programmed (the cell 14 is therefore at a second logic of selected cells to predetermined voltages or impedances to state, e.g., a one "1"). Consequently, one can read each cell effect designated operations of the cell such as 14 to determine whether it has been programmed (and programming, reading or erasing). 35 therefore identify its logic state). The memory cells within the core portion 11 are coupled In order to erase the flash memory cell 14, a relatively together in a NAND-type circuit configuration, such as, for high voltage Vg (e.g., approximately 20 volts) is applied to example, the configuration illustrated in prior art FIG. lb. the P-well 16 and the control gate 17d is held at a ground Each memory cell 14 has a drain 14a, a source 14b and a stacked gate 14c. A plurality of memory cells 14 connected 40 potential (V =0), while the drain 14a and the source 14b are allowed to float. Under these conditions, a strong electric together in series with a drain select transistor at one end and field is developed across the tunnel oxide 17a between the a source select transistor at the other end to form a NAND floating gate 17b and the P-well 16. The electrons that are string as illustrated in prior art FIG. lb. Each stacked gate trapped in the floating gate 17b flow toward and cluster at 14c is coupled to a word line (WLO, WLl, ... , WLn) while each drain of the drain select transistors are coupled to a bit 45 the portion of the floating gate 17b overlying the source region 14b and are extracted from the floating gate 17b and line (BLO, BLl, . .. , BLn). Lastly, each source of the source into the source region 14b by way of Fowler-Nordheim select transistors are coupled to a common source line Vss. tunneling through the tunnel oxide 17a. Consequently, as the Using peripheral decoder and control circuitry, each electrons are removed from the floating gate 17b, the cell 14 memory cell 14 can be addressed for programming, reading is erased. or erasing functions. 50 There is a strong need in the art for a flash memory device Prior art FIG. le represents a fragmentary cross section structure and process for manufacture that improves the diagram of a typical memory cell 14 in the core region 11 of performance and reliability of the device while simplifying prior art FIGS. la and lb. Such a cell 14 typically includes its method of manufacture. the source 14b, the drain 14a and a channel 15 in a substrate or P-well 16; and the stacked gate structure 14c overlying 55 SUMMARY OF THE INVENTION the channel 15. The stacked gate 14c further includes a thin The present invention relates to flash memory device gate dielectric layer 17a (commonly referred to as the tunnel oxide) formed on the surface of the P-well 16. The stacked structure and a method for its manufacture. In a core portion of a NAND-type flash memory cell, a select gate transistor gate 14c also includes a polysilicon floating gate 17b which overlies the tunnel oxide 17a and an interpoly dielectric 60 structure has a structure like that of the periphery low layer 17c overlies the floating gate 17b. The interpoly voltage transistor and is fabricated using essentially the dielectric layer 17c is often a multilayer insulator such as an same steps as those used in fabricating the periphery low oxide-nitride-oxide (ONO) layer having two oxide layers voltage transistor. The select gate transistor structure allows sandwiching a nitride layer. Lastly, a polysilicon control gate the device to be easily fabricated by eliminating the dual 17d overlies the interpoly dielectric layer 17c. The control 65 core oxide formation process. Elimination of the dual core gates 17d of the respective cells 14 that are formed in a oxide process steps reduces the number of process steps and lateral row share a common word line (WL) associated with prevents a source of potential contamination prior to the CORE CELL STRUCTURE AND CORRESPONDING PROCESS FOR NANOTYPE HIGH PERFORMANCE FLASH MEMORY DEVICE
0
Case 2:16-cv-01170 Document 1-3 Filed 10/14/16 Page 14 of 19 PageID #: 68 6,023,085 3
4
FIG. 8 is a flow chart diagram illustrating a semiconductor formation of the core tunnel oxide, thereby improving the reliability of the device. manufacturing process flow for forming the NAND-type flash memory device of FIGS. 6a and 6b according to the According to another aspect of the present invention, the present invention; and formation of a select gate transistor structure like that of the periphery low voltage transistor eliminates the stacked gate 5 FIGS. 9a-9h are cross section diagrams illustrating the structure for the select gate transistors and the need for a various steps in the manufacturing process of FIG. 8 accordpolyl contact to short out the polyl and poly2 layers, ing to the present invention. thereby advantageously reducing the die area In addition, DETAILED DESCRIPTION OF THE eliminating the stacked gate structure for the select gate INVENTION transistor allows for a channel stop implant to be performed 10 in the select gate transistor region, thereby improving the bit The present invention will now be described with referline isolation and decreasing the potential for bit line to bit ence to the drawings wherein like reference numerals are line punch through. used to refer to like elements throughout. The present To the accomplishment of the foregoing and related ends, invention relates to a flash memory device and a method for the invention comprises the features hereinafter fully 15 its manufacture that, according to one aspect of the present invention, eliminates the dual core oxide processing steps by described and particularly pointed out in the claims. The replacing the stacked gate transistor structure with a tranfollowing description and the annexed drawings set forth in sistor structure that resembles a conventional periphery low detail certain illustrative embodiments of the invention. These embodiments are indicative, however, of but a few of voltage transistor. Consequently, the steps used in forming the various ways in which the principles of the invention 20 the periphery low voltage transistors may be used to conmay be employed. Other objects, advantages and novel struct the core select gate transistors, thereby substantially features of the invention will become apparent from the reducing the number of processing steps needed to construct following detailed description of the invention when conthe flash memory device. sidered in conjunction with the drawings. According to another aspect of the present invention, 25 elimination of the dual core oxide processing steps advanBRIEF DESCRIPTION OF THE DRAWINGS tageously improves the manufacturability of the process by eliminating a source of potential tunnel oxide contamination FIG. la is a plan view illustrating a prior art layout of a and thereby improving the tunnel oxide integrity in the core flash memory chip; FIG. lb is a schematic diagram illustrating a prior art 30 flash memory cell region. The present invention also provides for a reduction in the size of the core portion of the NAND-type flash memory circuit configuration; device since the new select gate transistor structure is not a FIG. le is a fragmentary cross section illustrating a prior stacked gate structure. Consequently, a polyl contact is not art stacked gate flash memory cell; required to short out the polyl and poly2 layers. Eliminating FIG. 2a is a schematic diagram illustrating a core portion the polyl contact reduces the size of each select gate 35 of a NAND-type flash memory device; transistor. Eliminating the need for a polyl contact also FIG. 2b is a plan layout view of the core portion of the allows for the elimination of subsequent processing needed NAND-type flash memory device of FIG. 2a; to create the polyl contact. FIG. 3a is a cross section of a stacked gate flash memory According to yet another aspect of the present invention, cell; 40 elimination of the stacked gate structure for the select gate FIG. 3b is a cross section of a select gate transistor having transistors in the core region allows for a channel stop a stacked gate structure, wherein the polyl and poly2 layers implant to be performed in the select gate transistor regions are shorted together; which improves bit line isolation and substantially reduces FIG. 3c is a cross section of a periphery low voltage the potential for bit line to bit line punch through, thereby transistor; improving the reliability of the flash memory device. 45 FIG. 3d is a cross section of a periphery high voltage The present invention may best be understood and its transistor;. advantages appreciated in conjunction with the core structure and process of FIGS. 2a-5k. A circuit schematic diaFIG. 4 is a flow chart diagram illustrating a semiconductor gram illustrating a core portion 11 of a NAND-type flash manufacturing process flow for forming the NAND-type 50 memory device is illustrated in FIG. 2a. The core portion 11 flash memory device of FIGS. 2a and 2b; includes a memory cell region 22 which is bounded on one FIGS. 5a-5l are cross section diagrams illustrating the side by a drain select transistor portion 24 and bounded on various steps in the manufacturing process of FIG. 4; another side by a source select transistor portion 26. Each of FIG. 6a is a schematic diagram illustrating a core portion the select transistor portions 24 and 26 contain select gate of a NAND-type flash memory device according to the 55 transistors 24a-24c and 26a-26c, respectively, which operpresent invention; ate to selectively activate a desired bit line (e.g.,BLN-1, FIG. 6b is a plan layout view of the NAND-type flash BLN, BLN+l) by ensuring the selectivity of each bit line memory device of FIG. 6a according to the present invenand preventing the cell current from conducting current tion; through the bit line during a programming operation as is FIG. 7a is a cross section of a stacked gate flash memory 60 well known by those skilled in the art. cell in the core region according to the present invention; In the NAND-type flash memory process which forms the FIG. 7b is a cross section of a select gate transistor in the core circuit 12 of FIG. 2a and its corresponding circuit core region according to the present invention; layout (of which FIG. 2b is a plan view), a dual core cell FIG. 7c is a cross section of a periphery low voltage oxide process is used to form the memory cell oxides and the transistor according to the present invention; 65 select gate transistor oxides, respectively (since the memory FIG. 7d is a cross section of a periphery high voltage cell oxides and select gate transistor oxides have different transistor according to the present invention; thicknesses). In addition, a dual periphery gate oxide process
Case 2:16-cv-01170 Document 1-3 Filed 10/14/16 Page 15 of 19 PageID #: 69 6,023,085 5
6
the surface of the device at step 110, as illustrated in FIG. Sb. for formation of the high and low voltage transistors in the A tunnel oxide mask (TOX) (not shown) is then formed at periphery region 14 (see, e.g., FIG. 1) is also utilized. The process further includes a double polysilicon layer formation step 112 to define an area 114 within the core region 105 in which the tunnel oxide for the core memory cells will be layer to generate the stacked gate structures in the core 5 formed. An etch step follows to remove the oxide layer 108 region 12. in the region 114 exposed by the TOX mask but not in the The core select gate transistors 24a-24c and 26a-26c are peripheral regions 116 and 118, respectively, as illustrated in similar in structure to the stacked gate flash memory strucFIG. Sc. Step 112 continues with a photoresist clean to tures in the memory cell region 22 except that their gate remove the TOX mask. oxide is approximately twice as thick as the cell oxide (also called the tunnel oxide) in the stacked gate structure of the 10 Once the cleaning is complete, a tunnel oxide 119 having a thickness of about 95 A is grown in the region 114 at step memory cell (about 180 A compared to about 95 A.). The select transistors 24a-24c utilize a gate oxide of 180 A to 120. At the same time, the second oxidation step causes the improve the reliability of the transistors by reducing the oxide layer 108 to increase to about 180 A. Therefore steps vulnerability of the devices to band to band tunneling 110, 112 and 120 constitute the core dual oxide processing induced hot carrier stress during programming. The select 15 steps to form a memory cell tunnel oxide of about 95 A and gate transistors 24a-24c and 26a-26c further differ from the a select gate transistor gate oxide of about 180 A in the core stacked gate flash memory cell structures of the region 22 region 105. because they operate as conventional MOS transistors and Step 120 also includes the deposition of a first polysilicon therefore have the first and second polysilicon layers shorted layer 122 over the surface of the device, as illustrated in FIG. together to simulate a standard MOS transistor configura- 20 5d. The polysilicon layer 122 is then covered with a photion. A plan circuit layout view of the conventional NANDtoresist mask (not shown) at step 124 and etched to define a type circuit arrangement 12 is illustrated in FIG. 2b. plurality of polyl regions in the core region 105, wherein the The dual core oxides (the tunnel oxide and the select gate regions comprise the floating gates for stacked gate flash oxide) are created by growing a first gate oxide of approximemory cells and the first polysilicon layer for the source mately 140 A and then using a mask to open a space for 25 select transistor and drain select transistor, respectively, as etching to thereby define a tunnel oxide region. Subsequent illustrated in FIG. Se. Note that in step 124, the polysilicon the etching, -another oxide is grown to form the tunnel oxide layer 122 is not etched between bit lines in the select gate of about 95 A in the previously etched region while the transistor regions 24 and 26, as illustrated in FIG. 2b. Since unetched select gate oxide region continues to grow to a FIG. Se transversely cuts across the word lines, this lack of 30 poly etching between the bit lines is not visible. thickness of about 180 A. Consequently, FIGS. 5/ and 5g are provided which are cross Similarly, the dual periphery gate oxides are later formed sections of the core region 105 taken along dotted lines in a dual oxide process that includes growing an initial gate 5/-5/ and 5g-5g in FIG. Se, respectively. oxide of about 285 A and then using a mask to define for Note that in select gate transistor regions of FIG. 5g, the etching a thin low voltage transistor gate oxide region. 35 Subsequent the etching, another oxide is grown to generate poly region 122 is not etched between the bit lines 125 since a 160 A low voltage transistor oxide in the previously etched this polyl layer 122 is later used as an interconnect to short region while the unetched high voltage transistor oxide out the polyl and poly2 layers (see also FIG. 3b). region continues to grow to a thickness of about 400 A. A channel stop implant followed by a photoresist clean is In the above process, the first polysilicon layer (polyl) is 40 then performed at step 126 to form an isolation implant used as the floating gate region for the core memory cells doping region 129 under the field oxide 127. The channel and the second polysilicon layer (poly2) is used for both the stop implant serves to isolate the bit lines from one another in the memory cell region 22 of FIG. 2a in regions where the core memory cell control gates and the gate regions for the periphery transistors (both high and low voltage). polyl layer 122 was etched (that is, over the field oxide Consequently, the NAND-type process involves the fabri- 45 regions which are not shown). This channel stop implant, cation of four types of devices, as illustrated in FIGS. 3a-3d, however, is not performed in the select gate regions 24 and wherein FIG. 3a is a cross section of a stacked gate memory 26 of FIG. 2a, because the polyl layer 122 is not etched cell in the core memory cell region 22, FIG. 3b is a cross away, as illustrated in FIG. 5g. Consequently, the polyl layer 122 shields the field oxide regions 127 from the channel stop section of a select gate transistor in the select gate regions 24 and 26 (wherein the polyl and poly2 layers are shorted 50 implant which results in poor bit line to bit line isolation in together), FIG. 3c is a cross section of a periphery low the select gate transistor regions 24 and 26. voltage transistor and FIG. 3d is a cross section of a The process 100 continues at step 128 wherein an interperiphery high voltage transistor. poly dielectric layer 130 is formed over the surface of the A semiconductor manufacturing process flow illustrating device and patterned to overlie the first polysilicon regions the NAND-type flash memory device process 100 is illus- 55 122, as illustrated in FIG. Sh. The interpoly dielectric layer 130 often consists of an ONO layer which is an oxide/ trated in FIG. 4 and will be discussed in detail in conjunction with FIGS. 5a-5l. The process 100 begins with a core mask nitride/oxide layer formed via conventional processing techand core Vt (threshold voltage) implant step 102 wherein a niques as is well known by those skilled in the art. photoresist mask 103 is formed and patterned over a P-well Following the ONO deposition and patterning at step 128, which resides in an N-well which resides in a P-substrate 60 a pre-oxidation clean-up step is conducted followed by 104 to define an opening over a core region 105. The core another oxidation of about 285 A across the surface of the region 105 is then subjected to a P-type impurity dopant via, device at step 132. A channel threshold voltage mask is then for example, ion implantation to thereby form a highly formed at step 134 followed by an implant to adjust the doped channel region 106 in the P-well of the core region threshold voltage at step 134. The peripheral gate oxide 105, as illustrated in FIG. Sa. 65 mask (GOX)(not shown) is then formed at step 136 which The photoresist mask 103 is then removed, a select gate defines the opening for the thin gate oxide area of the low pre-clean is performed and an oxide layer 108 is formed over voltage peripheral transistor in the low voltage peripheral
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region 116. Step 136 includes the etching away of the oxide equals twenty (20) volts during programming which limits layer in the region 116 but not in the core region 105 since the memory device to operating at lower programming the oxide does not grow appreciably on the ONO layer, voltages, thereby resulting in a slower memory device. Furthermore, since the select gate structures require that the thereby leaving an intermediate oxide layer 137 remaining in the high voltage peripheral region 118, as illustrated in 5 polyl and poly2 layers be shorted together, a special polyl FIG. Si. The etching is then followed by a photoresist clean contact process is later required to effectuate that short to remove the GOX mask. circuit. Lastly, the polyl contact increases the size of each select gate transistor which adversely affects the die size of Once the GOX mask is removed, another oxidation step the flash memory device. takes place at step 138, wherein a thin gate oxide 140 of A circuit schematic of a NAND-type flash memory device about 160 A is formed in the low voltage peripheral region 10 and a corresponding plan view layout diagram according to 116 and a thick gate oxide 142 of about 400 A continues to one embodiment of the present invention is illustrated in grow (from the intermediate oxide layer 137) in the high FIGS. 6a and 6b, respectively. A core portion 200 of the flash voltage peripheral region 118, as illustrated in FIG. 5j. memory device includes a core memory cell portion 202 Therefore steps 136 and 138 constitute the periphery dual oxide processing steps to form the periphery low voltage and 15 which is similar to the memory cell portion 22 of FIG. 2a. The core memory cell portion 202 is bounded on one side by high voltage transistor oxides, respectively. Step 138 also a drain select gate transistor region 204 and on another side includes the deposition of a second polysilicon layer and a by a source select gate transistor region 206. The select gate tungsten silicide layer which is collectively illustrated as a transistor regions 204 and 206 differ from the select gate layer 144 in FIG. 5j. The process 100 continues at step 145, wherein a photo- 20 transistors 24 and 26 in that the select gate transistors within the regions 204 and 206 of the present invention are not resist mask (not shown) is formed and patterned with stacked gate structures (which required the shorting of the openings to define the low and high voltage periphery polyl and poly2 layers). Furthermore, since the select gate transistors in the periphery regions 116 and 118, transistor regions 204 and 206 are not stacked gate respectively, and the control gates for the stacked gate structures in the core region 105, as illustrated in FIG. 5k. 25 structures, but instead are like the periphery, low voltage transistors, the core dual oxide fabrication steps required to The process 100 is then completed at step 146 (at least with form the stacked gate structures of FIGS. 3a and 3b having respect to the formation of the four separate transistor differing oxide thicknesses is eliminated, thereby simplifystructures illustrated in FIGS. 3a-3d. Step 146 includes the ing the semiconductor processing. formation of a self-aligned mask (not shown) which defines In a preferred embodiment of the present invention, the openings in the core region 105 and the etching of the 30 poly2/silicide layer used to form the gate regions of the interpoly dielectric layer 130 and first polysilicon layer 122, periphery high and low voltage transistors is used to replace respectively, as illustrated in FIG. 51. The step 146 thereby the polyl/ONO/poly2 stacked gate structure of FIG. 3b for results in a low voltage peri1;heral transistor 150 having a the core select source and select drain transistors in the gate oxide 152 of about 160 A and a poly2 gate region 154, and a high voltage peripheral transistor 160 having a gate 35 regions 204 and 206. Therefore the process steps and masks used to form the periphery low voltage transistors may also oxide 162 of about 400 A and poly2 gate 164. The etching be used to form the core select gate transistors. Therefore, of step 146 further defines the stacked gate structures that instead of the process resulting in four transistor structures form the select gate transistors and the stacked gate/memory requiring two separate dual oxide fabrication process steps, cells, respectively. The select gate transistors 170 (the select source and select drain transistors) each have a select gate 40 only three transistor structures are fabricated, as illustrated in FIGS. 7a-7d (since the structures of FIG. 7b and 7c are oxide layer 108 of about 180 A, a polyl layer 122a and 122d, substantially the same), thereby eliminating one set of dual and an interpoly dielectric or ONO layer 130 and the poly2 oxide processing steps in forming the thin core tunnel oxide layer 144. At a later stage in the process, the polyl 122a and and substantially eliminating sensitive tunnel oxide con122d and poly two 144 are shorted together to achieve the select gate transistors as illustrated in FIG. 3b. The remain- 45 tamination associated with the core dual oxide process. ing stacked gate/memory cells 180 each have a tunnel oxide The structural differences between the present invention layer of about 95 A, a floating gate layer 122, an interpoly and other structures may further be seen in a comparison of dielectric or ONO layer 130 and a control gate layer 144. the plan layout view of the present invention of FIG. 6b with FIG. 2b. Note that in FIG. 6b, the first layer of polysilicon The fabrication process discussed above in conjunction with FIGS. 2a-5l has several advantageous features, 50 (polyl) is etched between the bit lines (BLN-1, BLN, BLN+l) in both the core memory region 202 and the select however, the process may be improved. First, the dual core gate transistor regions 204 and 206. In addition, the ONO oxide steps needed to produce the memory cells and select and GOX masks (which will be described in greater detail gate transistors having different oxide thicknesses in the core supra) effectively prohibit ONO deposition and double oxide region is somewhat complicated and requires an additional mask, mainly the TOX mask discussed above, as well as the 55 layer formation in the select gate transistor regions 204 and 206, thereby resulting in select gate transistors having poly2 associated resist clean and oxide regrowth steps. In addition, as the gate material, as illustrated in FIG. 7b. Conversely, in poor tunnel oxide integrity may arise due to contamination FIG. 2b, the etching of the polyl does not extend through the during the TOX masking steps since a conventional HF dip select gate transistor regions 24 and 26, thereby resulting in can not be used to remove residual oxide. Furthermore, a channel stop implant can not be performed in the select gate 60 double poly, stacked gate structures, as illustrated in FIG. 3b. In addition to the above advantages, the removal of the transistor regions after the polyl etch step as discussed polyl layer between the bit lines in the select gate transistor above since the polyl is used as an interconnect layer to short out the polyl and poly2. The lack of a channel stop regions 204 and 206 allows the regions 204 and 206 to receive a channel stop implant which results in significantly implant in the select gate transistor areas may result in bit line to bit line punch through. In addition, the spacing region 65 improved bit line isolation and word line field turn-on. The substantial improvement in bit isolation allows for higher between the first word line (WLl) and the select drain transistors 24a-24c of FIG. 2b may turn on when WLl programming voltages which provide for higher speed pro-
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gramming functionality and the potential for use of the regions 316a and 316b, respectively, as illustrated in FIG. 9e. The interpoly dielectric lay consists of an ONO layer structure in multi-level NAND-type devices. In addition to which is an oxide/nitride/oxide layer formed via conventhe above features, the poly2 gate region, which may be tional processing techniques as is well known by those composed of a poly/tungsten silicide combination, may be used as an interconnect for the select gate transistors, 5 skilled in the art. Note that in FIG. 9e the patterning of the interpoly dielectric layer 322 etches away the layer 322 and thereby further improving their performance. the first polysilicon layer 312 in the periphery areas as well In the preferred embodiment of the present invention, the as in the select transistor areas within the core region 305. semiconductor processing steps used to form the periphery, Following the ONO deposition and patterning at step 320, low voltage transistor structures are also used to form the a pre-oxidation clean-up step is conducted followed by the 10 core select gate transistors, thereby making the structures formation of an oxide layer across the surface of the device substantially the same. A method of forming a NAND type at step 323. A channel threshold voltage mask is then formed flash memory device according to the preferred embodiment (not shown) followed by an implant to adjust the threshold of the present invention will now be described in conjuncvoltage for the periphery devices at step 324. A peripheral tion with a semiconductor manufacturing flow chart in FIG. 15 gate oxide mask (GOX)(not shown) is then formed at step 8 and FIGS. 9a-9h. 326 which defines an opening for the thin gate oxide area for The process 300 begins with a core mask and implant step the low voltage peripheral transistor in the low voltage 302 wherein a photoresist mask 303 is formed and patterned peripheral region 320 and the gate oxide for the select gate over a P-well which resides in an N-well in the P-substrate transistors in the core region 305. Step 326 includes the 304 to define an opening over a core region 305. The core etching away of the oxide layer in the region 328 as well as 20 region 305 is then subjected to a P-type impurity dopant via, in the select transistor areas within the core region 305 using for example, ion implantation to thereby form a highly the GOX mask as shown in FIG. 6b, thereby leaving an doped channel region 306 in the P-well of the core region intermediate oxide layer 330 remaining in the high voltage 305, as illustrated in FIG. 9a. peripheral region 332, as illustrated in FIG. 9e. The etching The photoresist mask 303 is then removed and a tunnel 25 is then followed by a photoresist clean to remove the GOX oxide 308 having a thickness of about 95 A is grown over mask. the surface of the device at step 310. The oxide layer is Once the GOX mask is removed, another oxidation step grown, for example, in a dry oxidation furnace. takes place at step 334, wherein a thin gate oxide 336 of Step 310 also includes the deposition of a first polysilicon about 160 A is formed in the low voltage peripheral region layer 312 over the surface of the device, as illustrated in FIG. 30 328 and the core region 305 to form the gate oxide for the 9b. The polysilicon layer 312 is then covered with a phoselect gate transistors while a thick gate oxide 337 of about toresist mask 315 at step 314 and etched to define a plurality 400 A continues to grow (from the intermediate oxide layer of polyl regions 316a and 316b, wherein the regions 316a 330) in the high voltage peripheral region 332, as illustrated and 316b comprise the floating gates for the stacked gate in FIG. 9f Therefore steps 326 and 334 constitute the flash memory cells and select transistors in the core region 35 periphery dual oxide processing steps to form the periphery 305, as illustrated in FIG. 9c. low voltage and select gate transistor oxides and the high A channel stop implant is then performed at step 318. voltage transistor oxides, respectively. Step 324 also Since the cross section diagram of FIG. 9c is oriented to cut includes the deposition of a second polysilicon layer and a transversely across the word lines, the channel stop implant tungsten silicide layer which is collectively illustrated as a (which helps isolate the bit lines) is not illustrated in the 40 layer 338 in FIG. 9f Figure. FIG. 9d, however, illustrates the core portion 305 of The process 300 then continues at step 339, wherein a FIG. 9c taken along dotted line 9d-9d so that the cross photoresist mask (not shown) is formed and patterned with section transversely cuts across the bit lines. FIG. 9d illusopenings to define the low and high voltage periphery trates how the absence of polyl between the bit lines in the transistors in the periphery regions 328 and 332, select gate transistor regions allows the channel stop implant 45 respectively, the select gate transistors and the control gate in the region 319 to be formed. structures for the stacked gate devices in the core region 305, The channel stop implant uses the polyl etch photomask as illustrated in FIG. 9g. The process 300 is then completed 315 of step 314 to define the regions 319 that receive the at step 340 ( at least with respect to the formation of the three implant, as illustrated in FIG. 9d. Step 318 then concludes separate transistor structures illustrated in FIGS. 7a-7d. Step with a photoresist clean step to remove the photomask 315 50 340 includes the formation of a self-aligned mask (not which was used for the polyl etch and the channel stop shown) and the etching of selective portions of the interpoly implant. dielectric layer 322 and the first polysilicon layers 316a and The present invention provides an improvement to the 316b, as illustrated in FIG. 9h. During the self-aligned etch above described structure and method since the polyl layer process, the select transistor areas are covered by the SAE between the bit lines (BLN-1, BLN, BLN+l) is etched away 55 mask to avoid potential polysilicon gouging in the region. in the select gate regions 204 and 206, as illustrated in FIG. The step 339 thereby results in a low voltage peripheral transistor 342 and select gate transistors 344 having a gate 6b. Etching away the polysilicon between the bit lines in the regions 204 and 206 allows the channel stop implant to be oxide 336 of about 160 A and a poly2 gate region 338, and performed in the regions 204 and 206, which thereby a high voltage peripheral transistor 350 having a gate oxide decreases the potential for bit line to bit line punch through 60 337 of about 400 A and a poly2 gate 338. The etching of step 340 defines the stacked gate structures using the layer 338 as or leakage in the select gate regions 204 and 206, respeca self-aligned mask that form the stacked gate/memory cells tively. The channel stop implant region 319 of step 318 provides good bit line to bit line isolation which allows the 346, respectively. device to operate at a wider range of program voltages. Although the invention has been shown and described The process 300 continues at step 320 wherein an inter- 65 with respect to a certain preferred embodiment or embodiments, it is obvious that equivalent alterations and poly dielectric layer 322 is formed over the surface of the device and patterned to overlie the polyl floating gate modifications will occur to others skilled in the art upon the
Case 2:16-cv-01170 Document 1-3 Filed 10/14/16 Page 18 of 19 PageID #: 72 6,023,085 11 reading and understanding of this specification and the annexed drawings. In particular regard to the various functions performed by the above described components ( assemblies, devices, circuits, etc.), the terms (including a reference to a "means") used to describe such components 5 are intended to correspond, unless otherwise indicated, to any component which performs the specified function of the described component (i.e., that is functionally equivalent), even though not structurally equivalent to the disclosed structure which performs the function in the herein illus- 10 trated exemplary embodiments of the invention. In addition, while a particular feature of the invention may have been disclosed with respect to only one of several embodiments, such feature may be combined with one or more other features of the other embodiments as may be desired and 15 advantageous for any given or particular application. What is claimed is: 1. ANAND-type flash memory device, comprising: a core region comprising a stacked gate flash memory cell 20 structure and a select gate transistor; and a periphery region comprising a low voltage transistor and a high voltage transistor, wherein the select gate transistor and the low voltage transistor both have a gate oxide layer and a gate electrode layer, 25 wherein a thickness of the gate oxide layer of the select gate transistor and the low voltage transistor are substantially the same, and a thickness of the gate electrode layer of the select gate transistor and the low voltage transistor are substantially the same. 30 2. The NAND-type flash memory device of claim 1, wherein the gate oxide layer is about 160 A 3. The NAND-type flash memory device of claim 1, wherein the stacked gate flash memory cell comprises: a tunnel oxide layer; 35 a floating gate layer overlying the tunnel oxide layer;
12 an insulating layer overlying the floating gate layer; and a control gate layer overlying the insulating layer. 4. The NAND-type flash memory device of claim 1, wherein the high voltage transistor has a structure comprising a gate oxide layer of about 400 A and a conductive gate region overlying the gate oxide layer. 5. The NAND-type flash memory device of claim 1, wherein the select gate transistor has a channel stop implant region. 6. The NAND-type flash memory device of claim 1, further comprising a plurality of select gate transistors, wherein the plurality of select gate transistors share a common conductive gate region to thereby form a select gate word line. 7. ANAND-type flash memory device, comprising: a core region comprising a stacked gate flash memory cell structure having a thin oxide material forming a tunnel oxide layer, a first conductive material forming a polyl layer overlying the tunnel oxide layer, an insulating material forming an insulating layer overlying the polyl layer and a second conductive material forming a poly2 layer overlying the insulating layer; the core region further comprising a select gate transistor having a gate oxide material forming a gate oxide layer and the second conductive material forming a gate layer overlying the gate oxide layer; and a periphery region including a low voltage transistor and a high voltage transistor, wherein the same gate oxide formation step used to form the gate oxide layer of the select gate transistor also forms a gate oxide laver of the low voltage transistor and thus a thickness of the gate oxide layers of the select gate transistor and the low voltage transistor are substantially the same.
* * * * *
Case 2:16-cv-01170 Document 1-3 Filed 10/14/16 Page 19 of 19 PageID #: 73 UNITED STATES PATENT AND TRADEMARK OFFICE CERTIFICATE OF CORRECTION PATENT NO.:
6,023,085
DATED:
February 8, 2000
INVENTOR(S):
Hao Fang
It is certified that error appears in the above-identified patent and that said Letters Patent is hereby corrected as shown below:
Column 2, Line 38, please replace "Vg" with--V 5--. Column 5, Line 27, please delete the dash(-) prior to the word "another". Column 7, Line 41, please replace "A" with
--A--.
Column I 0, Line 2, please delete the word "lay" and insert the phrase --layer 320 often--. Column 12, Line 5, please replace "A" with --A--.
Signed and Sealed this Tenth Day of October, 2000 Attest:
Q. TODD DICKINSON
Attesting Officer
Director of Parents and Trademarks
Case 2:16-cv-01170 Document 1-4 Filed 10/14/16 Page 1 of 8 PageID #: 74
EXHIBIT C
Case 2:16-cv-01170 Document 1-4 Filed 10/14/16 8 PageID #: 75 IIIIII IIIIIIII Ill lllll lllllPage lllll lllll2llllloflllll lllll lllll 111111111111111111 US006388330Bl
(12)
United States Patent
(10)
Ngo et al.
(45)
LOW DIELECTRIC CONSTANT ETCH STOP LAYERS IN INTEGRATED CIRCUIT INTERCONNECTS
(54)
Inventors: Minh Van Ngo, Fremont; Dawn M. Hopper, San Jose; Robert A. Huertas, Hollister; Terri J. Kitson, San Jose, all of CA(US)
(75)
(73)
( *)
Assignee: Advanced Micro Devices, Inc., Sunnyvale, CA (US) Notice:
Subject to any disclaimer, the term of this patent is extended or adjusted under 35 U.S.C. 154(b) by O days.
(21)
Appl. No.: 09/776,012
(22)
Filed:
(51) (52)
Int. Cl.7 .......................... HOlL 23/48; HOlL 23/52 U.S. Cl. ....................... 257/760; 257/758; 257/759; 257/762; 257/765 Field of Search ................................. 438/622-624, 438/629, 631, 633, 634, 637-640, 672, 675, 687, 688, 692, 783, 791; 257/758-760, 762,765
(58)
Feb. 1, 2001
Patent No.: Date of Patent:
US 6,388,330 Bl May 14, 2002
References Cited
(56)
U.S. PATENT DOCUMENTS 6,071,809 A 6,168,726 Bl 6,245,662 Bl
* 6/2000 Zhao .......................... 438/634 * 1/2001 Li et al. ....................... 216/79 * 6/2001 Naik et al. .................. 438/622
FOREIGN PATENT DOCUMENTS WO
WO 99/33102
* 7/1999
* cited by examiner Primary Examiner-Ha Tran Nguyen (74) Attorney, Agent, or Firm---Mikio Ishimaru (57)
ABSTRACT
An integrated circuit and method of manufacture therefore is provided having a semiconductor substrate with a semiconductor device with a dielectric layer over the semiconductor substrate. A conductor core fills the opening in the dielectric layer. An etch stop layer with a dielectric constant below 5.5 is formed over the first dielectric layer and conductor core. A second dielectric layer over the etch stop layer has an opening provided to the conductor core. A second conductor core fills the second opening and is connected to the first conductor core.
10 Claims, 2 Drawing Sheets
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on the adhesion layer to line the adhesion layer in the first channel openings. The refractory metals are good barrier materials, have lower electrical resistance than their nitrides, and have good adhesion to copper. TECHNICAL FIELD 5 In some cases, the barrier material has sufficient adhesion to the dielectric material that the adhesion layer is not The present invention relates generally to semiconductor technology and more specifically to etch stop layers m required, and in other cases, the adhesion and barrier mateintegrated circuits. rial become integral. The adhesion and barrier layers are often collectively referred to as a "barrier" layer herein. BACKGROUND ART 10 For conductor materials such as copper, which are deposIn the manufacture of integrated circuits, after the indiited by electroplating, a seed layer is deposited on the barrier vidual devices such as the transistors have been fabricated in layer and lines the barrier layer in the first channel openings and on the semiconductor substrate, they must be connected to act as an electrode for the electroplating process. Protogether to perform the desired circuit functions. This intercesses such as electroless, physical vapor, and chemical connection process is generally called "metalization" and is 15 vapor deposition are used to deposit the seed layer. performed using a number of different photolithographic, A first conductor material is deposited on the seed layer deposition, and removal techniques. and fills the first channel opening. The first conductor Briefly, individual semiconductor devices are formed in material and the seed layer generally become integral, and and on a semiconductor substrate and a device dielectric are often collectively referred to as the conductor core when 20 layer is deposited. Various techniques are used to form gate discussing the main current-carrying portion of the channels. and source/drain contacts, which extend up to the surface of A chemical-mechanical polishing (CMP) process is then the device dielectric layer. In a process called the "damaused to remove the first conductor material, the seed layer, scene" technique, dielectric layers are deposited over the and the barrier layer above the first channel dielectric layer device dielectric layers and openings are formed in the 25 to form the first channels. When a layer is placed over the dielectric layers. Conductor materials are deposited on the first channels as a final layer, it is called a "capping" layer dielectric layers and in the openings. A process is used to and a "single" damascene process is completed. When the planarize the conductor materials with the surface of the layer is processed further for placement of additional chandielectric layers so as to cause the conductor materials to be nels over it, the layer is a via stop layer. "inlaid" in the dielectric layers. For more complex integrated circuits, a "dual damascene" 30 More specifically, for a single layer of interconnections a technique is used in which channels of conductor materials "single damascene" technique is used in which the first are separated by interlayer dielectric layers in vertically channel formation of the single damascene process starts separated planes and interconnected by vertical connections, with the deposition of a thin first channel stop layer over the or "vias". device dielectric layer. The first channel stop layer is an etch 35 More specifically, the dual damascene process starts with stop layer which is subject to a photolithographic processing the deposition of a thin etch stop layer, or the via stop layer, step which involves deposition, patterning, exposure, and over the first channels and the first channel dielectric layer. development of a photoresist, and an anisotropic etching A via dielectric layer is deposited on the via stop layer. step through the patterned photoresist to provide openings to Again, where the via dielectric layer is of an oxide material, the device contacts. The photoresist is then stripped. A first 40 such as silicon oxide, the via stop layer is a nitride, such as channel dielectric layer is formed on the first channel stop silicon nitride, so the two layers can be selectively etched. layer. Where the first channel dielectric layer is of an oxide Second channel stop and second channel dielectric layers material, such as silicon oxide (Si0 2 ), the first channel stop are formed on the via dielectric layer. Again, where the layer is a nitride, such as silicon nitride (SiN), so the two second channel dielectric layer is of an oxide material, such layers can be selectively etched. 45 as silicon oxide, the second channel stop layer is a nitride, The first channel dielectric layer is then subject to further such as silicon nitride, so the two layers can be selectively photolithographic process and etching steps to form first etched. The second channel and via stop layers and second channel openings in the pattern of the first channels. The channel and via dielectric layers are then subject to further photoresist is then stripped. photolithographic process, etching, and photoresist removal An optional thin adhesion layer is deposited on the first 50 steps to form via and second channel openings in the pattern channel dielectric layer and lines the first channel openings of the second channels and the vias. to ensure good adhesion of subsequently deposited material An optional thin adhesion layer is deposited on the second to the first channel dielectric layer. Adhesion layers for channel dielectric layer and lines the second channel and the copper (Cu) conductor materials are composed of compounds such as tantalum nitride (TaN), titanium nitride 55 via openings. A barrier layer is then deposited on the adhesion layer and (TiN), or tungsten nitride (WN). lines the adhesion layer in the second channel openings and These nitride compounds have good adhesion to the the vias. dielectric materials and provide fair barrier resistance to the Again, for conductor materials such as copper and copper diffusion of copper from the copper conductor materials to the dielectric material. High barrier resistance is necessary 60 alloys, a seed layer is deposited by electroless deposition on the barrier layer and lines the barrier layer in the second with conductor materials such as copper to prevent diffusion channel openings and the vias. of subsequently deposited copper into the dielectric layer, A second conductor material is deposited on the seed which can cause short circuits in the integrated circuit. layer and fills the second channel openings and the vias. However, these nitride compounds also have relatively poor adhesion to copper and relatively high electrical resistance. 65 A CMP process is then used to remove the second Because of the drawbacks, pure refractory metals such as conductor material, the seed layer, and the barrier layer tantalum (Ta), titanium (Ti), or tungsten (W) are deposited above the second channel dielectric layer to form the second LOW DIELECTRIC CONSTANT ETCH STOP LAYERS IN INTEGRATED CIRCUIT INTERCONNECTS
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channels. When a layer is placed over the second channels and conductor core. A second dielectric layer is deposited as a final layer, it is called a "capping" layer and the dual over the etch stop layer and a second opening is formed. A second conductor core is deposited to fill the second opendamascene process is completed. ing. The method allows the integrated circuit to have a The capping layer may be an etch stop layer and may be processed farther for placement of additional levels of 5 denser etch stop layer and results in a reduced dielectric constant for the interlayer dielectric layers as a whole. channels and vias over it. Individual and multiple levels of single and dual damascene structures can be formed for The above and additional advantages of the present invensingle and multiple levels of channels and vias, which are tion will become apparent to those skilled in the art from a collectively referred to as "interconnects". reading of the following detailed description when taken in The use of the single and dual damascene techniques 10 conjunction with the accompanying drawings. eliminates metal etch and dielectric gap fill steps typically BRIEF DESCRIPTION OF THE DRAWINGS used in the metalization process. The elimination of metal etch steps is important as the semiconductor industry moves FIG. 1 (PRIOR ART) is a plan view of aligned channels from aluminum (Al) to other metalization materials, such as with a connecting via; copper, which are very difficult to etch. 15 FIG. 2 (PRIOR ART) is a cross-section ofFIG. l (PRIOR Further for placement of additional levels of channels and ART) along line 2-2; and vias over it. Individual and multiple levels of single and dual FIG. 3 is a cross-section, similar to FIG. 2 (PRIOR ART), damascene structures can be formed for single and multiple showing the etch stop layer according to the present invenlevels of channels and vias, which are collectively referred 20 tion. to as "interconnects". The use of the single and dual damascene techniques BEST MODE FOR CARRYING OUT THE eliminates metal etch and dielectric gap fill steps typically INVENTION used in the metallization process. The elimination of metal Referring now to FIG. 1 (PRIOR AR1), therein is shown etch steps is important as the semiconductor industry moves 25 a plan view of a semiconductor wafer 100 with a silicon from aluminum (Al) to other metallization materials, such as semiconductor substrate (not shown) having as interconcopper, which are very difficult to etch. nects first and second channels 102 and 104 connected by a With the development of high integration and highvia 106. The first and second channels 102 and 104 are density very large scale integrated circuits, reductions in the size of transistors and interconnects have been accompanied 30 respectively disposed in first and second channel dielectric layers 108 and 110. The via 106 is an integral part of the by increases in switching speed of such integrated circuits. second channel 104 and is disposed in a via dielectric layer The closeness of the interconnects and the higher switching 112. speeds have increased the problems due to switching slowThe term "horizontal" as used in herein is defined as a downs resulting from capacitance coupling effects between the closely positioned, parallel conductive channels connect- 35 plane parallel to the conventional plane or surface of a wafer, such as the semiconductor wafer 100, regardless of the ing high switching speed semiconductor devices in these orientation of the wafer. The term "vertical" refers to a integrated circuits. Since the capacitance coupling effects direction perpendicular to the horizontal as just defined. are reduced when the dielectric constant of the material Terms, such as "on", "above", "below", "side" (as in between the channels is reduced, this has rendered currently used silicon nitride, which has a dielectric constant in excess 40 "sidewall"), "higher", "lower", "over", and "under", are defined with respect to the horizontal plane. of 7.5, problematic for protective dielectric layers, such as etch stop layers. Referring now to FIG. 2 (PRIOR AR1), therein is shown a cross-section of FIG. 1 (PRIOR AR1) along line 2-2. A A solution for reducing the dielectric constant of the portion of the first channel 102 is disposed in a first channel materials used in interconnects has been long sought but has eluded those skilled in the art. In this area, even small 45 stop layer 114 and is on a device dielectric layer 116, which is on the silicon semiconductor substrate. Generally, metal reductions in the dielectric constant are significant. contacts are formed in the device dielectric layer 116 to DISCLOSURE OF THE INVENTION connect to an operative semiconductor device (not shown). This is represented by the contact of the first channel 102 The present invention provides an integrated circuit having a semiconductor substrate with a semiconductor device. 50 with a semiconductor contact 118 embedded in the device dielectric layer 116. The various layers above the device A dielectric layer is on the semiconductor substrate and has dielectric layer 116 are sequentially: the first channel stop an opening provided therein. A conductor core fills the layer 114, the first channel dielectric layer 108, a via stop opening and an etch stop layer over the first dielectric layer layer 120, the via dielectric layer 112, a second channel stop and conductor core has a dielectric constant below 5.5. A second dielectric layer over the etch stop layer has an 55 layer 122, the second channel dielectric layer 110, and a capping or next channel stop layer 124 (not shown in FIG. opening provided to the conductor core. A second conductor 1). core fills the second opening and is connected to the first conductor core. The resulting integrated circuit has reduced The first channel 102 includes a barrier layer 126, which capacitive coupling effects and is able to operate at higher could optionally be a combined adhesion and barrier layer, speeds. 60 and a seed layer 128 around a conductor core 130. The The present invention further provides a method for second channel 104 and the via 106 include a barrier layer manufacturing an integrated circuit having a semiconductor 132, which could also optionally be a combined adhesion substrate with a semiconductor device. A dielectric layer is and barrier layer, and a seed layer 134 around a conductor formed on the semiconductor substrate and an opening is core 136. The barrier layers 126 and 132 are used to prevent formed in the dielectric layer. A conductor core is deposited 65 diffusion of the conductor materials into the adjacent areas to fill the opening and an etch stop layer with a dielectric of the semiconductor device. The seed layers 128 and 134 form electrodes on which the conductor material of the constant below 5.5 is formed over the first dielectric layer
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layers which are in a thickness "t" as shown in FIG. 3, where conductor cores 130 and 136 are deposited. The seed layers 128 and 134 are of substantially the same conductor material the thickness "t" is from 270 A to 330 A thick. as the conductor cores 130 and 136 and become part of the First, multi-layer depositions may be used which elimirespective conductor cores 130 and 136 after the deposition. nates pinholes and produces a denser film. For example, In the past, for copper conductor material and seed layers, 5 silicon nitride can be deposited in six 50 A layers, either by highly resistive diffusion barrier materials such as tantalum successive deposition or by successive deposition and rotanitride (TaN), titanium nitride (TiN), or tungsten nitride tion between each deposition of a layer. (WN) are used as barrier materials to prevent diffusion. Second, for silicon nitride where silane (SiH 4 ) is used The first channel stop layer 114, the via stop layer 120, with ammonia (NH 3 ), the gas flow can be reduced and the and the second channel stop layer 122 are used as layers to 10 pressure can be increased. For example, silicon nitride is stop the etching process which are used to etch and make the formed in a plasma process using silane at a flow rate of 170 various channel and via openings in the respective first to 290 seem and ammonia at a flow rate of 40 to 48 seem and channel dielectric layer 108, the via dielectric layer 112, and under a pressure of 4.0 to 4.8 torr the second channel dielectric layer 110. The stop layers are of a dielectric material deposited to a thickness "T" by a Third, the silane flow may be reduced to about 50% of the 15 500-watt plasma deposition process in an ammonia (NH 3 ) prior art flow with increased pressure and nitrogen (N2 ) can atmosphere at 4.8 torr pressure. Generally, the stop layer be used in place of the ammonia to reduce hydrogen (H 2 ). material is silicon nitride (SiN, S(Ny), which has a dielectric For example, silicon nitride is formed in a plasma process constant above 7.5 and which is deposited to a thickness "T" using silane at a flow rate of 170 to 290 seem and nitrogen from 470 A to 530 A. at a flow rate of 4700 to 6700 seem and under a pressure of Referring now to FIG. 3, therein is shown a cross-section 20 4.0 to 4.8 torr. similar to that shown in FIG. 2 (PRIOR ART) of a semiFourth, a 500 A thick layer of silicon nitride can be conductor wafer 200 of the present invention. The semicondeposited and then densified, for example, at a temperature ductor wafer 200 has first and second channels 202 and 204 of 450° C. to 480° C. for up to one hour. connected by a via 206. The first and second channels 202 With the reduced dielectric constant and the reduced 25 and 204 are respectively disposed in first and second dielecthickness, the capacitive coupling effect between the first tric layers 208 and 210. The via 206 is a part of the second and second channels 202 and 204 is effectively reduced over channel 204 and is disposed in a via dielectric layer 212. 25% compared to the prior art. A portion of the first channel 202 is disposed in a first In various embodiments, the barrier layers are of materials channel stop layer 214 and is on a device dielectric layer 30 such as tantalum (Ta), titanium (Ti), tungsten (W), com216. Generally, metal contacts (not shown) are formed in the pounds thereof, and combinations thereof. The seed layers device dielectric layer 216 to connect to an operative semi(where used) are of materials such as copper (Cu), gold conductor device (not shown). This is represented by the (Au), silver (Ag), compounds thereof to and combinations contact of the first channel 202 with a semiconductor device thereof with one or more of the above elements. The gate 218 embedded in the device dielectric layer 216. The 35 conductor cores with or without seed layers are of materials various layers above the device dielectric layer 216 are such as copper, aluminum (Al), gold, silver, compounds sequentially: the first channel stop layer 214, the first chanthereof, and combinations thereof. The dielectric layers are nel dielectric layer 208, a via stop layer 220, the via of dielectric materials such as silicon oxide (SiOJ, tetradielectric layer 212, a second channel stop layer 222, the ethoxysilane (TEOS), borophosphosilicate (BPSG) glass, second channel dielectric layer 210, and a next channel stop 40 etc. with dielectric constants from 4.2 to 3.9 or low dielectric layer 224. constant dielectric materials such as fluorinated tetraethoxThe first channel 202 includes a barrier layer 226 and a ysilane (FTEOS), hydrogen silsesquioxane (HSQ), benzoseed layer 228 around a conductor core 230. The second cyclobutene (BCE), etc. with dielectric constants below 3.9. channel 204 and the via 206 include a barrier layer 232 and While the invention has been described in conjunction a seed layer 234 around a conductor core 236. The barrier 45 with a specific best mode, it is to be understood that many layers 226 and 232 are used to prevent diffusion of the alternatives, modifications, and variations will be apparent conductor materials into the adjacent areas of the semiconto those skilled in the art in light of the aforegoing descripductor device. The seed layers 228 and 234 form electrodes tion. Accordingly, it is intended to embrace all such on which the conductor material of the conductor cores 230 and 236 is deposited. The seed layers 228 and 234 are of 50 alternatives, modifications, and variations that fall within the spirit and scope of the included claims. All matters hithersubstantially the same conductor material of the conductor to-fore set forth or shown in the accompanying drawings are cores 230 and 236 and become part of the respective to be interpreted in an illustrative and non-limiting sense. conductor cores 230 and 236 after the deposition. The invention claimed is: The first channel stop layer 214, the via stop layer 220, 1. An integrated circuit comprising: and the second channel stop layer 222 are used as layers to 55 a semiconductor substrate having a semiconductor device stop the etching process which are used to etch and make the provided thereon; various channel and via openings in the respective first a first dielectric layer formed over the semiconductor channel dielectric layer 208, the via dielectric layer 212, and substrate having a first opening provided therein; the second channel dielectric layer 210. a first conductor core filling the first opening and conIn the present invention, a half thickness, high quality, 60 nected to the semiconductor device; etch stop layer (compared to the prior art etch stop layer) is deposited. an etch stop layer of silicon nitride formed over the first dielectric layer and the first conductor core, the etch For example, for silicon nitride, the dielectric constant of stop layer having a dielectric constant below 5.5; an etch stop layer in accordance with the present invention is about 5.5 contrasted to an excess of 7.5 in the prior art. 65 a second dielectric layer formed over the etch stop layer and having a second opening provided therein open to It has been determined that a number of processes can be the first conductor core; used to produce the under 5 .5 dielectric constant etch stop
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a second conductor core filling the second opening and a via dielectric layer formed over the via etch stop layer and having a via opening provided therein open to the connected to the first conductor core. first conductor core; 2. The integrated circuit as claimed in claim 1 wherein the a channel etch stop layer of silicon nitride formed over the etch stop layer is a multilayer structure. via dielectric layer, the channel etch stop layer having 3. The integrated circuit as claimed in claim 1 wherein the s a dielectric constant below 5.5; etch stop layer is a multilayer structure with each of the a second dielectric layer formed over the via dielectric layers having a different layer orientation. layer and having a second opening provided therein 4. The integrated circuit as claimed in claim 1 wherein the open to the via opening; and first and second dielectric layers are of a material having a a second conductor core filling the via and second opendielectric constant under 3. 9. 10 ings and connected to the first conductor core. 5. The integrated circuit as claimed in claim 1 wherein the 7. The integrated circuit as claimed in claim 6 wherein the conductor core contains a material selected from a group via and channel etch stop layers are a multilayer structure. consisting of copper, aluminum, gold, silver, a compound 8. The integrated circuit as claimed in claim 6 wherein the thereof, and a combination thereof. 6. An integrated circuit comprising: 1 s via and channel etch stop layers are multilayer structures with each of the layers having a different layer orientation. a semiconductor substrate having a semiconductor device 9. The integrated circuit as claimed in claim 6 wherein the provided thereon; first, via, and second dielectric layers are of a material a first dielectric layer formed over the semiconductor having a dielectric constant under 3.9. substrate having a first opening provided therein; 10. The integrated circuit as claimed in claim 6 wherein 20 a first conductor core filling the first opening and conthe first and second conductor cores contain materials nected to the semiconductor device; selected from a group consisting of copper, gold, silver, a a via etch stop layer of silicon nitride formed over the first compound thereof, and a combination thereof. dielectric layer and the first conductor core, the via etch stop layer having a dielectric constant below 5.5; * * * * *
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EXHIBIT D
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IIIIII IIIIIIII Ill lllll lllllll llll llll lllll lllll lllll lllll 111111111111111111 US00RE39518E
United States c12) Reissued Patent c19)
Toprac et al.
(45)
(54)
RUN TO RUN CONTROL PROCESS FOR CONTROLLING CRITICAL DIMENSIONS
(75)
Inventors: Anthony John Toprac, Austin, TX (US); Douglas John Downey, Scottsdale, AZ (US); Subhash Gupta, Singapore (SG)
(73)
Assignee: Advanced Micro Devices, Inc., Austin, TX (US)
(21)
Appl. No.: 09/908,390
(22)
Filed:
(52) (58)
U.S. Patent Documents 5,926,690 Jul. 20, 1999 08/864,489 May 28, 1997
Int. Cl. HOJL 21/66 HOJL 21/302
(2006.01) (2006.01)
U.S. Cl. .......................... 438/17; 438/725; 438/780 Field of Classification Search ................... 438/17, 438/16, 725, 780 See application file for complete search history. References Cited
(56)
U.S. PATENT DOCUMENTS 5,629,772 5,655,110 5,773,174 5,939,130
A A A A
* * *
5/1997 8/1997 6/1998 8/1999
Ausschnitt .................. 356/372 Krivokapic et al. ........ 395/500 Koizumi et al ............... 430/30 Shiraishi et al ................ 427/9
(Continued) FOREIGN PATENT DOCUMENTS
EP EP JP
0 810 633 A2 0 863 438 Al 11340134
Patent Number: US RE39,518 E Date of Reissued Patent: Mar. 13, 2007 OTHER PUBLICATIONS Hankinson et al., "Integrated Real-Time and Run-to-Run Control of Etch Depth in Reactive Ion Etching", Mar. 13, 1996, pp. 1-17.* (Continued)
Primary Examiner-W. David Coleman (74) Attorney, Agent, or Firm-Williams, Morgan & Amerson, P.C. ABSTRACT
(57)
Jul. 18, 2001
Related Reissue of: (64) Patent No.: Issued: Appl. No.: Filed: (51)
(IO)
12/1997 9/1998 10/1999
It has been discovered that all causes of critical dimension variation, both known and unknown, are compensated by adjusting the time of photoresist etch. Accordingly, a control method employs a control system using photoresist etch time as a manipulated variable in either a feedforward or a feedback control configuration to control critical dimension variation during semiconductor fabrication. By controlling critical dimensions through the adjustment of photoresist etch time, many advantages are achieved including a reduced lot-to-lot variation, an increased yield, and increased speed of the fabricated circuits. In one embodiment these advantages are achieved for polysilicon gate critical dimension control in microprocessor circuits. Polysilicon gate linewidth variability is reduced using a control method using either feedforward and feedback or feedback alone. In some embodiments, feedback control is implemented for controlling critical dimensions using photoresist each time as a manipulated variable. In an alternative embodiment, critical dimensions are controlled using RF power as a manipulated variable. A run-to-run control technique is used to drive the critical dimensions of integrated circuits to a set specification. In a run-to-run control technique a wafer test or measurement is made and a process control recipe is adjusted based on the result of the test or measurement on a run-by-run basis. The run-to-run control technique is applied to drive the critical dimensions of a polysilicon gate structure to a target specification. The run-to-run control technique is applied to drive the critical dimensions in an integrated circuit to a defined specification using photoresist etch time as a manipulated variable.
104 Claims, 2 Drawing Sheets
NEW RECIPE VARIABLE VALUES
FICD TARGET
UPDATE MODEL
FILTER FICD 112
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US RE39,518 E Page 2
U.S. PATENT DOCUMENTS 6,004,047 6,072,191 6,221,787 6,593,245
A A Bl Bl
*
12/1999 6/2000 4/2001 7/2003
Akimoto et al ............. 396/604 La et al. ....................... 257 /48 Ogata ......................... 438/7 58 Chan .......................... 438/724
OTHER PUBLICATIONS 1995 IEEE/SEMI Advanced Semiconductor Manufacturing Conference-Boning et al., "Practical Issues in Run by Run Process Control", 1995, pp. 201-208.* 187th ECS Meeting in Reno, NV-E. Zafiriou et al., "Nonlineal Model Based Run-To-Run Control For Rapid Thermal Processing With Unmeasured Variable Estimation", May 1995.*
IEEE/CHMT International Electronics Manufacturing Technology Symposium, Austin, Texas-Boning et al., "Run by Run Control of Chemical-Mechanical Polishing", Oct. 2-4, 1995.* VMIC, Santa Clara, CA-Smith et al., "Compensating for CMP Pad Wear Using Run by Run Feedback Control", Jun. 18-20, 1996.* IEEE Transactions on Semiconductor Manufacturing-Sachs et al., "Process Control System for VLSI Fabrication", Apr. 5, 1990, pp. 1-31.* * cited by examiner
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US RE39,518 E
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RUN TO RUN CONTROL PROCESS FOR CONTROLLING CRITICAL DIMENSIONS
possible wafer-to-wafer variations in exposure. Second, the results of the exposure are highly dependent on photoresist thickness so that differences in coating thickness arising in the photoresist coating step are amplified during exposure. Critical dimensions are conventionally tested by randomly sampling one wafer or a few wafers of a lot or multiple lots of processed wafers on post-develop inspection. If a sampled wafer is found to have critical dimensions that are outside specifications, another sample from the lots of processed wafers may be tested. If the subsequent test results in critical dimensions outside specified values, many wafers may be remeasured. If the critical dimensions are consistently outside the specification limits, the lot or entire group of lots are stripped of photoresist and reprocessed through the photolithography process. The critical dimensions of polysilicon gates affect many operating parameters of integrated circuits, but fundamentally the greatest considerations of critical dimensions is speed performance and power consumption of a circuit. The smaller this critical dimension, the faster the operation of the transistor and the integrated circuit as a whole. Too small a polysilicon gate critical dimension, however, results in unacceptably high power consumption and parasitic currents in the transistor. An optimal operating point for this critical dimension is therefore defined by these countervailing effects. Thus, the narrower the distribution of critical dimension values centered about the optimal critical dimension in a lot of wafers, the more high speed, functional circuits are produced. Unfortunately, the critical dimensions resulting from conventional manufacturing methods are rarely optimum, resulting in reduced yield of high performance circuits. Furthermore, the conventional process is very wasteful when process conditions are substandard. What is need is a technique for reducing polysilicon gate linewidth variability and controlling the process at, or very near, the optimal linewidth value. What is further needed is a technique for reducing lot average critical dimensions in a polysilicon gate etch process without negatively impacting other parameters such as uniformity and line shape.
Matter enclosed in heavy brackets [ ] appears in the original patent but forms no part of this reissue specification; matter printed in italics indicates the additions made by reissue.
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BACKGROUND OF THE INVENTION 1. Field of the Invention
The present invention relates to semiconductor fabrication methods. More precisely, the present invention relates to a control system used in semiconductor fabrication for controlling feature critical dimensions. 2. Description of the Related Art Two aspects of feature sizes are controlled in a lithographic and etch process. The first aspect is a critical dimension, the absolute size of a feature, including linewidth, spacing or contact dimensions. The second aspect is the variation in feature size across the wafer surface as measured by steps of a wafer stepper. Linewidth and spacing measurements are regularly performed to determine the actual sizes of critical dimensions at each masking level of a process. Another aspect of linewidth control is that correct feature sizes are to be maintained across an entire wafer and also maintained from wafer to wafer. As a feature size is reduced, the tolerable error on feature size control is also reduced. When an exposure is performed by a wafer stepper, the feature size is controlled across every exposure field and field-to-field variations are to be held within specified limits. Linewidth control is affected by many factors including fabrication tools and equipment, process recipes, and raw materials. Critical dimensions are analyzed by measuring fabricated test structures with nominal feature sizes at many positions of a wafer. The measurement results are then plotted as a function oflocation to determine critical dimension variation. Linewidth control and control of critical dimensions is largely determined by specific characteristics of the steps of photoresist processing. Photoresist processing typically includes steps of substrate cleaning, dehydration baking and priming, spin coating, soft-baking or pre-baking, exposure, post-exposure treatment, a photoresist develop step, inspection following development, plasma de-scumming, postbaking, etching, deep ultraviolet hardening of photoresist, and stripping of the photoresist. Many of these steps are very important for determining linewidth control and control of critical dimensions. For example, dehydration baking and priming assures adhesion of the photoresist during processing. Poor adhesion can cause a loss of linewidth control including the entire loss of pattern elements in extreme cases. The coating process including resist formulation, spinner type, wafer size, spin parameters, and ambient temperature during deposition determine the thickness variation across a wafer which, in turn, influences the critical dimensions across the wafer. Contamination with airborne particles and air bubbles can occur during the coating step. The softbaking step can lead to wafer-to-wafer variations in critical dimensions since, for example, solvent vapors can coat infrared soft-baking lamps changing the energy output. Exposure of the photoresist is a critical step in the resist processing procedure for several reasons. First, exposure is a step in which wafers are processed individually, leading to
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It has been discovered that all causes of critical dimension variation, both known and unknown, are compensated by adjusting the time duration of a photoresist etch. Accordingly, a control method employs a control system using photoresist etch time as a controlling variable in either a feedforward or a feedback control configuration to control critical dimension variation during semiconductor fabrication. By controlling critical dimensions through the adjustment of photoresist etch time, many advantages are achieved including a reduced lot-to-lot variation, an increased yield, and increased speed of the fabricated circuits. In one embodiment these advantages are achieved for polysilicon gate critical dimension control in microprocessor circuits. In accordance with an embodiment of the present invention, polysilicon gate linewidth variability is reduced using a control method using either feedforward or feedback. In some embodiments, feedback control is implemented for controlling critical dimensions using photoresist etch time as a manipulated variable. In an alternative embodiment, critical dimensions are controlled using RF power, gas flow rates, chamber pressure, and/or other recipe variables as manipulated variable(s). In accordance with an embodiment of the present invention, a run-to-run control technique is used to drive the critical dimensions of integrated circuits to a set specifica-
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tion. In a run-to-run control technique a wafer test or measurement is made and a process control recipe is adjusted based on the result of the test or measurement on a run-by-run basis. In accordance with a further embodiment of the present invention, the run-to-run control technique is applied to drive the critical dimensions of a polysilicon gate structure to a target specification. In accordance with a yet further embodiment of the present invention, the run-to-run control technique is applied to drive the critical dimensions in an integrated circuit to a defined specification using photoresist etch time as a manipulated variable. Many advantages are achieved by the described process control method. One advantage is that the control of critical dimension uniformity is substantially improved by the described process. It is also highly advantageous that the described method improves manufacturability as well as control.
The fabrication process 100 of the illustrative embodiment first under-exposes a wafer 102 to initially produce critical dimensions that are larger than target critical dimension values so that the photoresist etch time is subsequently varied during the photoresist etch step 106 to control driving of the critical dimensions to the target value. In one embodiment, the step of under-exposing the wafer 102 involves exposing the wafer to less energy, typically 5 to 15 milliJoules (mJ) less energy, than is used in the nominal process. In a Develop Inspection Critical Dimensions (DICD) step 104, the critical dimensions are measured for some of the wafers following the develop step of the photoresist processing procedure. Measurements performed during the Develop Inspection Critical Dimensions (DICD) step 104 are typically inaccurate by nature relative to the Final Inspect Critical Dimension (FICD) measurement. DICD measurements are relatively noisy and often do not reflect important process variations in the photolithography process. In the illustrated method, the Develop Inspection Critical Dimensions step 104 involves measurement of critical dimensions for three "pilot" wafers in a lot of 24 wafers. In other embodiments of the fabrication process 100 more or fewer wafers may be tested to characterize a full lot of wafers. A single wafer may be tested. The greater the number of tested "pilot" wafers, the better the characterization of the lot remainder. The wafers measured in the Develop Inspection Critical Dimensions step 104 are etched in the photoresist etch step 106 with the etch time set to a nominal photoresist etch time that is based on the initial, average, or moving average operating conditions of the fabrication process 100. The photoresist etch procedure advantageously improves acrosswafer uniformity according to FICD measurements, including improvement of the critical dimension ratio for dense and isolated gate structures. The initial or average operating conditions are set according to the original state of the process model 114. In one embodiment, the nominal etch time is set as an average of the exponentially-weighted moving average of the current photoresist etch times. Following the photoresist etch step 106, the polysilicon gates are etched, the pilot wafers are stripped and cleaned, and the critical dimensions of the etched wafers are measured in a Final Inspection Critical Dimensions (FICD) step 108. Measurements resulting from the Final Inspection Critical Dimensions (FICD) step 108 more accurately reflect the critical dimensions than DICD measurements generally because the photoresist, which resolves relatively poorly in a scarming electron microscope, is stripped from the wafer for the FICD measurement. Various measurement techniques may be used for the Develop Inspection Critical Dimensions step 104 and the Final Inspection Critical Dimensions step 108 including scanning electron microscopy (SEM), mechanical measurement techniques, image shearing, and reflectance measurements. Scanning electron microscopy is highly accurate for measuring line widths. A scarming electron microscope uses an electron beam as an illumination source which is scarmed over a wafer surface. Impinging electrons from the illumination cause ejection of electrons from the wafer surface. The ejected electrons are collected and translated into a picture of the surface of the wafer on a screen or photograph. Once the measurements are acquired in the Develop Inspection Critical Dimensions step 104 and the Final Inspection Critical Dimensions step 108, measurement data
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BRIEF DESCRIPTION OF THE DRAWINGS The features of the described embodiments believed to be novel are specifically set forth in the appended claims. However, embodiments of the invention relating to both structure and method of operation, may best be understood by referring to the following description and accompanying drawings. FIG. 1 is a flow chart which illustrates a control method for controlling critical dimensions in a semiconductor fabrication process by adjusting the fabrication parameters or "recipe" for a photoresist etch step in accordance with an embodiment of the present invention. FIG. 2 is a graph showing the relationship of final inspection critical dimensions to photoresist etch time for developing a process model of the control method depicted in FIG. 1. FIG. 3 is a cross-sectional view of the photoresist line used to create a polysilicon gate structure which is useful for illustrating the quantitative analysis for implementing a process model in accordance with an embodiment of the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Referring to FIG. 1, a flow chart illustrates a control method for controlling critical dimensions in a semiconductor fabrication process 100 by adjusting the fabrication parameters or "recipe" for a photoresist etch step 106 previous to a polysilicon gate etch step in the fabrication process 100. In particular, the critical dimensions are controlled using photoresist etch time as a control variable to drive the critical dimensions to a target value. In overview, the fabrication process 100 involves selection of one or more test wafers, called "pilot" wafers from an entire lot of wafers. The pilot wafers are tested to characterize the lot of wafers, processed through the photoresist etch step 106 using a nominal, average, or moving average processing recipe, and measured in a Final Inspection Critical Dimensions step 108. The results from the pilot lot tests are applied to update a process model 114 which is used to adjust the etch recipe for the remaining wafers in the lot to drive their critical dimensions to the target values. In the illustrative embodiment, scanning electron microscopy (SEM) measurements are made to determine changes in the etch recipe for the remainder of the lot, adjusting the average critical dimension toward a current target critical dimension.
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is added to a database including a DICD database and an FICD database. Measurements acquired during the Develop Inspection Critical Dimensions step 104 are filtered in a filter DICD step 110 and the filtered measurements are applied to the process model 114 to supply a feed forward control of critical dimensions. Similarly, measurements acquired in the Final Inspection Critical Dimensions step 108 are filtered in a filter FICD step 112 and applied to the process model 114 to supply feedback control of critical dimensions. In some embodiments or some applications, only feedback control of critical dimensions is employed using feedback of the FICD measurements. In other embodiments or other applications, feedforward control of critical dimensions is implemented using feedforward of DICD measurements in conjunction with feedback control from FICD measurements. The filter DICD step 110 and the filter FICD step 112 are used for averaging or smoothing of the data for removal of measurement noise such as random noise and measurement variability. In one embodiment, both the filter DICD step 110 and the filter FICD step 112 are performed using an exponentially-weighted moving average filter. In the process model 114, the critical dimension measurements for the pilot wafers are used to determine a proper value for the manipulated variable, the photoresist etch time, and applied to the remaining wafers in the lot. The process model 114 determines the extent that the final inspection critical dimensions differ from the FICD target value and changes the photoresist etch time for the remainder of the lot of wafers. In addition, the value of the average etch time may be updated using the updated or changed new value of etch time. The process model 114 is updated to establish a quantitative relationship between the manipulated variable, photoresist etch time in the illustrative embodiment, and the etched polysilicon gate critical dimensions. The process model 114 is updated by adjusting one or more model parameters such that the latest value of photoresist etch time, when input to the model, gives a model prediction for FICD value which is the same as the measured FICD value resulting from the given photoresist etch time. The measurements acquired during the Develop Inspection Critical Dimensions step 104 are typically not sufficiently accurate and reliable for sole usage in controlling the fabrication process 100 although the measurements are useful for predictive modeling at the early stages of the process model 114. The operation of the process model 114 is shown graphically in FIG. 2 as a relation 200 of final inspection critical dimensions with respect to photoresist etch times. The process model 114 receives measurement data resulting from the pilot test wafers. In the illustrative embodiment, three wafers are included in the set of pilot test wafers. The model relation is updated and centered based on the measurement results so that the updated model reflects the current wafer conditions and the current state of the etcher. The updated model is then used to adjust the etch recipe for the remaining wafers in the lot to improve control of critical dimensions. The improvement is attained through better centering of the FICD mean 204 for each lot at the target critical dimension. The improvement is further attained by decreasing or eliminating variability in the FICD results that are caused by variations in raw materials entered into the fabrication process 100. In the illustrated embodiment, the process model 114 is updated using the measurement of final inspection critical dimensions and the photoresist etch time used for the pilot test wafers. The updated model is used to predict an effective
photoresist etch time to improve critical dimensions for the remaining 24 wafers of the 24 wafer lot. Following etching of all wafers in a lot, the Final Inspection Critical Dimensions step 108 measures the critical dimensions of the remaining wafers in the lot and the process model 114 is updated according to the measurements of the remaining wafers. If a plurality of wafer lot runs are processed, the process model 114 may be continually updated for the series of runs depending on the results of the tests. For example, the fabrication process 100 may be controlled so that the model is either updated or unchanged between runs. Furthermore, the manipulated variable may be set by external adjustment. In one embodiment, the process model 114 uses a quadratic relationship between the critical dimensions and the photoresist etch time. A polynomial function for the critical dimensions is shown in equation (3), as follows:
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FICD=at'+bt+c,
(3)
which may be solved by iterative methods or by using the quadratic formula, shown in equation (4) as follows: 25
-b+ ,,/b2-4ac
(4)
t=-----
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The quadratic relationship is used for modeling various physical phenomena, reverting to a linear relationship for lateral etches and remaining in a quadratic form for isotropic vertical etches. In this embodiment, the c parameter in the quadratic relationship is used to center the relationship between the final inspection critical dimensions and the photoresist etch times. By setting the c parameter, the process model 114 sets the model through a current average operating point which is indicative of the characteristics of the wafers, the etch chamber, and the process in general. Once the current average operating point of the process is set, the model presumably reflects the actual current state of the process, wafers and chamber so that any difference between the final inspection critical dimensions and the target FICD values reflects the amount of time the photoresist etch time is to be changed to drive measured FI CDs to the target value. In some embodiments, the c parameter is derived from the DICD measurement which is supplied using feedforward control of the process model 114. The c parameter is used in this manner as an adjustable constant. In some embodiments, the value of c used to update the model is the value of c determined as described above and then averaged or filtered using the exponentially weighted moving average or other filtering method to "smooth" variations in the c parameter. In an alternative embodiment, the process model 114 is developed based on the sidewall angle of photoresist lines, which is depicted in a cross-sectional view in FIG. 3. In the alternative process model 114 the difference between the Develop Inspection Critical Dimensions step 104 and the Final Inspection Critical Dimensions step 108 is developed, shown in equation (5) as follows:
DICD-FICD=CB+(2*ER *ET*tan(k*ET+8 0 )). 65
(5)
where DICD is the develop inspection critical dimensions, FICD is the final inspection critical dimensions, CB is the chamber bias, ER is the etch rate, ET is the etch time, and
Case 2:16-cv-01170 Document 1-5 Filed 10/14/16 Page 9 of 15 PageID #: 90 US RE39,518 E 7 Ela is the initial sidewall angle of the photoresist. The initial sidewall angle of the photoresist Ela may be a measured parameter. The relationship shown in equation ( 5) reduces to the quadratic form or equation (3) to attain a very good approximation for small angles 8 such that tan 8 is approximately equal to 8. Preliminary studies have shown that usage of the polynomial function as shown in equation (3) and (4) produces a more stable model than usage of a function according to equation (5). The fabrication process 100 uses feedback control of the process recipe using run-by-run control to control critical dimensions. In particular, photoresist etch time is varied depending on the measurement of wafers which were previously processed. In an alternative embodiment, critical dimensions are controlled using radio frequency power as a control variable. Generally, embodiments using photoresist etch time as the control variable advantageously provide more stable control of critical dimensions without unwanted process side-effects. In an alternative embodiment, a plurality of pilot wafers are tested with each pilot wafer representing a "split" of wafers. In one example, a lot of 24 wafers is divided into three splits with each split containing eight wafers. One pilot wafer is assigned for each of the three splits. In the step of under-exposing the wafer 102, the splits are processed separately using a different exposure energy to produce three levels of DICD measurements. The range of DICD measurements is determined based on the range of acceptable values of the manipulated variables, for example the photoresist etch times, and constraints of the process model 114. While the invention has been described with reference to various embodiments, it will be understood that these embodiments are illustrative and that the scope of the invention is not limited to them. Many variations, modifications, additions and improvements of the embodiments described are possible. In various embodiments of the critical dimension control procedure, the method may be practiced in a manual or automatic form. For example, a software system may be used to automate the entire critical dimension control loop. In an alternative implementation of a critical dimension control procedure, a Bottom Anti-Reflective Coating (BARC) etch step is implemented prior to etching of polysilicon or other substrates. The BARC process is used to improve a photolithography process by reducing the stray light photoresist exposure from reflections off a substrate, such as polysilicon. A BARC process involves the formation of an anti-reflective coating beneath the photoresist layer but overlying the polysilicon layer. The BARC layer is etched before the polysilicon is exposed for etching. In an embodiment of a critical dimension control procedure for an implementation of the photoresist processing procedure using a BARC etch step, the BARC etch time may be used as a control variable for controlling critical dimensions, rather than usage of photoresist etch time as the control variable. What is claimed is: 1. A method of fabricating an integrated circuit comprising: pattern, exposure, and develop a photoresist layer on a wafer in a photolithography process that forms a plurality of structures on the integrated circuit including a gate; measuring a DICD critical dimension of the gate following developing of the photoresist layer in a Develop Inspection Critical Dimensions (DICD) operation; etching the wafer including etching of the gate;
8 measuring a FICD critical dimension of the gate following etching of the wafer in a Final Inspection Critical Dimensions (FICD) operation; 5
feeding forward the DICD critical dimension to a process model; feeding back the FICD critical dimension to the process model; and
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controlling a photoresist deposit and etch process recipe parameter in the process model according to the DICD critical dimension and the FICD critical dimension of the gate to improve critical dimension uniformity. 2. A method according to claim 1 wherein: the gate is a polysilicon gate. 3. A method according to claim 1 further comprising: initially underexposing the wafer to initially produce DICD and FICD critical dimensions that are larger than target critical dimension values. 4. A method according to claim 3 further comprising: subsequent to initially underexposing the wafer, varying photoresist etch time to control driving of the FICD critical dimensions to the target critical dimension values. 5. A method according to claim 4 further comprising: etching the wafer using an etch time set to a nominal photoresist etch time that is based on the initial, average, or moving average operating conditions of the fabrication method. 6. A method according to claim 1 wherein: the DICD critical dimension measurement and the FICD critical dimension measurement are measured using a measurement technique selected from among scanning electron microscopy (SEM), mechanical measurement techniques, image shearing, and reflectance measurements. 7. A method according to claim 1 further comprising: storing the DICD critical dimension measurement and the FICD critical dimension measurement in a database. 8. A method according to claim 1 further comprising:
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filtering the DICD critical dimension measurement to supply a filtered feed-forward control of critical dimensions to the process model. 9. A method according to claim 1 further comprising: filtering the FICD critical dimension measurement to supply a filtered feed-back control of critical dimensions to the process model. 10. A method according to claim 1 further comprising: controlling the photoresist deposit and etch process recipe parameter in the process model according to a quadratic relationship between the DICD and the FICD critical dimensions and photoresist etch time. 11. A method according to claim 1 further comprising: controlling the photoresist deposit and etch process recipe parameter in the process model according to a quadratic relationship between the DICD and the FICD critical dimensions and photoresist etch time as follows:
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FICD-at'+bt+c,
Case 2:16-cv-01170 Document 1-5 Filed 10/14/16 Page 10 of 15 PageID #: 91 US RE39,518 E 9 which is solved using the quadratic formula, as follows:
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feeding back the FICD critical dimension to the process model; and controlling a photoresist deposit and etch process recipe -b+~ t= parameter in the process model according to the DICD 2a critical dimension and the FICD critical dimension of the gate to improve critical dimension uniformity. in which parameter c sets a current average operating point. 19. A method according to claim 18 further comprising: 12. A method according to claim 1 further comprising dividing the plurality of wafers into two or more split controlling the photoresist deposit and etch process recipe subsets of wafers; and parameter in the process model according to a relation- 10 processing the split subsets separately using different ship between the difference of the DICD and the FICD exposure levels to produce a respective two or more critical dimensions and photoresist etch time as follevels of DICD critical dimension measurements. lows: 20. A method according to claim 18 wherein: the photoresist deposit and etch process recipe parameter 15 DICD-FICD=CB+(2*ER*E*tan(k*ET +8 0 ) ), for controlling the DICD and the FICD critical dimensions is etch time. in which CB is a chamber bias parameter, ER is etch rate, ET 21. A method offabricating an integrated circuit device, is etch time, and 8 0 is initial sidewall angle of the photocomprising: resist. 20 providing a wafer having a gate electrode material layer 13. A method according to claim 1 further comprising: formed thereabove; performing a run-to-run control technique to drive the forming a patterned layer of photoresist above the gate DICD and the FICD critical dimensions of a polysilielectrode material layer; con gate structure to a target specification. performing a photoresist etching process on the patterned 14. A method according to claim 1 further comprising: 25 layer of photo resist; exposing the photoresist at a selected radio frequency etching the gate electrode material layer to define at least (RF) power; and one gate electrode in said gate electrode material selecting the selected RF power as the selected photoresist layer; deposit and etch process recipe parameter for controlmeasuring a critical dimension of said at least one gate 30 ling the DICD and FICD critical dimensions. electrode; and 15. A method according to claim 1 wherein: controlling a duration of a photoresist etching process to the photoresist deposit and etch process recipe parameter be performed on a patterned layer of photoresist for controlling the DICD and the FICD critical dimenformed above at least one subsequently provided wafer sions is etch time. based upon said measured critical dimension and a 16. A method according to claim 1 further comprising: 35 target critical dimension for said at least one gate forming a polysilicon layer overlying a substrate; electrode. depositing a photoresist layer on the polysilicon layer; 22. The method of claim 21, wherein providing a wafer etching the deposited photoresist layer for a controlled having a gate electrode material layer formed thereabove photoresist etch time; and 40 comprises providing a wafer having a gate electrode material layer comprised of polysilicon formed thereabove. etching the polysilicon layer subsequent to the step of 23. The method of claim 21, wherein forming a patterned etching the deposited photoresist layer. layer ofphoto resist above the gate electrode material layer 17. A method according to claim 1 further comprising: comprises forming a patterned layer ofphotoresist above the forming an anti-reflective coating beneath the photoresist 45 gate electrode material layer by performing at least an layer using a Bottom Anti-Reflective Coating (BARC) exposure process, a post-exposure bake process and a etch step to reduce stray light photoresist exposure photoresist develop process. from reflections off a substrate. 24. The method of claim 21, wherein measuring a critical 18. A method of fabricating an integrated circuit comdimension of said at least one gate electrode comprises prising: 50 measuring a critical dimension of said at least one gate pattern, expose, and develop a photoresist layer on a electrode by using at least one of scanning electron plurality of wafers in a photolithography process that microscopy, image shearing, and reflective measurements. forms a plurality of structures on the integrated circuit 25. The method of claim 21, further comprising storing including a gate; said measured critical dimension in a database. measuring a DICD critical dimension of the gate in a pilot 55 26. The method of claim 21, further comprising feeding subset of the plurality of wafers following developing back the measured critical dimension ofthe at least one gate of the photoresist layer in a Develop Inspection Critical electrode to a process model. Dimensions (DICD) operation; 2 7. The method of claim 26, further comprising filtering etching wafers of the plurality of wafers remaining after the measured critical dimension prior to feeding back the removal of the pilot subset, the etching including 60 measured critical dimension to the process model. etching of the gate; 28. The method of claim 21, wherein controlling a durameasuring a FICD critical dimension of the gate followtion of a photoresist etch process is based upon a compariing etching of the plurality of wafers remaining after son between said measured critical dimension and said removal of the pilot subset in a Final Inspection Critical target critical dimension for said at least one gate electrode. Dimensions (FICD) operation; 65 29. The method of claim 21, wherein controlling a duration of a photoresist etching process to be performed on a feeding forward the DICD critical dimension to a process patterned layer of photoresist formed above at least one model;
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above at least one subsequently provided wafer based upon subsequently provided wafer based upon a comparison a quadratic relationship between the measured critical between said measured critical dimension and a target dimensions and the duration of the photo resist etch process. critical dimension for said at least one gate electrode 39. The method of claim 32, further comprising measurcomprises controlling a duration of a photoresist etching process to be performed on a patterned layer ofphotoresist 5 ing a critical dimension ofa feature formed in said patterned layer of photoresist prior to performing said photoresist formed above at least one subsequently provided wafer etching process. based upon a quadratic relationship between the measured 40. The method of claim 39, wherein controlling a duracritical dimension and the duration of the photoresist etch tion of a photo resist etching process comprises controlling a process. duration ofsaid photo resist etching process based upon said 30. The method of claim 21, further comprising measur- 10 measured critical dimension of said gate electrode, said ing a critical dimension ofa feature formed in said patterned measured critical dimension ofsaid feature in said patterned layer of photoresist prior to performing said photoresist layer of photoresist, and said target value for said gate etching process. electrode. 31. The method of claim 30, wherein controlling a dura41. A method offabricating an integrated circuit device, tion of a photoresist etching process comprises controlling a 15 comprising: duration ofsaid photoresist etching process based upon said providing a wafer having a gate electrode material layer measured critical dimension of said gate electrode, said comprised of polysilicon formed thereabove; measured critical dimension ofsaid feature in said patterned forming a patterned layer of photoresist above the gate layer of photoresist, and said target value for said gate electrode material layer; electrode. 20 performing a photoresist etching process on the patterned 32. A method offabricating an integrated circuit device, layer of photo resist; comprising: etching the gate electrode material layer using the etched providing a wafer having a gate electrode material layer patterned layer of photoresist as a mask to define a comprised of polysilicon formed thereabove; plurality of gate electrodes comprised of polysilicon; 25 forming a patterned layer of photo resist above the gate measuring a critical dimension of a plurality of said gate electrode material layer; electrodes; performing a photo resist etching process on the patterned feeding back the measured critical dimensions of the layer of photo resist; plurality of gate electrodes to a process model; and etching the gate electrode material layer using the etched 30 controlling a duration of a photoresist etching process to patterned layer of photoresist as a mask to define a be performed on a patterned layer of photoresist plurality of gate electrodes comprised ofpolysilicon; formed above at least one subsequently provided wafer measuring a critical dimension of a plurality of said gate based upon a comparison between said measured critielectrodes; and cal dimensions and a target critical dimension for said plurality of gate electrodes. controlling a duration of a photoresist etching process to 35 42. The method of claim 41, wherein forming a patterned be performed on a patterned layer of photoresist formed above at least one subsequently provided wafer layer ofphoto resist above the gate electrode material layer based upon a comparison between said measured criticomprises forming a patterned layer ofphotoresist above the cal dimensions and a target critical dimension for said gate electrode material layer by performing at least an 40 exposure process, a post-exposure bake process and a plurality of gate electrodes. 33. The method of claim 32, wherein forming a patterned photoresist develop process. 43. The method of claim 41, wherein measuring a critical layer ofphoto resist above the gate electrode material layer comprises forming a patterned layer ofphotoresist above the dimension of a plurality of gate electrodes comprises meagate electrode material layer by performing at least an suring a critical dimension of a plurality of gate electrodes exposure process, a post-exposure bake process and a 45 by using at least one ofscanning electron microscopy, image shearing, and reflective measurements. photoresist develop process. 44. The method of claim 41, further comprising filtering 34. The method of claim 3 2, wherein measuring a critical dimension of a plurality of gate electrodes comprises meathe measured critical dimensions prior to feeding back the suring a critical dimension of a plurality of gate electrodes measured critical dimensions to the process model. by using at least one ofscanning electron microscopy, image 50 45. The method of claim 41, wherein controlling a durashearing, and reflective measurements. tion of a photoresist etching process to be performed on a 35. The method of claim 32, further comprising storing patterned layer of photoresist formed above at least one said measured critical dimensions in a database. subsequently provided wafer based upon a comparison between said measured critical dimensions and a target 36. The method of claim 32, further comprising feeding back the measured critical dimensions of the plurality of 55 critical dimension for said plurality of gate electrodes gate electrodes to a process model. comprises controlling a duration of a photoresist etching 3 7. The method of claim 3 6, further comprising filtering process to be performed on a patterned layer ofphotoresist formed above at least one subsequently provided wafer the measured critical dimensions prior to feeding back the measured critical dimensions to the process model. based upon a quadratic relationship between the measured 38. The method of claim 32, wherein controlling a dura- 60 critical dimensions and the duration of the photo resist etch tion of a photoresist etching process to be performed on a process. patterned layer of photoresist formed above at least one 46. The method of claim 41, further comprising storing subsequently provided wafer based upon a comparison said measured critical dimensions in a database. 47. The method of claim 41, further comprising measurbetween said measured critical dimensions and a target critical dimension of said plurality of gate electrodes com- 65 ing a critical dimension ofa feature formed in said patterned prises controlling a duration ofa photoresist etching process layer of photoresist prior to performing said photoresist etching process. to be performed on a patterned layer ofphotoresist formed
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48. The method of claim 47, wherein controlling a duration of a photoresist etching process comprises controlling a duration ofsaid photoresist etching process based upon said measured critical dimension of said gate electrode, said measured critical dimension ofsaid feature in said patterned layer of photoresist, and said target value for said gate electrode. 49. A method offabricating an integrated circuit device, comprising: providing a wafer having a gate electrode material layer formed thereabove; forming a patterned layer of photo resist above the gate electrode material layer; performing a photo resist etching process on the patterned layer of photo resist; etching the gate electrode material layer to define at least one patterned feature in said gate electrode material layer; measuring a critical dimension of said at least one patterned feature; and
58. The method of claim 49, further comprising measuring a critical dimension ofa feature formed in said patterned layer of photoresist prior to performing said photoresist etching process. 59. The method of claim 58, wherein controlling at least one parameter of a photoresist etching process comprises controlling at least one parameter of said photoresist etching process based upon said measured critical dimension of said at least one patterned feature, said measured critical dimension of said feature in said patterned layer of photoresist, and said target value for said at least one patterned feature. 60. The method of claim 49, wherein etching the gate electrode material layer to define at least one patterned feature in said gate electrode material layer comprises etching the gate electrode material layer to define at least one gate electrode in said gate electrode material layer. 61. The method of claim 60, wherein measuring a critical dimension of said at least one patterned feature comprises measuring a critical dimension of said at least one gate electrode. 62. The method of claim 49, wherein controlling at least one parameter of a photoresist etching process to be performed on a patterned layer ofphotoresist formed above at least one subsequently provided wafer based upon said measured critical dimension and a target critical dimension for said at least one patterned feature comprises controlling a duration of a photoresist etching process to be performed on a patterned layer ofphoto resist formed above at least one subsequently provided wafer based upon said measured critical dimension and a target critical dimension for said at least one patterned feature. 63. A method offabricating an integrated circuit device, comprising: providing a wafer having a gate electrode material layer formed thereabove; forming a patterned layer of photoresist above the gate electrode material layer; performing a photoresist etching process on the patterned layer of photo resist; etching the gate electrode material layer using the etched patterned layer of photoresist as a mask to define a plurality of patterned features; measuring a critical dimension of a plurality of said patterned features; and controlling at least one parameter of a photoresist etching process to be performed on a patterned layer of photo resist formed above at least one subsequently provided wafer based upon a comparison between said measured critical dimensions and a target critical dimension for said plurality of patterned features. 64. The method of claim 63, wherein forming a patterned layer ofphoto resist above the gate electrode material layer comprises forming a patterned layer ofphotoresist above the gate electrode material layer by performing at least an exposure process, a post-exposure bake process and a photoresist develop process. 65. The method of claim 63, wherein measuring a critical dimension of a plurality of patterned features comprises measuring a critical dimension of a plurality of patterned features by using at least one of scanning electron microscopy, image shearing, and reflective measurements. 66. The method of claim 63, further comprising storing said measured critical dimensions in a database. 67. The method of claim 63, further comprising feeding back the measured critical dimensions of the plurality of patterned features to a process model.
controlling at least one parameter of a photoresist etching process to be performed on a patterned layer of photoresist formed above at least one subsequently provided wafer based upon said measured critical dimension and a target critical dimension for said at least one patterned feature. 50. The method of claim 4 9, wherein providing a wafer having a gate electrode material layer formed thereabove comprises providing a wafer having a gate electrode material layer comprised of polysilicon formed thereabove. 51. The method of claim 49, wherein forming a patterned layer ofphoto resist above the gate electrode material layer comprises forming a patterned layer ofphotoresist above the gate electrode material layer by performing at least an exposure process, a post-exposure bake process and a photoresist develop process. 52. The method of claim 49, wherein measuring a critical dimension of said at least one patterned feature comprises measuring a critical dimension ofsaid at least one patterned feature by using at least one of scanning electron microscopy, image shearing, and reflective measurements. 53. The method of claim 49, further comprising storing said measured critical dimension in a database. 54. The method of claim 49, further comprising feeding back the measured critical dimension of the at least one patterned feature to a process model. 55. The method of claim 54, further comprising filtering the measured critical dimension prior to feeding back the measured critical dimension to the process model. 56. The method of claim 4 9, wherein controlling at least parameter of a photoresist etch process is based upon a comparison between said measured critical dimension and said target critical dimension for said at least one patterned feature. 57. The method of claim 49, wherein controlling at least one parameter of a photoresist etching process to be performed on a patterned layer ofphotoresist formed above at least one subsequently provided wafer based upon a comparison between said measured critical dimension and a target critical dimension for said at least one patterned feature comprises controlling at least one parameter of a photoresist etching process to be performed on a patterned layer ofphotoresist formed above at least one subsequently provided wafer based upon a quadratic relationship between the measured critical dimension and a duration of the photoresist etch process.
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68. The method of claim 67, further comprising filtering the measured critical dimensions prior to feeding back the measured critical dimensions to the process model. 69. The method of claim 63, wherein controlling at least one parameter of a photoresist etching process to be performed on a patterned layer ofphotoresist formed above at least one subsequently provided wafer based upon a comparison between said measured critical dimensions and a target critical dimension of said plurality of patterned features comprises controlling at least one parameter of a photoresist etching process to be performed on a patterned layer ofphotoresist formed above at least one subsequently provided wafer based upon a quadratic relationship between the measured critical dimensions and a duration of the photoresist etch process. 70. The method of claim 63, further comprising measuring a critical dimension of a plurality offeatures formed in said patterned layer ofphotoresist prior to performing said photoresist etching process. 71. The method of claim 70, wherein controlling at least one parameter of a photoresist etching process comprises controlling at least one parameter of said photoresist etching process based upon said measured critical dimension of said plurality of patterned features, said measured critical dimension of said plurality of features in said patterned layer ofphotoresist, and said target value for said plurality of patterned features. 72. The method of claim 63, wherein etching the gate electrode material layer using the etched patterned layer of photoresist as a mask to define a plurality of patterned features comprises etching the gate electrode material layer using the etched patterned layer ofphoto resist as a mask to define a plurality of gate electrodes. 73. The method of claim 70, wherein measuring a critical dimension ofa plurality ofsaid patterned features comprises measuring a critical dimension of a plurality of said gate electrodes. 74. The method of claim 63, wherein controlling at least one parameter of a photoresist etching process to be performed on a patterned layer ofphotoresist formed above at least one subsequently provided wafer based upon a comparison between said measured critical dimensions and a target critical dimension for said plurality of patterned features comprises controlling a duration of a photoresist etching process to be performed on a patterned layer of photoresist formed above at least one subsequently provided wafer based upon a comparison between said measured critical dimensions and a target critical dimension for said plurality of patterned features. 75. A method offabricating an integrated circuit device, comprising: providing a wafer having a gate electrode material layer formed thereabove; forming a patterned layer of photo resist above the gate electrode material layer; performing a photo resist etching process on the patterned layer of photo resist; etching the gate electrode material layer using the etched patterned layer of photoresist as a mask to define a plurality of patterned features; measuring a critical dimension of a plurality of said patterned features; feeding back the measured critical dimensions of the plurality ofpatterned features to a process model; and controlling at least one parameter of a photoresist etching process to be performed on a patterned layer of photo resist formed above at least one subsequently provided wafer based upon a comparison between said
measured critical dimensions and a target critical dimension for said plurality of patterned features. 76. The method of claim 75, wherein forming a patterned layer ofphoto resist above the gate electrode material layer comprises forming a patterned layer ofphotoresist above the gate electrode material layer by performing at least an exposure process, a post-exposure bake process and a photoresist develop process. 77. The method of claim 75, wherein measuring a critical dimension of a plurality of patterned features comprises measuring a critical dimension of a plurality of patterned features by using at least one of scanning electron microscopy, image shearing, and reflective measurements. 78. The method of claim 75, further comprising filtering the measured critical dimensions prior to feeding back the measured critical dimensions to the process model. 79. The method of claim 75, wherein controlling at least one parameter of a photoresist etching process to be performed on a patterned layer ofphotoresist formed above at least one subsequently provided wafer based upon a comparison between said measured critical dimensions and a target critical dimension for said plurality of patterned features comprises controlling at least one parameter of a photoresist etching process to be performed on a patterned layer ofphotoresist formed above at least one subsequently provided wafer based upon a quadratic relationship between the measured critical dimensions and a duration of the photoresist etch process. 80. The method of claim 75, further comprising storing said measured critical dimensions in a database. 81. The method of claim 75, further comprising measuring a critical dimension ofat least one feature formed in said patterned layer of photoresist prior to performing said photoresist etching process. 82. The method of claim 81, wherein controlling at least one parameter of a photoresist etching process comprises controlling at least one parameter of said photoresist etching process based upon said measured critical dimension of a plurality of said patterned features, said measured critical dimension ofsaid at least one feature in said patterned layer of photoresist, and said target value for said patterned features. 83. The method of claim 75, wherein etching the gate electrode material layer using the etched patterned layer of photoresist as a mask to define a plurality of patterned features comprises etching the gate electrode material layer using the etched patterned layer ofphoto resist as a mask to define a plurality of gate electrodes. 84. The method of claim 83, wherein measuring a critical dimension ofa plurality ofsaid patternedfeatures comprises measuring a critical dimension of a plurality of said gate electrodes. 85. The method of claim 83, wherein feeding back the measured critical dimensions of the plurality of patterned features to a process model comprises feeding back the measured critical dimensions of the plurality of gate electrodes to a process model. 86. The method of claim 75, wherein controlling at least one parameter of a photoresist etching process to be performed on a patterned layer ofphotoresist formed above at least one subsequently provided wafer based upon a comparison between said measured critical dimensions and a target critical dimension for said plurality of patterned features comprises controlling a duration of a photoresist etching process to be performed on a patterned layer of photoresist formed above at least one subsequently provided wafer based upon a comparison between said measured critical dimensions and a target critical dimension for said plurality of patterned features.
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87. A method offabricating an integrated circuit device, comprising: providing a wafer having a gate electrode material layer formed thereabove; forming a patterned layer of photo resist above the gate electrode material layer, said patterned layer of photoresist having a plurality offeatures formed therein; measuring a critical dimension of at least one of said features in said patterned layer ofphotoresist prior to performing a photoresist etching process on said patterned layer of photo resist; and controlling a duration of said photoresist etching process based upon at least said measured critical dimension of said at least one feature in said patterned layer of photoresist. 88. The method of claim 87, further comprising etching said gate electrode material layer after said photoresist etching process has been performed using said patterned layer ofphotoresist as a mask to thereby define at least one feature in said gate electrode material layer. 89. The method of claim 88, further comprising measuring a critical dimension of at least one of said features in said gate electrode material layer. 90. The method of claim 88, wherein said at least one feature in said gate electrode materia l layer is a gate electrode. 91. A method offabricating an integrated circuit device, comprising: providing a wafer having a gate electrode material layer formed thereabove; forming a patterned layer of photo resist above the gate electrode material layer, said layer ofphoto resist having a plurality offeatures formed therein; measuring a critical dimension of at least one of said features in said patterned layer ofphotoresist prior to performing a photoresist etching process on said patterned layer of photo resist; determining a duration ofsaid photoresist etching process based upon at least said measured critical dimension of said at least one feature in said patterned layer of photoresist; and performing said photoresist etch process for said determined duration on a patterned layer of photoresist formed above at least one subsequently processed wafer. 92. The method of claim 91, further comprising etching said gate electrode material layer after said photoresist etching process has been performed to thereby define at least one feature in said gate electrode material layer. 93. The method of claim 92, further comprising measuring a critical dimension of at least one of said features in said gate electrode material layer. 94. The method of claim 92, wherein said at least one feature in said gate electrode material layer is a gate electrode. 95. A method offabricating an integrated circuit device, comprising: providing a wafer having a gate electrode material layer formed thereabove;
forming a patterned layer of photo resist above the gate electrode material layer, said patterned layer of photo resist having a plurality offeatures formed therein; measuring a critical dimension of at least one of said features in said patterned layer ofphotoresist prior to performing a photoresist etching process on said patterned layer of photo resist; and controlling at least one parameter of said photoresist etching process based upon at least said measured critical dimension of said at least one feature in said patterned layer of photo resist. 96. The method of claim 95, further comprising etching said gate electrode material layer after said photoresist etching process has been performed using said patterned layer ofphoto resist as a mask to thereby define at least one feature in said gate electrode material layer. 97. The method of claim 96, further comprising measuring a critical dimension of at least one of said features in said gate electrode material layer. 98. The method of claim 96, wherein said at least one feature in said gate electrode material layer is a gate electrode. 99. The method of claim 95, wherein said at least one parameter comprises at least one of RF power, a gas flow rate and a chamber pressure. 100. A method offabricating an integrated circuit device, comprising: providing a wafer having a gate electrode material layer formed thereabove; forming a patterned layer of photo resist above the gate electrode material layer, said layer ofphoto resist having a plurality offeatures formed therein; measuring a critical dimension of at least one of said features in said patterned layer ofphotoresist prior to performing a photoresist etching process on said patterned layer of photo resist; determining at least one parameter of said photoresist etching process based upon at least said measured critical dimension of said at least one feature in said patterned layer of photo resist; and performing said photoresist etch process for said determined duration on a patterned layer of photoresist formed above at least one subsequently process wafer. 101. The method of claim 100,further comprising etching said gate electrode material layer after said photoresist etching process has been performed to thereby define at least one feature in said gate electrode material layer. 102. The method of claim 101, further comprising measuring a critical dimension of at least one ofsaid features in said gate electrode material layer. 103. The method of claim 101, wherein said at least one feature in said gate electrode material layer is a gate electrode. 104. The method of claim 100, wherein said at least one parameter comprises at least one of RF power, a gas flow rate and a chamber pressure.
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Case 2:16-cv-01170 Document 1-5 Filed 10/14/16 Page 15 of 15 PageID #: 96 UNITED STATES PATENT AND TRADEMARK OFFICE
CERTIFICATE OF CORRECTION PATENT NO. APPLICATION NO. DATED INVENTOR(S)
: RE 39,518 E Page 1 of 1 : 09/908390 : March 13, 2007 : Anthony John Toprac, Douglas John Downey and Subhash Gupta
It is certified that error appears in the above-identified patent and that said Letters Patent is hereby corrected as shown below:
Col. 7, line 60 (claim 1, line 3), change "exposure" to -- expose--. Col. 18, line 45 (claim 100, line 18), change "process" to -- processed--.
Signed and Sealed this Twenty-fourth Day of April, 2007
JONW.DUDAS Director of the United States Patent and Trademark Office
