Data Storage

MoS2 Nanosheets for Top-Gate Nonvolatile Memory Transistor Channel Hee Sung Lee, Sung-Wook Min, Min Kyu Park, Young Tack Lee, Pyo Jin Jeon, Jae Hoon Kim, Sunmin Ryu, and Seongil Im* Graphene and related 2D nanosheet materials have received much attention in view of their applications for future nanoelectronics.[1,2] These new 2D materials have initially been prepared by the exfoliation method using scotch tape, that is, the micromechanical cleavage technique.[3] Graphene has a high carrier mobility (μ) over 100 000 cm2/(V·s), but it also reveals some limitations in device applications: an intrinsic difficulty caused by its rather small bandgap (Eg).[4–6] Even though significant efforts to open up the bandgap of graphene were made bymodifying its form into a nanoribbon, the gap turned out to be only around 200 meV while the intrinsic mobility was seriously reduced to ~200 cm2/(V·s).[7,8] Due to the bandgap problems, graphene can hardly be used in its natural form for switching circuits or nonvolatile memory applications, which need clearly defined on-and-off or program (write)-and-erase states. As a result, graphene oxide, which is electrically insulating with a high bandgap, has been applied for nonvolatile memory.[9,10] Very recently, molybdenum disulfide (MoS2) layers appeared to overcome the dilemma of graphene as an alternative nanosheet material prepared by the same exfoliation technique.[11–14] Although the Eg of bulk MoS2 is known to be ~1.2 eV of indirect type, the few-angstrom-thin singlelayered MoS2 has recently been reported to exhibit a direct bandgap of 1.8 eV and a high mobility of ~200–350 cm2/(V·s) when used as the channel of a top-gate transistor with thin HfO2 oxide, whose high dielectric constant, κ (~25) probably causes dielectric screening for mobility enhancement.[14–19] Furthermore, due to the large bandgap of MoS2, the singlelayered MoS2 transistor displayed a high on/off current ratio of ~106–108 under quite a low operating voltage, and also exhibited a very low subthreshold swing of 74 mV/decade (mV/dec), benefiting from the absence of dangling bonds in a MoS2 single layer.[14,20–24] Since only a few top-gate transistor H. S. Lee, S.-W. Min, Y. T. Lee, P. J. Jeon, Prof. J. H. Kim, Prof. S. Im Institute of Physics and Applied Physics Yonsei University 262 Seongsanno, Seodaemun-gu, Seoul 120-749, Korea E-mail: [email protected] M. K. Park, Prof. S. Ryu Department of Applied Chemistry Kyung Hee University Yongin, Gyeonggi 446-701, Korea DOI: 10.1002/smll.201200752 small 2012, 8, No. 20, 3111–3115

results particularly with HfO2 have been reported, any type of top-gate nanodevice research with single-layered MoS2 is very timely and necessary and would be a major step toward full-scale device applications. Here, we demonstrate topgate nonvolatile memory field-effect transistors (FETs) with single- to triple-layered MoS2 nanosheets adopting a ferroelectric polymer poly(vinylidenefluoride-trifluoroethylene) [P(VDF-TrFE)].[25–27] Our nonvolatile-memory FET with a single-layer MoS2 channel exhibited little degradation in its retention properties as measured up to 1000 s maintaining ~5 × 103 as its program/erase ratio and also displayed a maximum mobility of 220 cm2/(V·s), which is comparable to the previous value obtained from a top-gate transistor using a thin HfO2 dielectric.[14] A surface-cleaned 285-nm-thick SiO2/p++-Si wafer was chosen as the substrate for our n-type MoS2 nanosheet transistor with Au source/drain (S/D) electrodes, since 285 nm was reported as an optimal thickness to identify a few-layer dichalcogenide.[28,29] Indeed, each exfoliated MoS2 flake showed a distinctive optical contrast with thinner flakes exhibiting less optical density, which enabled fast screening of few-layered flakes under the optical microscope. Figure 1a and b displayed a single-layer MoS2 flake which was caught via photolithography to contact with patterned Au for the S/D electrodes. Since the flake size was as long as ~10 μm, a 5-μm-long channel was available for our device [width/ length (W/L) ratio was ~1]. The largest flake was ~17-μmlong as shown in Figure S1a,b (Supporting Information, SI). Figure 1c illustrates a top-view 3D scheme of our FET with single-layered MoS2 and ferroelectric P(VDF-TrFE) polymer. Figure 1d shows Raman spectra obtained from the five samples assigned to single-, double-, three-to-four-, four-, and fivelayered MoS2 flakes spanning ~5 μm × 5 μm. As shown by the previous report,[30] the frequency difference between E12g and A1g, the two prominent Raman-active modes of 2H-MoS2 crystals, increases stepwise with the number of layers (see the plot of Figure 1e). The interpeak separation or frequency difference for the thinnest flake in Figure 1d is 18.0 ± 1.0 cm−1 which is in excellent agreement with that for single-layer MoS2.[30] Confirming the layer number of exfoliated flakes by Raman spectra, we selected a single-layer MoS2 as the channel of our nanosheet transistor for high mobility and ferroelectric nonvolatile memory applications. The thickness of monolayer MoS2 was measured by previous researchers to be ~0.65 nm.[14] Even though other exfoliated flakes exist around

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HfO2, resulting in a slower charging rate at the MoS2 channel. After the long-range (from –20 to +20 V) VG sweep for memory hysteresis, a short-range sweep between –4 and 0 V was also performed following the 1 s gate pulses of +20 and –20 V, so the two distinct states of write (WR) and erase (ER) were respectively obtained as overlapped with the long-range memory hysteresis curve. Since the full memory hysteresis window of 200-nm-thick P(VDFTrFE) itself is around 20 V according to general remnant charge density–applied electric field (Pr–E) and capacitance– voltage (C–V) curves (Figure S4, SI), it is likely that our nanosheet MoS2 ferroelectric FET achieves 70% of full polarization of internal dipoles under the condition of VD = 1 V, maintaining the high mobility and excellent WR/ER current ratio. This impressive result shows that the MoS2 nanosheet can effectively be used as a channel in nonvolatile memory devices; Figure 1. a) Optical microscope image of exfoliated MoS2 flakes including a single layer. b) Optical microscope image of the bottom-gate transistor with the single-layer MoS2 channel graphene could hardly achieve these fea[31–33] The ER and WR states in the caught by the Au S/D electrodes. c) Schematic 3D top-view of our memory FET with the single- tures. layer MoS2 nanosheet of hexagonal structure, 200-nm-thick ferroelectric P(VDF-TrFE) polymer, memory transistor were again confirmed and Al gate. Input voltage (VIN) was applied to the Al gate as pulses or bias sweep exceeding by the ID–VD output curves obtained after coercive electric field (0.55 MV/cm). d) Raman spectra of 1-, 2-, ~(3–4)-, 4-, and 5- layers of the respective pulses of –20 and +20 V MoS2. The inset figure shows atomic displacements of the two Raman-active modes: E12g for 1 s (see Figure S5, SI). According to and A1g. e) The frequency difference between E12g and A1g vibration mode increases with the the retention plots of Figure 2b, the two layer number. distinctive states were maintained and recorded for 1000 s without a notable our single-layer MoS2, as shown in the optical microscopy ID variation under the continuous VD bias of 1 V after the image of Figure 1a, our single-layer MoS2 transistor with no respective pulses of ±20 V. The WR/ER ratio in ID current top dielectric layer operated well in the bottom-gate mode was over ∼5 × 103 and the ratio was quite nicely maintained with a mobility of ~22 cm2/(V·s) and an on/off drain current even during the dynamic switching of WR/ER states. When (ID) ratio of ~105 (Figure S2a, SI). According to the drain alternating pulses for dynamic WR/read/ER/read processes current–drain voltage (ID–VD) curves of Figure S2b (SI), our were applied onto the gate as shown in the inset diagram of single-layered MoS2 channel shows an almost ohmic contact Figure 2c, we were able to observe the slightly reduced WR/ ER ratio of 2×103. with the Au S/D electrodes. We fabricated a second ferroelectric nonvolatile memory Unlike the bottom-gate-controlled device, a much higher mobility was achieved from our top-gate ferroelectric non- transistor with double-layered MoS2 channel and observed volatile memory transistor as shown in its transfer charac- similarly distinct WR/ER states from its memory hysteresis teristics of Figure 2a (at VD = 1 V). The memory hysteresis curves in Figure 3a, where a reduced memory window was window of the transistor with 200-nm-thick P(VDF-TrFE) found, however, to be ∼6 V. In this case, the memory transistor polymer appears to be ∼14 V as the long-range gate voltage shows the reduced μlin of 34 cm2/(V·s) along with the on/off (VG) sweep is performed between –20 and 20 V. The linear ID ratio of over ∼104. Moreover, the S.S. was ∼2 V/dec, which mobility, μlin of the memory transistor was ∼220 cm2/(V·s) is incomparably larger than 300 mV/dec from the single-layer at maximum, along with the on/off ID ratio over ∼105. The channel. These low mobility and degraded S.S. results may μlin was estimated and plotted as a function of VG, based be coupled with the possibilities of carrier scattering in the on the following equations: gm(VG) = dID/dVG and μlin = thickness-direction and phonon-assisted scattering in double(gm/CoxVD)·(L/W), where gm and Cox respectively represent layer MoS2 which may be sensitive to the indirect bandgap, if transconductance and gate-dielectric/ferroelectric capaci- we assume no difference in surface roughness among singletance (see mobility plot in Figure S3, SI). The subthreshold to triple-MoS2 layers.[34] The short-range VG sweep after the swing (S.S.) appears to be around 300 mV/dec, which is still WR and ER pulses also showed the two distinct states but good but four times higher than that (74 mV/dec) of the pre- with a small WR/ER ratio of ∼20. According to Figure 3b, the viously reported transistor with high-κ HfO2. It is probably retention properties are well maintained for 1000 s under the because the dipole aligning speed (polarization speed) in continuous VD (= 1 V) bias condition, although the WR/ER organic ferroelectric might be slower than that in inorganic ID ratio (<∼100) was relatively lower than that of single-layer

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MoS2 Nanosheets for Top-Gate Nonvolatile Memory

Figure 2. a) The transfer curve of top-gate-driving single-layer MoS2 transistor with P(VDF-TrFE) ferroelectric layer; VG sweep range = –20 to +20 V and VD = 1 V. Memory hysteresis window of the transistor with 200-nm-thick P(VDF-TrFE) polymer appears to be ∼14 V. Short pulses of +20 and –20 V on the gate lead to two distinct states of WR and ER, respsectively, as shown overlapped with the memory hysteresis curve. IG from the P(VDF-TrFE) polymer was below ∼100 pA. b) Retention properties of WR and ER states recorded under VD = 1 V and VG = 0 V for 1000 s. Inset shows the ±20 V 1 s pulse for retention measurements. c) Current dynamics of our memory transistor in response to repetitive input voltage pulses under VD = 1 V. The inset figure shows the periodic pulse mode for WR/read/ER/read process.

MoS2-based ferroelectric FET due to the considerably reduced memory hysteresis window. For retention measurements, we applied a gate bias of 2 V according to the memory transfer characteristics of Figure 3a. The shortened window is attributed to some depolarization effects from the doublelayer MoS2 and also to the degraded S.S. behavior of the same MoS2 ferroelectric FET.[35] The depolarization mechanism is not perfectly clear but presumably explained. When the MoS2 small 2012, 8, No. 20, 3111–3115

Figure 3. a) The transfer curve of top-gate double-layer MoS2 transistor with P(VDF-TrFE) ferroelectric layer; VG sweep range = –20 to +20 V and VD = 1 V. Memory hysteresis window of the transistor appears to be ∼6 V. Short pulses of +20 and –20 V on the gate lead to two distinct states of WR and ER, respectlively. b) Retention properties of WR and ER states recorded under VD = 1 V, VG = 2 V for 1000 s. c) Current dynamics of our memory transistor in response to repetitive input voltage pulses under VD = 1 V. The inset figure shows the periodic pulse mode for WR/read/ ER/read process. (WR/ER ratio = ~20).

layer increases in number, its dielectric constant is changed (becomes larger) as reported by theory.[36] If it is larger than that of our ferroelectric polymer (κ = ~7),[25] the electric (E)field lines driven by the source-to-drain voltage (VDS) are not so much confined in the MoS2 nanosheet but deviate to the ferroelectric polymer which may now hardly provide its highκ-induced dielectric screening effects.[34] During ferroelectric operation in our FET, such deviating E-field lines disturb the semi-permanent dipoles in ferroelectric layer, causing some depolarization effects. Dynamic WR/ER behavior was well

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Table 1. Electrical properties of top-gate-controlled MoS2 memory FET with P(VDF-TrFE). Number of layers

observed in Figure 3c, but its ratio was reduced to ∼20 which is smaller than that of the static retention (∼100). The S.S. degradation and memory window reduction in ferroelectric memory transistor becomes even more serious with the layer thickness increase. According to the results from our device with ∼(3–4)-layer MoS2 channel in Figure 4a, its S.S. value was as large as ∼2.7 V/dec and the memory window was only 3 V. The mobility was estimated to be 21 cm2/(V·s) and the on/off ID ratio was ∼103. The WR/ER ratio of the device with ∼(3–4)-layer MoS2 was less than 5 as observed from the memory hysteresis curve (Figure 4a) and the dynamic retention curve (Figure 4b). In order to summarize all the properties of our nanosheetbased ferroelectric memory devices in a more organized way, we prepared Table 1 for the three FETs containing different numbers of MoS2 layers. In addition to the information summary, the minimum electron charge densities in the nanosheet channels of memory FETs could be estimated with the maximum mobility and on-current values of MoS2 nanosheet FETs when we use the following equation; nqμ·E = J, where n is electron density per unit volume, q electronic charge, μ

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WR/ER ratio

Memory window [V]

1

220

0.3

5 × 10−5

∼5 × 103

14

2

34

2

1 × 10−5

<102

6

5

3

3

Figure 4. a) The transfer curve of top-gate triple-layer MoS2 transistor with P(VDF-TrFE) ferroelectric layer; VG sweep range = –20 to +20 V and VD = 1 V. Memory hysteresis window of the transistor appears to be only ∼3 V. Short pulses of +20 and –20 V on the gate barely lead to the WR and ER states. b) Current dynamics of our memory transistor in response to repetitive input voltage pulses under VD = 1 V. The inset figure shows the periodic pulse mode for WR/read/ER/read process. (WR/ER ratio = ∼3).

S.S. On current Maximum μlin [cm2/(V·s)] [V/decade] [A]@ VD = 1 V

21

2.7

−6

7 × 10

maximum mobility, E electric field between source and drain, and J current density. For the single-layer MoS2 nanosheet FET, the minimum electron charge density in the on-state was about ∼1.0 × 1012/cm2 (or ∼1.5 × 1019/cm3) by considering the single-layer MoS2 thickness (t = 0.65 nm), E-field as VD/L, and W/L ratio (=1). The charge density is about the same as that of the graphene layer.[37] Even though our MoS2 FET with organic P(VDF-TrFE) top layer is the first and principlebased demonstration of nanosheet ferroelectric memory FET, it may not be as practical as with inorganic crystalline ferroelectrics, which would enable low-voltage high-speed dipole switching. So, our initial work may suggest future memory FET research adopting fast-switching inorganic ferroelectrics, which are possibly integrated on nanosheets by a physical/ chemical deposition method. In conclusion, we for the first time demonstrated a topgate nonvolatile memory transistor with a single-layered MoS2 nanosheet adopting a ferroelectric polymer, P(VDFTrFE). Our nonvolatile memory transistor exhibited a high mobility of 220 cm2/(V·s), high on/off ID ratio of 105, and good retention properties in both static and dynamic switching, maintaining a high program/erase ratio of ∼5 × 103. Although the increased layer number of MoS2 reduces the memory window and nano-FET performance, the excellent device characteristics inherent in single-layer MoS2 should pave a way for future nanosheet applications in nonvolatile memory transistors.

Experimental Section Exfoliation and Characterization of MoS2: We prepared singleand few-layer MoS2 nanosheets from bulk MoS2 (SPI supplies, natural molybdenite) on 285 nm SiO2 on p++-doped silicon substrate by using a standard micromechanical exfoliation scotchtape method. Our MoS2 nanosheet flakes were as large as ∼10 μm on one side, so that a long 5 μm channel was possible in our device (W/L ratio was ∼1). We have previously found that the layer number of the MoS2 nanosheet can be conjectured by optical microscope observations while it is then clearly identified by Raman spectroscopy. Top-Gate Memory Nanosheet FET Fabrication: We made source (S) and drain (D) electrodes using photolithography and liftoff processes. First, we coated the lift-off layer (LOL 2000: Micro Chem) and photoresist (PR) layers by spin-casting. Then the substrate was exposed to ultraviolet (UV) light with a photo-mask for our S/D electrode pattern. After developing patterns, we deposited a 50-nm-thick Au for S/D electrodes using a DC sputtering system. The lift-off process was done with acetone and LOL remover.

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Figure S1 (SI) shows the optical microscope images of three different MoS2 flakes taken before and after Au contact. As shown in the figure, the MoS2 nanosheet channels have kept their original positions during the whole photolithography processes. In order to fabricate a ferroelectric gate dielectric layer, 200-nm-thick film of P(VDF/TrFE) 75/25 mol% copolymer (6 wt% cyclohexanone solutions) was coated by spin-casting and subsequent quenching by blowing N2 gas (99.9% purity) at room temperature (RT). The spincasting needed vacuum-oven curing at 160 °C for 2 h. Because P(VDF/TrFE) is very weak in typical organic solvent, it is hard to pattern the ferroelectric organic for top-gate device structure through the lift-off process. We found, however, that P(VDF/TrFE) is strongly insoluble in methanol while PR (SPR 3612: Micro Chem) has a good solubility in methanol as well as in acetone. We could thus successfully pattern the Al top-gate electrodes on the P(VDF-TrFE) layer through photolithography and lift-off processes using methanol. Electrical Characterization: The electrical properties of the 200-nm-thick P(VDF-TrFE) ferroelectric layers, such as capacitance– voltage (C–V) and remnant charge density–electric field (Pr–E) characteristics were obtained using a capacitance meter (HP 4284 LCR meter, Agilent Technologies, 1 MHz) and a Sawyer-Tower circuit with 300-mm-sized Al dot/ferroelectric/indium-tin-oxide structures in the dark and in air (relative humidity 40%). All current–voltage (I–V) and retention properties of our MoS2 transistors were measured using a semiconductor parameter analyzer (HP 4155C, Agilent Technologies), while dynamic memory retention measurements needed a function generator (Tektronix AFG 3202B).

Supporting Information Supporting Information is available from the Wiley Online Library or from the author.

Acknowledgements The authors acknowledge the financial support from NRF (NRL program, No. 2012-0000126), BK21 Project. HSL acknowledges the tuition support from the LOTTE fellowship. SR acknowledges the financial support from NRF (program No. 2011-0031629).

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Received: April 6, 2012 Revised: May 22, 2012 Published online: July 31, 2012

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