IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 32, NO. 6, JUNE 1997

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A 1-V High-Speed MTCMOS Circuit Scheme for Power-Down Application Circuits Satoshi Shigematsu, Member, IEEE, Shin’ichiro Mutoh, Member, IEEE, Yasuyuki Matsuya, Member, IEEE, Yasuyuki Tanabe, and Junzo Yamada, Member, IEEE

Abstract— This paper proposes a new multithreshold-voltage CMOS circuit (MTCMOS) concept aimed at achieving highspeed, ultralow-power large-scale integrators (LSI’s) for batterydriven portable equipment. The “balloon” circuit scheme based on this concept preserves data during the power-down period in which the power supply to the circuit is cut off in order to reduce the standby power. Low-power, high-speed performance is achieved by the small preserving circuit which can be separated from the critical path of the logic circuit. This preserving circuit is not only three times faster than a conventional MTCMOS one, but it consumes half the power and takes up half the area. Using this scheme for an LSI chip, 20-MHz operation at 1.0 V and only a few nA standby current was achieved with 0.5-m CMOS technology. Moreover, this scheme is effective for high-speed and low-power operation in quarter-micrometer and finer devices. Index Terms—Circuit design, circuit optimization, CMOS digital integrated circuits, flip-flops, low-power circuit, low-voltage CMOS.

I. INTRODUCTION

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ECENTLY, there has been an increasing demand for portable, battery-operated devices like cellular phones and notebook computers. Low-power circuit technology is essential to miniaturize these devices and extend battery life. Lowering the power supply voltage is the most effective way to achieve low-power operation and miniaturize portable equipment [1]–[6]. On the process side, the subquarter-micrometer and even finer devices are being studied and developed to achieve high-speed and low-power largescale integrators (LSI’s). In these devices, the power supply voltage has to be reduced, because of their low source-drain breakdown voltage. Therefore, in these future devices, the threshold voltage will certainly be reduced because highspeed operation is also needed at a low power supply voltage. Although lowering the threshold voltage reduces the delay, at the same time, it also exponentially increases the standby leakage current due to the subthreshold characteristics. In recent mobile equipment, many power-down techniques have been introduced to reduce power consumption. In these techniques, the clock is slowed or stopped in order to lower the frequency of operation when the system is not in use. However, these techniques are not sufficient in low- LSI’s Manuscript received March 12, 1996; revised November 25, 1996. S. Shigematsu, S. Mutoh, Y. Matsuya, and Y. Tanabe are with the HighSpeed Integrated Circuits Laboratory, NTT System Electronics Laboratories, Kanagawa 243-01, Japan. J. Yamada is with the Technology Department, NTT, Tokyo, Japan. Publisher Item Identifier S 0018-9200(97)03833-X.

because power is wasted by the standby leakage current even if the circuit operation is stopped. Therefore, we have developed a multithreshold-voltage CMOS circuit (MTCMOS) technology [1] to lower threshold voltage and reduce standby leakage current by using a powerdown technique. This power-down technique uses highMOS transistors to cut off leakage paths because of their low leakage current. In the sleep mode for power-down, however, data in the circuit is lost because the power supply for the logic circuits is cut off by these high- MOS transistors. The data in the circuit should be preserved during the sleep mode to guarantee continuous circuit operation. The conventional MTCMOS D-flip/flop (DFF) [1] has been proposed to solve this problem, but it creates a bottleneck during high-speed operation because high- MOS transistors are in its critical path for preserving data. This paper proposes a new circuit scheme to preserve data in the sleep mode for a smart power-down technique to achieve lower power, higher speed MTCMOS LSI’s [8]. In this scheme, the data is preserved in a small additional data preserving circuit that is separated from the critical path in the active mode. This scheme achieves 20-MHz operation for an LSI at 1.0 V and only a few nA of standby leakage current with 0.5- m CMOS technology. The features of the MTCMOS circuit are discussed in the next section. Section III presents the new circuit schemes for preserving data in the sleep mode. Section IV discusses the standard cells of the new circuits. Finally, experimental results are shown in Section V. II. MTCMOS CIRCUITS We developed MTCMOS circuit technology to achieve a lower threshold voltage and a smaller standby leakage current. MTCMOS has two main features. First, it employs MOS transistors with both high and low threshold voltages on the same chip. Fig. 1 illustrates the basic circuit scheme. The logic gates are composed of low- MOS transistors. They are not connected directly to the power supply line or , but rather to a virtual power line or . These power lines are linked by high- MOS transistor Q and Q’. These transistors are called power transistors. The second feature is that there are two operating modes: active and sleep. In the active mode, the power transistors are on, which means that and function as and , respectively. Consequently, the low- logic gates function normally and at high-speed. On the other hand, in the sleep mode, the power transistors are off, so

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Fig. 1. Schematic circuit diagram of MTCMOS.

and float. Since Q has a high and thus a low leakage current, leakage from the low- MOS transistors is almost completely suppressed. As a result, the standby leakage current is dramatically reduced by the sleep mode. Thus, this technology achieves high-speed and low-standby-power circuits in low-voltage LSI’s. Recently, there are various power management techniques for low-power LSI’s. These power management techniques employ “sleep operation” to reduce the power consumption. In an MTCMOS circuit, the circuit states are lost in the sleep mode because the virtual power supply lines connected to the logic circuits float in order to cut off the standby leakage current. This is not a matter for the LSI which uses a kind of sleep operation. There is the conventional sleep operation in which the power supply for the LSI is cut off when the LSI is not in use. This sleep operation is produced by a conventional power management technique as a long-period sleep such as “power down” in notebook computers and a “waiting call” in cellular phones. It is no problem to apply the MTCMOS scheme to an LSI using such sleep operation because it is allowed that the circuit states are lost in this sleep operation. On the other hand, there is also the other sleep operation which only stops the operation of the logic circuit when the LSI is not in use. Some the low-power LSI’s in portable equipment use this sleep operation during an intermittent operation such as waiting input from a keyboard or communicating through a slow interface. These LSI’s can restart the operation without resuming operations because the common registers and the pipeline registers also preserve data during the sleep period. So the circuit modes, sleep or active, can be changed quickly and frequently. Many low-power LSI’s achieve the low power consumption by using this sleep operation. However, it is difficult to apply MTCMOS scheme to these LSI’s since data in the MTCMOS circuit are lost in the sleep period. In order to apply MTCMOS to any lowpower LSI’s, the most important issue is to preserve data in the circuit during the sleep period. Therefore, we developed an MTCMOS latch circuit for preserving data in the sleep mode [1]. Fig. 2 shows the circuit diagram of the MTCMOS latch circuit. A latch path , which consists of high- MOS inverters powered directly and , can preserve data during the sleep by period. Transmission gate TG1 in the critical path is composed of high- transistors to cut off the standby leakage current

Fig. 2. Circuit diagram of a conventional MTCMOS latch circuit.

path. High- power transistors for sleep control, Q1–Q4, are connected to low- data-path inverters independently to cut off the standby leakage path. If data-path inverters are connected to common virtual power supply lines directly, the standby-leakage-current path between and or and will be created in the sleep mode [1]. In this circuit scheme, these data-path inverters cannot get the speed-up effect of the capacitance of the virtual power lines. Thus, in order to operate the MTCMOS latch as fast as the ordinary latch, the power transistors Q1–Q4 must be enlarged. This circuit successfully preserves data in the sleep mode, but it creates a bottleneck during high-speed operation because there are high- MOS transistors (TG1) in the critical path. In addition, since the high- power transistors Q1–Q4 must be large enough to supply power to the data-path inverters, this circuit not only takes up a larger area than an ordinary latch circuit, but it also wastes power. Besides this circuit, the data-preserving circuit scheme has been proposed [7]. It preserves data in the low- circuit by using the level holder circuit during the sleep period. However, in this scheme, as in the MTCMOS latch circuit, highpower transistors also have to be connected to low- datapath inverters independently to cut off the standby leakage path. This also increases the delay and in order to suppress this delay, high- power transistors have to be enlarged over eight times larger than low- transistors. Therefore, a novel data-preserving circuit scheme is needed that uses little power to preserve data in the sleep mode, yet still allows high-speed operation in the active mode, and uses a small area. Consequently, we devised a new 1-V high-speed MTCMOS circuit scheme for preserving data in the sleep mode. III. NEW CIRCUIT SCHEME Fig. 3 shows the concept of the new MTCMOS circuit for preserving data during the sleep period. It involves the use of a memory circuit, which is always powered, and a switch. We call the memory circuit “a balloon circuit” because of its shape and because we “blow up” the memory with data at the

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(b)

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Fig. 3. Concept of new MTCMOS data-preserving circuit: (a) circuit diagram, (b) operation in sleep mode, (c) read/write data, and (d) operation in active mode.

beginning of the sleep mode to preserve it and let the data out at the end to restore it. This circuit is connected to node A of the MTCMOS logic circuit. This scheme has two states according to the circuit modes; sleep and active. In the sleep mode, the balloon circuit preserves data using the memory circuit and a leakage current from the memory circuit to the logic circuit is cut off by the switch [Fig. 3(b)]. In the active mode, the balloon circuit does not add to the load at the node because it is separated from the node by the switch [Fig. 3(d)]. During the transitional period between these two states, the switch becomes on-state to read data from the node or restore data to the node [Fig. 3(c)]. A. Balloon Circuit Fig. 4(a) shows a schematic of the balloon circuit. The memory circuit contains two inverters and a transmission gate (TG). The inverters, which are composed of hightransistors, get power directly from the power supply. The switch (TG2) is a high- TG that separates the memory circuit from the node. TG1 and TG3 are low- TG’s that are used for reading and writing to the memory circuit. These TG’s are controlled by signals B1 and B2. Fig. 4(b) shows these signals. Signal SL is a sleep signal which controls highpower transistors. In the sleep mode, SL is low ( ) level, and in the active mode, SL is high ( ) level. There are four periods in the logic circuits: active, sleep, sleep-in, and sleep-out, for the balloon circuit. The “sleep-in” and “sleepout” periods are transitional periods between sleep and active periods. In the sleep-in period, the balloon circuit reads data from the node. In the sleep-out period, the balloon circuit restores data to the node. This balloon circuit accomplishes these operations through switching the TG’s according to these periods. The switch TG2 is composed of high- transistors and controlled by signal B1. This TG becomes on-state to connect the balloon circuit with node A during sleep-in and sleep-out periods. During the sleep period, TG2 is off-state. If the TG2 is on-state in this time, It is probable that the current paths between the balloon and the other balloon are created through the low- circuits. This wastes a large amount of the standby power. Therefore, TG2 is turned off in order to cut off the standby current from the balloon memory circuit by the low

(a)

(b) Fig. 4. MTCMOS balloon circuit. (a) Schematic circuit diagram of the balloon circuit. (b) Sequence of the control signals for the balloon circuit.

leakage current of high- transistor. This TG is also off-state during the active period to suppress the load of node A to which the balloon circuit is connected. TG1 is composed of low- transistors and controlled by signal B2. This TG is off-state during the sleep-in period in which the balloon circuit reads data from node A. This prevents the balloon circuit destructing data in node A when TG2 becomes on-state to read data. TG1 is also off-state during the active period. During this time, node N in the balloon memory circuit floats, because TG1 and TG2 are offstate. One solution to avoid this problem is to turn TG1 on during the active period. This increases the number of control signals for the balloon circuit and the area overhead of the balloon circuit. Here we solve this problem by applying lowtransistors to TG1, because their leakage current prevents node N from floating. Therefore, the number of control signals can be suppressed to two, and the control circuit for the balloon circuit can be designed simply as only two small inverters. The overhead of the balloon circuit can be reduced. TG3 is inserted between node A, to which the balloon circuit is connected, and the output of the circuit which drives node A for prevention of conflict between these circuits. This TG is off-state to help writing during the sleep-out period in which the balloon memory circuit writes data to node A. In Fig. 4(a), node B is an output of the circuit, such as inverter I1, which drives node A. In the MTCMOS circuit, it is probable that the data in node B and the data in the balloon memory circuit are different when the sleep period is over and the lowcircuits resume power, because any node in the low- circuits is floating in the sleep period. Hence, the data in the balloon memory circuit must be destroyed when TG2 is turned on to restore data in the sleep-out period. In order to solve this

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Fig. 5. Operation of the balloon circuit.

Fig. 6. Schematic circuit diagram of a typical CMOS D-flip/flop circuit.

problem, TG3 becomes off-state to separate node A from node B during the sleep-out period. After all the balloon circuits restore data to the nodes, data in node B resumes and becomes the same as data in the balloon memory circuit. Since TG3 is turned on after all nodes resume, data in the balloon memory circuit is not destroyed. Besides, if node A has large capacitance, such as the clock line, there is a possibility that data in the balloon circuit is destroyed by the charge sharing in the sleep-out period. Basically, the balloon circuit is connected to the node which has a small capacitance, such as the node in the cell or the input node of the clock driver. However, if the balloon circuit has to be connected to the node which has large capacitance, we locate node A near the circuit which assigns node A for input, such as inverter I2 in Fig. 4(a), and insert TG3 near this node A. Thus, the capacitance of node A can be reduced. This prevents data in the balloon from destruction caused by the charge sharing. transistors and is on-state TG3 is composed of lowduring the active period. This can avoid reducing the speed performance of low- circuit during the active period. Fig. 5 shows the operation of the balloon circuit, which is explained as follows. • In the active period, the balloon circuit is separated from the node by TG2. This keeps the load down. In this period, the balloon circuit does not operate. • During the sleep-in period, which is a transition period from the active period to the sleep period, TG2 is turned on so that the balloon circuit can read data from the node. • In the sleep period, the memory just holds the data. TG2 cuts off the leakage current path from the memory circuit. In this period, the state in the balloon circuit does not change. • During the sleep-out period, which is a transition period from the sleep period to the active period, the balloon circuit writes the data back to the node, thus restoring the node to its previous state. This operation enables active-mode operation to resume smoothly. The state of the balloon circuit only changes during the transitional periods between sleep and active periods. Since the balloon memory circuit and the switch do not operate in the active period, the balloon circuit does not become a bottleneck during high-speed operation of the low- application circuit.

Thus, the balloon circuit does not need to be fast. This means that it can be designed with a high- and the smallest MOS transistors, thereby allowing a lower standby power and a smaller increase in area. B. Clock-Free Balloon DFF A DFF circuit is generally used for holding data. A typical CMOS DFF circuit is shown in Fig. 6. We call it “a pure DFF.” When the clock signal CKin is high level, the data is held in the master latch, and when the clock signal is low level, the data is held in the slave latch. In the MTCMOS circuit, a pure DFF cannot preserve data during the sleep period because the power supplies and , which connect to the inverters, float. This is where our new circuit scheme comes in. Fig. 7 shows a new type of DFF consisting of a pure DFF and the balloon circuits. It is called “a clock-free balloon DFF.” This balloon DFF has two balloon circuits, one is used to preserve data which the DFF holds, and the other preserves the state of clock signal CKin during the sleep period. In the DFF circuit, it depends on the state of clock which latch holds data, master or slave. If the state of the clock for this DFF cannot be fixed at the same state in any sleep-in period, for instance in the circuit which uses the gated clock, the balloon circuit has to be able to preserve the data in the master and slave latches according to the state of the clock. Thus, in this balloon DFF, the balloon circuit which preserves data of the DFF is connected to nodes A and B, and the other balloon circuit preserves the state of the clock, which is distributed to the DFF, in order to set the state of the clock in the sleep-out period to the same state as in the sleep-in period. As a result, this circuit has two balloon circuits. In this balloon DFF, the transmission gates TG1, TG2a, TG2b, TG3a, and TG3b are controlled by signals B1 and B2 in the same way as the balloon circuit. These control signals B1 and B2 are generated from signal SL. TG3a and TG3b help to restore data to node A or B in the sleep-out period. For instance, if clock CKin is low, this DFF holds data in the slave latch. In the sleep-in period, if the clock state is low, the balloon circuit reads data from node B, and the clock state is also preserved as a low state by the balloon in the clock circuit. In the sleep-out period, TG4 becomes off-state and TG5 becomes on-state because the clock for DFF is restored

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(b) Fig. 8. Clock circuit in the synchronous system. (a) Schematic of the clock holding circuit. (b) Sequence of the control signals and clock signal.

Fig. 7. A balloon circuit applied to a DFF circuit (clock-free type).

as a low state by the balloon circuit. During this time, if TG3b is not inserted, it is probable that the data which is preserved in the balloon memory will be destroyed by inverter I1. Therefore, TG3a and TG3b, which become off-state in the sleep-out period, are inserted to avoid this problem in the same way as TG3 in Fig. 4(a). Besides, during the active period, TG3a and TG3b do not increase the delay in the DFF operation because these TG’s are not inserted into the critical path of the DFF. C. Clock-Dependent Balloon DFF In synchronous systems such as digital signal processors and microprocessorss which use many pipeline registers, most DFF’s use a common clock. In such systems, the clock-hold circuit, as shown in Fig. 8(a), can fix the clock for each DFF as the same state during the sleep-in and the sleep-out period. Signal SL2 is used to fix the states of the distributed clock signals, and it is presented as one in Fig. 8(b). When the mode of the low- circuit moves to the sleep mode, SL2 becomes high level before the sleep-in period. During the sleep-in period, node A, which is the output of the clockhold circuit in Fig. 8(a), is fixed at low level, and the clock for the DFF’s which are in the low- logic circuit are also fixed. For instance, the clocks for DFF F1 and F2 are fixed at low and high states, respectively. In the same manner as the above, when the mode of the low- circuit moves to the active mode, SL2 keeps a high level until the sleep-out period is over. During the sleep-out period, node A is fixed at low level, and the clocks for the DFF’s are fixed at the same state which was fixed during the sleep-in period.

In these systems, DFF’s in the logic circuit do not have to preserve the state of the clock during the sleep period because the state of clock for the DFF can be fixed at the same state in any sleep-in and sleep-out period. Consequently, the other balloon DFF circuit, which has a single balloon circuit to preserve data, is composed. It is called “a clock-dependent balloon DFF.” This balloon DFF circuit is shown in Fig. 9. This balloon DFF can be applied to the DFF in which the state of the clock is fixed at a low level during the sleep-in and sleep-out period, such as F1 in Fig. 8(a). In this circuit, the balloon circuit is connected to node B and only preserves data which is held in the slave latch. In the same way, the other balloon DFF circuit has been also composed. This balloon DFF can be applied to the DFF, in which the state of the clock is fixed at a high level during the sleep-in and sleep-out periods, such as F2 in Fig. 8(a). In this circuit, the balloon circuit is connected to node A and only preserves data which is held in the master latch. When the low- logic circuit block is designed, these balloon DFF’s are chosen according to the state of the clock during the sleep-in and sleep-out periods. These balloon DFF’s have only one balloon circuit because it is not necessary to preserve the state of the clock. Therefore, these balloon DFF’s can suppress the increase in the circuit size and lower the power to preserve data during the sleep period. IV. STANDARD CELL

FOR

BALLOON

In order to design low-voltage LSI’s practically, it is important that conventional CAD tools can be applied for design. For this requirement, the balloon cell and the balloon DFF cells are designed to be used in the standard-cell-based design in which conventional CAD tools can be used easily. The

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TABLE I DEVICE TECHNOLOGY

Fig. 9. A balloon circuit applied to a DFF circuit (clock-dependent type).

MTCMOS standard cells have been designed [1]. They are made from the conventional standard cells, which are used and adding at a supply voltage of 3.3 V, by lowering the the virtual power lines. Moreover, these cells have the control signal lines for B1 and B2 which control the balloon circuit. The balloon circuit cell is designed based on the balloon circuit scheme as shown in Fig. 4(a). This cell consists of two high- inverters and a low- TG for the memory circuit, a high- TG for the switch circuit, and two high- inverters for generation of control signals. This cell contains 12 transistors. The state of the balloon circuit cell only changes during the transitional periods between sleep and active modes. Since the balloon circuit does not operate in the active mode, it does not need to be fast and can be designed with the smallest MOS transistors. Therefore, two transistors can be placed in the area for one conventional transistor. This keeps the area penalty small and the standby power low. As a result, the balloon cell has been designed as small as a four-input NAND cell which contains eight transistors. The MTCMOS data preserving circuit cell, which can preserve data during the sleep period, is realized by applying the above balloon cell to the MTCMOS cell. In order to make this data preserving cell, the balloon cell is only placed next to an MTCMOS cell and they are connected with one line. Since the control signal lines for B1 and B2 pass all MTCMOS standard cells, the balloon cell can get signals from these lines. Thus, the CAD tools do not have to route signals B1 and B2 to the balloon cells, and they do not have to change the net list which has been designed for the conventional circuit. Therefore, it is possible to realize low-voltage LSI’s which can preserve data during the sleep period, using conventional resources such as CAD tools and net-lists easily. We designed a balloon DFF cell based on this idea. The clock-free balloon DFF cell, which is designed based on the circuit scheme as shown in Fig. 7, and the clockdependent balloon DFF cell, which is designed based on the

circuit scheme as shown in Fig. 9, are realized by using the balloon cells. The area of the clock-free balloon DFF is 83% of one of the conventional MTCMOS DFF cells [1], and the area of the clock-dependent balloon DFF is 55% of one. The area of the clock-dependent balloon DFF is 143% of the area of the pure DFF cell which loses data during the sleep period, and the area of the conventional MTCMOS DFF cell is 257% of one. Thus, the clock-dependent balloon DFF is much smaller than a conventional one, and only slightly bigger than a pure DFF. The area overhead of improvement to preserve data can be decreased from 157% by the conventional MTCMOS DFF to 43% by the balloon DFF. One area penalty of the MTCMOS circuit is enlargement of the cell caused by improvement to preserve data during the sleep period. This balloon scheme can make this area penalty small with keeping the function of preserving data. V. EXPERIMENTAL RESULTS To evaluate the effectiveness of the balloon circuit scheme, we designed some test chips. These test chips were fabricated using a 0.5- m double-metal MTCMOS process. The device parameters and characteristics are summarized in Table I. The gate length of the low- MOSFET is 0.65 m. This is 0.1 m longer than that of the high- MOSFET, in order to suppress variations in the due to short-channel effects. The gate ˚ for both types of MOSFET’s. The oxide thickness is 110 A low- ’s are 0.25 V for n-channel and 0.35 V for p-channel MOSFET’s. All experiments were carried out at a temperature 25 C. A. Balloon Cell The first test chip contained a balloon circuit and a latch circuit. This chip was fabricated using a 0.5- m double-metal MTCMOS process. It was designed to measure read/write time and skew immunity of the balloon circuit. Fig. 10 shows the dependence on supply voltage of the minimum time to read data from the node and write data to the node. The balloon cell needed only 15 ns to read and write at a supply voltage of 1 V. The balloon circuit might suffer from skew between signals B1 and B2. Two types of skew might occur between B1 and B2. One type arises when signal B2 is late. This means that the sleep-in and sleep-out periods become longer. It was experimentally confirmed that the balloon circuit can operate even when B2 is late by several s. The other type is when signal B1 is late. This means that the sleep-in and sleep-out periods are shortened. The experimental results show that the balloon circuit can operate if sleep-in

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Fig. 10.

Measured access time for the balloon circuit versus supply voltage.

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and sleep-out periods are longer than the minimum read/write time. Therefore, if skew caused by B1 being late can be ignored. Thus, we confirmed that skew between B1 and B2 can be ignored. From the above results, the minimum read/write time of the balloon circuit is shown to be 15 ns. If a maximum skew between B1 and B2 is measured, the most suitable time of the sleep-in and sleep-out period can be decided to be over the sum of the maximum skew time and the minimum read/write time. (b)

B. Balloon DFF The second test chip contained 1/8 frequency dividers, each of which employed DFF cells. This chip was fabricated using a 0.5- m double-metal MTCMOS process. It has four dividers, composed, respectively, of clock-free balloon DFF’s, clockdependent balloon DFF’s, conventional MTCMOS DFF’s, and pure DFF’s. Fig. 11(a) shows measured maximum operating frequency versus supply voltage for the dividers. Clearly, the balloon DFF’s are much faster than the conventional MTCMOS type. In particular, clock-dependent balloon DFF’s are almost as fast as pure DFF’s. We achieved a speed of 200 MHz at a supply voltage of 1 V. Fig. 11(b) shows how measured power consumption varies with supply voltage. Balloon DFF’s use much less power than the conventional MTCMOS type, and clock-dependent balloon DFF’s in particular use about the same amount of power as pure DFF’s. This is because they slightly increase the internal load on the critical path. In the sleep mode, the leakage current of a balloon DFF is as low as that of a high- DFF. These results show that there is only a negligible speed and power penalty for balloon DFF’s. Table II summarizes the measured characteristics of the three types of DFF’s. The pure DFF cannot preserve data in the sleep mode. All of them can operate at a supply voltage above 0.8 V. In a frequency divider, the maximum operating speed of a clock-dependent balloon DFF is three times that of a conventional MTCMOS DFF, and it uses about half the power. In addition, its cell is only half as wide as the conventional MTCMOS type.

Fig. 11. Measurement results for 0.5-m DFF circuits; (a) maximum input frequency versus supply voltage and (b) power consumption versus supply voltage. TABLE II CHARACTERISTICS OF DFF’s

C. 8-K-Gate Communication LSI The third test chip was a cell-based communication LSI containing about 8 K gates. This chip was fabricated using a 0.5- m double-metal MTCMOS process. Fig. 12 shows micrographs of the two types; one containing conventional MTCMOS DFF’s and the other balloon DFF’s. In the chip with balloon DFF’s, we applied clock-dependent balloon DFF’s to DFF’s in which the clock can be fixed and applied clock-free balloon DFF’s to the other DFF’s. The DFF cells make up 10% of all the cells. The core area of the LSI with balloon DFF’s is 73% of the size of the LSI with conventional DFF’s. This shows that the area overhead to use the balloon circuit is very small.

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FEATURES

TABLE III COMMUNICATION LSI

OF THE

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(b) Fig. 12. Micrograph of communication LSI’s (a) with conventional DFF (8.9 mm2 ) and (b) with balloon DFF (6.5 mm2 ).

Table III lists the specifications of an LSI with balloon DFF’s. The core is 6.5 mm . The chip operates at a frequency of 20 MHz at a supply voltage of 1 V. The sleep mode functions normally above a supply voltage of 0.8 V. The time needed to read and write to the balloon circuit is under 30 ns. The power dissipation is 0.24 mW/MHz. The leakage current is 50 A in the active mode and only 1 nA in the sleep mode. D. Application to 0.25- m MTCMOS The fourth test chip contained 1/8 frequency dividers, all of which used DFF cells. This chip was fabricated using a 0.25- m double-metal MTCMOS process. The circuits in this chip are the same as in the chip described in the experiment in Section V-B. Fig. 13(a) shows the measured maximum operation frequency versus supply voltage for the dividers. The maximum frequency of the balloon DFF at 1 V is 760 MHz. This is four times the speed of the 0.5- m balloon DFF. We achieved GHz operation at a supply voltage of under 1.2 V. Fig. 13(b) shows how measured subthreshold leakage current varies with supply voltage. In the sleep mode, the leakage

(b) Fig. 13. Measurement results for 0.25-m DFF circuits; (a) maximum input frequency versus supply voltage and (b) standby leakage current versus supply voltage.

current of the balloon DFF is as small as that of a high- pure DFF. It is 1/140 of the leakage current in the active mode at a supply voltage of 1 V. These results show that the balloon circuit and MTCMOS technology are also effective for high-speed and low-power operation in sub-quarter-micrometer and finer devices. VI. CONCLUSION We have developed a new 1-V high-speed MTCMOS circuit scheme for power-down application circuits. The main feature is a small, fast, low-power balloon circuit for preserving

SHIGEMATSU et al.: 1-V HIGH-SPEED MTCMOS CIRCUIT SCHEME

data. A balloon DFF is not only three times faster than a conventional MTCMOS DFF, but it consumes half the power and takes up half the area. This is a very efficient circuit scheme for high-performance power-down application circuits using MTCMOS technology. Moreover, it is effective for highspeed and low-power operation in sub-quarter-micrometer and finer devices. Consequently, this scheme brings smart power management to LSI’s. ACKNOWLEDGMENT The authors would like to thank S. Horiguchi, H. Fukuda, and T. Douseki for their support and comments. REFERENCES [1] S. Mutoh, T. Douseki, Y. Matsuya, T. Aoki, S. Shigematsu, and J. Yamada, “1-V power supply high-speed digital circuit technology with multi threshold-voltage CMOS,” IEEE J. Solid-State Circuits, vol. 30, pp. 847–854, Aug. 1995. [2] M. Horiguchi, T. Sakata, and K. Itoh, “Switched-source-impedance CMOS circuit for low standby subthreshold current giga-scale LSI’s,” IEEE J. Solid-State Circuits, vol. 28, pp. 1131–1135, Nov. 1993. [3] D. Takashima, S. Watanabe, H. Nakano, Y. Oowaki, K. Ohuchi, and H. Tango, “Standby/active mode logic for sub-1-V operating ULSI memory,” IEEE J. Solid-State Circuits, vol. 29, pp. 441–447, Apr. 1994. [4] J. Burr, and J. Shott, “A 200-mV self-testing encoder/decoder using Stanford ultra-low-power CMOS,” in ISSCC Dig. Tech. Papers, Feb. 1994, pp. 84–85. [5] A. P. Chandrakasan, A. Burstein, and R. W. Brodersen, “A lowpower chipset for portable multimedia I/O terminal,” IEEE J. Solid-State Circuits, vol. 29, pp. 1415–1428, Dec. 1994. [6] K. Seta, H. Hara, T. Kuroda, M. Kakumu, and T. Sakurai, “50% activepower saving without speed degradation using standby power reduction (SPR) circuit,” in ISSCC Dig. Tech. Papers, Feb. 1995, pp. 318–319. [7] T. Sakata, K. Itoh, and M. Horiguchi, “Subthreshold-current reduction circuits for multi-gigabit DRAM’s,” IEEE J. Solid-State Circuits, vol. 29, pp. 761–769, July 1994. [8] S. Shigematsu, S. Mutoh, Y. Matsuya, and J. Yamada, “A 1-V highspeed MTCMOS circuit scheme for power-down applications,” in IEEE 1995 Symp. VLSI Circuits Dig. Tech. Papers, June 1995, pp. 125–126.

Satoshi Shigematsu (M’93) was born in Tokyo, Japan, on August 2, 1967. He received the B.S. and M.E. degrees in system engineering from Tokyo Denki University, Tokyo, Japan, in 1990 and 1992, respectively. In 1992 he joined Nippon Telegraph and Telephone Corporation (NTT), Tokyo, Japan. Since 1992 he has been engaged in the research and development of low-voltage, low-power CMOS circuits. He is now in the High-Speed Integrated Circuits Laboratory, NTT System Electronics Laboratories, Kanagawa, Japan. Mr. Shigematsu is a member of the Institute of Electronic, Information and Communication Engineers of Japan and the Information Processing Society of Japan.

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Shin’ichiro Mutoh (M’93) was born in Tokyo, Japan, on October 12, 1963. He received the B.E. and M.E. degrees in electronic engineering from Chiba University, Chiba, Japan, in 1986 and 1988, respectively. In 1988, he joined Nippon Telegraph and Telephone Corporation (NTT), Tokyo, Japan, where he was first engaged in research on ultra high-speed BiCMOS SRAM and low-power CMOS SRAM circuits. Then he has involved in the research and development of low-power and low-voltage digital circuit technologies, especially multiple-threshold-voltage CMOS (MTCMOS) circuits. He is now in the High-Speed Integrated Circuits Laboratory, NTT System Electronics Laboratories, Kanagawa, Japan. Mr. Mutoh is a member of the Institute of Electronic, Information and Communication Engineers of Japan.

Yasuyuki Matsuya (M’88) was born in Aomori, Japan, on February 14, 1956. He received the B.E. and Ph.D. degrees in electronic engineering from Iwate University, Iwate, Japan, in 1978, and Tokyo Institute University, Tokyo, Japan, in 1996, respectively. He joined the NTT Electrical Communications Laboratories in 1978. He has been engaged in the research and design of high-resolution and audio A/D and D/A converters. His current research interest is in low voltage supply LSI circuit technology and A/D conversion technology with NTT System Electronics Laboratories, Atsugi, Japan. Dr. Matsuya is a member of IEEE and the Institute of Electronics, Information and Communication Engineers of Japan.

Yasuyuki Tanabe was born in Okayama, Japan, on June 17, 1953. He received the B.E. and M.E. degrees in electrical engineering from Waseda University, Tokyo, Japan in 1976 and 1978, respectively. Since joining the Musashino Electrical Communication Laboratories, NTT, Japan in 1978, he has been engaged in the research of silicon bipolar devices using polysilicon self-aligned process technology and the development of BiCMOS process for telecommunications ASIC LSI’s. His current research interests include low-power and high-speed integrated circuits design. He is presently a Senior Research Engineer at the NTT System Electronics Laboratories, Kanagawa, Japan. Mr. Tanabe is a member of the IEICE of Japan and the Japan Society of Applied Physics.

Junzo Yamada (M’86) was born in Nagoya, Japan, on April 3, 1951. He received the B.E. and the M.S. degrees in electronic engineering and the Ph.D. degree in computer science from Tokyo Institute of Technology, Tokyo, Japan, in 1974, 1976, and 1990, respectively. In 1976 he joined the Musashino Electrical Communications Laboratory, Nippon Telegraph and Telephone (NTT) Public Corporation, Tokyo, Japan, where he worked on the design and testing of fault tolerant DRAM. Since 1990, he has been engaged in research on 1-V CMOS circuit technology including memories and A/D converters as a Low-Voltage Integrated Circuits Research Group Leader in NTT LSI Laboratories. He is currently Senior Manager in Technology Department, NTT. Dr. Yamada is a member of the Institute of Electronic, Information and Communication Engineers of Japan.