A BIST Architecture for Sigma Delta ADC Testing Based on Embedded NOEB Self-Test and CORDIC Algorithm Nabil Chouba,

Laroussi Bouzaida1 DTCad-Engineering WTC, 38025 Grenoble, France [email protected]

STMicroelectronics, 2083 La Gazelle Ariana, Tunisia [email protected]

Abstract — This paper presents a Built In Self Test (BIST) technique for sigma delta ADC testing. The proposed solution consists in a mostly digital module, using a binary stream as test stimulus and sine wave fitting algorithm to estimate Signal-to-Noise and Distortion Ratio. Reference signal is generated using COordinate Rotation DIgital Computer CORDIC algorithm. The same structure is used for offset and amplitude adjustment. We are targeting a significant area overhead reduction by proposing a modified Number of Effective Bits NOEB estimation approach, based upon the absolute sum values rather than sum square values. This technique avoids the use of heavy digital signal processing, since it is based on multiplication and division operations. The architecture is completely described at RTL level and does not depend on the ADC features. Experimental results show the efficiency of our approach to test the sigma delta ADC.

I. INTRODUCTION Mixed-signal devices’ cost is mainly dominated by the production test cost. This is due to the fact that test equipments are very expensive and becoming more and more time consuming. BIST techniques are able to reduce test costs, by reducing test equipment‘s cost and testing time. Analog structures are, whenever possible, moved to the digital domain to exploit the noise robustness and design shrinking progress in the digital field. Although this leads to performances improvement, it impacts the testing procedure which becomes more difficult and expensive. In this paper, we focus on the testing of Sigma-Delta ΣΔ ADC where the digital parts are the most complex on, since they are used to relax the analog specifications. The performances of ΣΔ converters are continuously improved by larger modulator bandwidths, higher dynamic ranges and better resolutions. An approach to test ΣΔ ADCs consists to measure the Signal-to-Noise Ratio and Distortion (SINAD), which can be calculated by using the sine wave fitting algorithm [1]. An improvement of this test method is done by a binary stream to represent the codes the needed sine wave signal. In fact, several researches on BIST techniques for ΣΔ converters use the auto generation of the analog input by based upon binary stimulus [2][3][10] and [11]. An

1

innovative test strategy was presented in [2,3] consisting in the use of the existing decimation filter to generate a reference signal. Nevertheless, the BIST implementation needs significant efforts on the decimation filter, considering that it must be 3 bits more precise than the signal under test. This work is the continuation of previous works [2,3]. It adds significant minimization of the digital area overhead and implements a complete separation between the BIST, the decimation filter and the modulator order. These three elements are important for industrial deployment. In fact, designers require minimum constraints and changes on the existing design as well as a minimum area overhead. The BIST, developed in this work, is based on the CORDIC [4] algorithm which can only generate the sine reference signal. Therefore, we have modified the classical CORDIC, mainly the sine wave fitting algorithm [1], in order to extend its capabilities for enabling adjustment capability of sine wave amplitude and offset as well. So, this innovative ΣΔ ADC BIST architecture is independent of the modulator order and of the converter resolution. In addition, it gives a reduced area overhead solution. Furthermore, the BIST module being implemented in VHDL with generic parameters, it provides additional advantages: • It is totally isolated from the ADC itself, then , it is easily adaptable to different ADC parameters (no required BIST modifications) • It allows implementation of gated clock technique, so we guarantee low power consumption in functional mode. This paper is organized as follows: The first section introduces the overall BIST CORDIC-based architecture. The second section, presents detailed description of sine generation, offset and amplitude adaptation, using CORDIC structure. Section 3, details the modified sine wave fitting algorithm. In section four, we present the hardware implementation of processing bloc. The simulation results with some injected faults are presented in section 5. Section

Mr L. Bouzaida has recently left STMicroelectronics. He funded DTCad Engineering company

6, shows silicon results of the BIST capabilities. Finally, we will draw some conclusions. II. OVERALL VIEW OF THE BIST ARCHITECTURE In this work we will consider a ΣΔ ADC converter [1,2] used for audio applications. It works with input signal frequencies up to 22.05 Khz. The sampling frequency of the converter is 12.288 Mhz, and the digital output rate is 48 Khz. The ΣΔ converter is composed of a 2 order analog ΣΔ modulator and a third-stage digital decimation filter. The total power noise in the audio bandwidth is equal to 248 pV2. The full range of our modulator is 1.44 Vdd, and the modulator SNDR is equal to 96.78 dB. The ΣΔ ADC is based on over sampling technique, used to reduce the BIST overhead and therefore, enables the implementation of iterative algorithm. The decimation filter reduces the sampling rate from 12 MHz to 48 KHz, with an Over-Sampling Ratio OSR of 256 clock cycle. nd

To estimate SINAD and NOEB [1], a sine wave signal must be applied on the ADC inputs. Our method is based upon a sine wave which is coded by a binary stimulus [2,3] that will be processed with the sine wave fitting algorithm. The reference signal offset is adjusted to match the test signal. The signal amplitude is then adjusted and, finally, we sum the difference error between the both signals

•

A CTRL block: It is a global controller for the BIST module. The reference signal coming from the CORDIC must be finely synchronized with the binary input stimulus [1-3]. So, first, we proceed to match the offset and amplitude, and then, on the fly, we compute the difference between the reference signal and the test response. III. DETAILED BIST CORDIC ARCHITECTURE A. Reference signal gene ration The CORDIC algorithm is introduced by Volder [4] to calculate trigonometric functions. This method is suitable for hardware applications. As shown in Figure 2, the CORDIC architecture is simply composed of: additions, subtractions, digital shift in addition to non significant constant storage.

X0

Register X

Shift 2-order ∆∑ Modulutor

IN

Decimation Filter

Y0

Z0

Register Y

Register Z Const (n) atan

Shift

16bits

∑∆ ADC

xn Test Input

Stimulus Generation

Angle Generation

CTRL

CORDIC

Modified sine wave fitting BIST

zn

yn

Figure 2: CORDIC Hardware Implementation

The CORDIC algorithm is an iterative method for performing vector rotations around selected angles.

X

i +1

= X i − Y i .d i .2 − i

Y i + 1 = Y i + X i .d i . 2 − i Z i +1 = Z i − d i . arctan( 2 − i )

Figure 1: BIST for ΣΔ ADC Architecture

Figure 1 shows the architecture of our BIST solution, composed of four main modules: • Binary stream generator: it generates a periodic binary sinusoidal stimulus (fstimulus=5456 Hz, coded in 2252 bits) for the ΣΔ Modulator inputs. • A CORDIC and the angle generation module: It is used to generate and fit the reference signal. • A sine wave fitting block: It calculates the number of effective bits.

d i = −1

if ( Z i < 0 )

d i = +1

if ( Z i ≥ 0 )

(X0,Y0): initial coordinates of the vector and Z is the angle accumulator. In order to calculate the operation (Amp*sin (α)), we first initialize X0 to Amp/K, where Amp represents the signal amplitude and K is a predefined constant. Next, we initialize Z0 to α, which is the desired sine angle, and Y0 to zero. Finally we make n iterations to have n bits precision in the final result: Xn= Amp.sin(α) ; Xn= Amp.cos(α)

B. Amplitude adjustment Using the CORDIC algorithm, we control the amplitude of the signal by adjusting the initialization value x0, in order to avoid multiplication operations which are highly area consuming. The goal being to adjust the reference signal in order to match the ADC output amplitude. This can be done by controlling the initialization value X0. The following operations aim at determining the amount of errors Δ that must be added to the initial value X0 in order to fit the amplitude of test signal: A:

Current amplitude generated by CORDIC (reference signal) B: Test amplitude generated by ADC (test response) i: is the sampled current point. Z[i] : is the current sin angle on the sampled point i Sout[i] = B sin(Z0) : is the current output of ADC Sref [I = A sin(Z0) = Xn : is the current output of CORDIC X0 : is the initial value that generated Xn X’0: is the initial value that will generate B sin(Z0) Δ[i]: is the difference between reference Sref [i]and test Sout[i] Δ[i] = Xn - B sin(Z[i]) = (A-B) sin(Z[i]) Ö B = A – Δ[i] /sin (z[i])

(1)

In order to keep the reference Amplitude equal to the test amplitude, we need to update X0 as following: S out [i ] − S ref [i K sin(Z 0 )

]

X 0' = X 0 − sign(Z 0 ) ∗

S out [i ] − S ref [i 32

]

(4)

Hardware implementation of (4) only needs shift and Sub/adders blocks.

Figure 3: Amplitude adjustments (learning phase)

X0 = A/K (2) X0’ = B/K = B/A . A/k = B/A . X0 (replace A/k by X0 using (2)) = (A – Δ[i] /sin(z[i]) ).1/A .X0 (replaces B using (1)) = X0 – Δ[i]. X0 / A.sin(z[i]) = X0 - Δ[i] / K.sin(z[i])

X 0' = X 0 −

the noise error hold on the input, we only update it by a learning rate factor. We also adapt this strategy to minimize the hardware overhead by replacing the K sin(Z0) div operation by a simple shifting one. Firstly, in the formula above (3) we replace the sinus by its sign (-1 or +1), then the K=1.6 constant has been replaced by a 2n in order to simplify the hardware implementation. Simulation results show that K equal to 32 gives the best performances. The obtained model is presented by the formula (4). Figure 3 shows the HDL simulation results on amplitude adjustment and the resulting CORDIC sine wave.

(3)

A simple model for this adjustment parameter has been used in order to minimize the hardware overhead, and to be independent from the ADC output noise. The method presented below is inspired from the backpropagation learning algorithm, used in neuronal network [5]. It uses learning steps. In each step it tries to be closer to the desired function by a learning rate factor. Higher learning rate leads to faster convergence while lower learning rate leads to more resistant to noise error hold on the input. In fact, the ADC output is nosily and we cannot find the amplitude from only one sample. To fit the output to be closer to the desired value without being disturbed by

C. Offset adjustment We calculate the offset by summing all samples during a complete N period; the offset is the average of output response. The number of sampled points is deduced from the sampling frequency. The offset will be the sum of the sampled signed voltage values divided by the number of sampling. In our case, sampling frequency is 48 kHz and sin frequency is 5.46 kHz, therefore, the number of samples will be 563 that represent 64 periods. To divide by a constant, we reuse the CORDIC structure, barrel shifters, multiplexers, counters and registers. Figure 4 shows the main modifications done on the CORDIC block to perform the multiplication by 1/563. Initially, we put the sum in the register regX, then we use the register regY as accumulator for the multiplication operations.

Y0

X0=∑

regY

regX

msb bits

msb bits

msb bits

11

01

01

10

00

00

01

11

11

00

10

10

Z0

regZ

(a) Unsigned Counter (b) Signed interpretation (c) Signed target bshift

bshift

atan

Binary code of 1/563 Xn

Yn

Zn

Figure 4: CORDIC used for division

The added lockup table codes the binary value of 1/563 (colored in blue). This table controls the adder (colored in red) to perform the appropriate sequence. To activate this mode in the CORDIC bloc, we have added an input mode pin that enable switching between the division mode and sinus generation mode. D. Angle generation This bloc generates the input angle α for the reference sine signal sin(α). It must be a triangular signal incremented step by step (frequency related). The angle α signal must be within [-π/2, π/2]. This condition is mandatory for the CORDIC algorithm operation; however, the hardware implementation to generate such a signal is very complex. Therefore, we propose some modification in the CORDIC algorithm allowing to make “α” varying from [-2n, 2n] rather than [-π/2, π/2]. The modification is done in Z path of the CORDIC hardware structure as follows: z i +1 = z i − d i . arctan( 2 − i ) There Z0 = α ∈[-π/2, π/2]. Let’s suppose z ' i +1 = z ' i −

2 n +1

π

z' i =

2 n +1

π

⋅ zi

then Z’i ∈[-2n, 2n].

⋅ d i . arctan( 2 −i )

n +1 This leads to store 2 . arctan(2 −i ) rather than arctan(2 − i )

π

in the lockup table in CORDIC structure. In order to generate a triangular signal as required for the CORDIC algorithm, we implement a hardware inversion of a part of the signal as shown in figure 5. Actually, we use an unsigned counter which output (figure 5.a) is first interpreted as signed signal (figure 5.b) and then corrected (inversion) to meet the target (triangular) signal (figure 5.c).

Figure 5: Angle generation from unsigned counter

IV. MODIFIED NOEB USING ABSOLUTE SUM VALUE

After fitting a record of sampled data, we compute the estimation of the root mean square of the noise (rms_noise) as flows: rms _ noise =

(

)

1/ 2

⎡1 M , 2⎤ ⎢⎣ M n∑=1 yn − yn ⎥⎦

Where: is the test signal coming from ADC yn y’n is the fitted reference signal M is the number of used sampled values From the rms_noise we can find SINAD and NOEB as explained in IEEE Std 1241-2000 [1]: NOEB = SINAD=

log2(Vfull) – log2(rms_noise) – log2(√12) √ 1.5 * A/(Vfull/2) * 2NOEB

Where: Vfull: A:

is the ADC input full scale range. is the amplitude of sine wave test signal

One of the added values we propose in this work is to reduce on chip calculation complexity by avoiding the use of multiplication operators. Therefore, we redefine the NOEB by using the absolute value (Norm1) instead of sum of square values (Norm 2) for computing the sine wave stimulus signal: Norm 1:

N1 ( x) = x1 + x2 + ... + xn Norm 2:

N 2 ( x) =

x1

2

+ x2

2

+ ... + x n

2

So using Norm 1, the noise formula can be transformed as following: M

rmanoise _ n1 =

∑y

n

− yn,

n =1

M

For an ideal N-bit ADC and using sinusoidal waveform:

1 T 1 = T

rma noise _ n1 =

Where : Vlsb =

∫

T /2

∫

T /2

−T / 2

−T / 2

Vq .dt −t V .Vlsb dt = lsb 4 T

Vfull/2n

This gives the NOEB : NOEB = -log2( rma noise _ n1 ) -2 +log2(Vfull) In order to confirm the theoretical equation, we have performed several Matlab simulations on typical ΣΔ ADC faults (KT/C noise, input-referred, operational amplifier noise, integrator leakage, bandgap noise and nonlinear capacitors, random noise). In all cases, we have obtained less than 1dB error compared to standard test [1] (see table 1,2) . This modification leads to much simpler hardware implementation and results in smaller area consumption and less computing time. V.

HARDWARE IMPLEMENTATION OF PROCESSING BLOCK

In this section we will detail the processing steps necessary to perform the different stages: offset adjustment, amplitude adjustment, error summing, and signature shifting operation. Hardware implantation of the detailed structure is presented in figure 6; it is composed of 4 registers and 3 Sub-adderblocks. Offset adjustment stage: As the Result_reg register will be used as accumulator of the sum, it is 5 bits longer than other registers. The different steps are: • Initially we sum 563 sampled points which correspond to 64 sine periods. • Then the Result_reg value is passed to init_x0_reg register to perform the division 1/563. • Finally, this value is memorized in the offset_reg register as it will be used in adjustment. Amplitude adjustment stage: This is done as follows: • Initially we run the CORDIC to generate the sine reference signal. • The offset of this signal is adjusted by adding the offset_reg value. • We compute the difference diff_first between the readjusted value Sin_adc_offset and test signal sin_adc_reg. • We adjust the sign of the difference according to the sign of sinus, and we save the resulting value in the Result_reg registr • Finally we remove the first 5 bits to implement the

division by 32 and bypass the value to the register init_x0_reg. • We iterate this loop for 32 sine periods to tune the fitted amplitude. Error summing stage: In this stage we run CORDIC to generate sine wave signal for 563 points that correspond to 64 sine period: • first step is to adjust the offset of the reference signal • Then accumulate the error between reference signal and test signal coming from ADC. This is done by summing the absolute value of the difference between signal Sin_adc_offset and sin_adc_reg in the register Result_reg registr Signature shifting: The result of our BIST is a signature, which is composed of the amplitude of the test signal (X0) and the accumulated sum error (noise). These information are stored respectively in init_x0_reg and Result_reg register: • Initially, init_x0_reg is shifted using only one pin bist signature • Next, the Result_reg value is transferred to init_x0_reg register • Finally we shift the init_x0_reg is shifted to get the accumulated error. Bist signature

init_x0_reg x0 CORDIC yn offset_reg Sin_adc_offset

Input sin_adc_reg signal diff_first

logic

op_type

result_reg

Figure 6: processing data path

Once we get the BIST signature (noise, X0), we can calculate the SINAD and NOEB by using this formula: Amplitude A=

X0 /K ( K is CORIDC constant)

NOEB = -log2 (noise)-2+log2(Vfull) SINAD = √ 1.5 * A/(Vfull /2) * 2NOEB

In the used test chip we have implemented debug capability to validate our bist methodology. In production test it is more suitable to include on bist border tests for the three parameter offset, Gain and NOEB to have a pass/fail test.

the embedded self-test and a sinusoidal standard test are excellent, with a SINAD error smaller than 1 dB.

VI. SIMULATION RESULTS

In order to validate our BIST strategy, some behavioral faults were injected in our 2nd order analog modulator with 16 bits resolution. Those faults affect switched-capacitor implementation, as proposed in [2,3]. Test strategy should detect the main errors that are main causes of deterioration of the modulator resolution: KT/C noise, input-referred, operational amplifier noise, integrator leakage, bandgap noise and nonlinear capacitors. From the data presented in Table 1 we can see that the difference between using a binary input stimulus and an analog sinusoidal stimulus is always very small (<0.5dB), except in the case of distortion-based errors. Also, we can notice that BIST methodology detects all tested faults, except the nonlinear capacitors. However this is predictable considering the weakness of binary stimulus techniques already presented and discussed in [2,3]. In addition, simulation results show that the correlation between the embedded self-test and an analog sinusoidal standard test are excellent, with a SINAD error smaller than ~0.5 dB except for nonlinear capacitors. Table 1: processing data path Ideal Modulator 95.91 95.46 KTC noise (C=0.5pF) 93.7 93.84 1st Integrator Leakage (Lg=0.99) 94.83 95.14 1st Integrator Leakage (Lg=0.98) 92.09 92.6 94.86 94.58 (10µVrms) - Opamp Noise (100µVrms)- Opamp Noise 78.87 79.42 94.54 94.15 (20µVrms) - Bandgap Noise (200µVrms)- Bandgap Noise 78.1 78.67 89.92 95.34 Non-linear capacitor (α2=-0.01%)

0.45 -0.14 -0.43 -0.51 0.28 -0.55 0.39 -0.57 -5.42

VII. SILICON RESULTS

The ΣΔ modulator has been designed in STMicroelectronics CMOS 0.13μm technology. DFT bandgab structure was added to support the binary stimulus insertion. To validate the CORDIC based BIST approach on FPGA, we have recovered all test cases already applied in previous work [3] and performed them with this new approach. Figure 7 shows the ADC characterization results done by both the CORDIC based BIST algorithm and the standard BIST based on the digital filter reuse. We can easily remark that they fit very well. We have performed another experimental validation on the board, by introducing some errors on the voltage reference of the binary stimulus (Table 2). Experimental results show that the correlation between

Figure 7: SNDR measured by standard and CORDIC based approaches Table 2: Experimental validation

[Difference] SNRD SNRD IEEE vs IEEE 3V CORDIC CORDIC standard BIST BIST Fault Free 84.6 83.70 0.94 A 78.8 78.20 0.72 B 80.5 80.1 0.39 C 76.2 76.3 0.01 D 64.2 64.5 0.21 E 59.5 59.9 0.31 F 0.02 12.6 0.10 G 52.9 53.1 0.16 H 49.7 50.2 0.41 K 0.04 -0.04 0.52 M 0.01 -0.006 0.66 N 30.6 31.2 0.46 L 27.1 27.5 0.36 U 29.4 29.9 0.42 T 16.0 16.9 0.86 R 12.6 13.3 0.65

Test Result Pass Fail Fail Fail Fail Fail Fail Fail Fail Fail Fail Fail Fail Fail Fail Fail

VIII. CONCLUSION

In this work we focused on improving the digital part of the SNDR-based BIST technique, reducing the overhead area of the digital blocs. Using the CORDIC algorithm and the Norm 1 for ENOB calculation, we have reduced the BIST overhead area, obtaining an area smaller than 10.000 µm in STMicroelectronics 65nm technology. This represents a gain factor of 10X compared with the original BIST based on the filter modification [2,3]. The digital BIST part represents 1.5% of the total ADC area. It goes up to 6% if we include analog BIST bloc. The gain of area does not deteriorate the precision of the BIST technique and the measurement errors are smaller than 1dB in all cases, except in the case of distortion faults. These results are very encouraging to continue with this BIST strategy and to make a full implementation on real chip.

REFERENCES [1]

IEEE Standard for Terminology and Test Methods for Analog-toDigital Converters. IEEE Std 1241-200, pp. 51–54. [2] L. Rolíndez, S. Mir, A. Bounceur and J.L. Carbonéro, “A SNDR BIST for SD Analogue-to-Digital Converters,” in Proc. IEEE VLSI Test Symposium, Berkeley, USA, May 2006, pp. 314-319. [3] L. Rolíndez, S. Mir, J.L. Carbonero, D. Goguet and N. Chouba. “A stereo audio SD ADC architecture with embedded SNDR test”. IEEE International Test Conference, Santa Clara, USA, October 2007. [4] Volder J.E ”The CORDIC trigonometric computing technique.” In IRE Trans. Electronic Computing, volume EC-8, pages 330 - 334, 1959. [5] B. Widrow and M. A. Lehr. 30 Years of Adaptativ Neural NetWorks: Perceptron, Madaline and Backpropagation. Proc. IEEE, 78(9):14151442, 1990 [6] K. Arabi and B. Kaminska, “Efficient and Accurate Testing of Analog-to-Digital Converters Using Oscillation-Test Method”, Proceedings IEEE European Design and Test Conference, Paris, France, pp. 348-352, Mar. 1997. [7] J.L. Huang and K.T. Cheng, “Testing and Characterization of the One-Bit First-Order Delta- Sigma Modulator for On-Chip Analog Signal Analysis”, Proceedings IEEE International Test Conference, Atlantic City, USA, pp. 1021-1030, Oct. 2000. [8] A. Roy, S. Sunter, A. Fudoli and D. Appello, “High Accuracy Stimulus Generation for A/D Converter BIST”, Proceedings IEEE International Test Conference, Baltimore, USA, pp. 1031-1039, Oct. 2002. [9] C.K. Ong, K.T. Cheng and L.C. Wang, “A new sigma-delta modulator architecture for testing using digital stimulus”, IEEE Transaction of Circuit and System I, V. 51, pp. 206-213, Jan. 2004 [10] Dufort, B.; Roberts, G.W. “On-chip analog signal generator for mixed-signal built-in self-test”, Custom Integrated Circuits Conference, 1998. Proceedings of the IEEE 1998 Volume , Issue , 11-14 May 1998 Page(s):549 – 552 [11] Chee-Kian Ong; Kwang-Ting Cheng “Self-testing second-order delta-sigma modulators using digital stimulus” VLSI Test Symposium, 2002. (VTS 2002). Proceedings 20th IEEE Volume , Issue , 2002 Page(s): 123 – 128