A New Short Circuit Power Model for Complex CMOS Gates Qi Wang, Sarma B.K. Vrudhula Center for Low Power Electronics Department of Electrical and Computer Engineering The University of Arizona, Tucson, AZ 85721 qi,[email protected]

Abstract In this paper we propose a new model for short circuit power estimation of CMOS gates. The short circuit power of a CMOS gate is estimated by converting the gate into an equivalent CMOS inverter and all input signal waveforms into a single equivalent input signal for the inverter. The channel width and the input to the equivalent inverter are functions of the waveforms of all the inputs. This is dierent from the traditional approaches where only worst case situations are considered. HSPICE simulation of NAND gates using a commercial 0.25 m CMOS process show that the proposed new short circuit power model for CMOS gates is much more accurate than previously reported models.

1 Introduction

Traditional power optimization and estimation techniques for digital CMOS circuits focus on the dynamic power dissipation, caused by charging and discharging the load capacitances at the gate outputs. However, as the device sizes and threshold voltagea continue to decrease, the short circuit power dissipation (Psc ) is no longer a negligible factor [5, 10]. Psc is due to the simultaneous conduction of the PMOS and NMOS transistors during the input and output transitions. Although the problem of the Psc modeling for CMOS inverters has received a much attention recently [2, 7, 8, 10], little work has been done on the Psc modeling of complex CMOS gates. A common approach to solve this problem is to reduce a CMOS gate into an equivalent inverter for short circuit power estimation. The key issue here is to determine the channel widths of the transistors of the equivalent inverter and the eective input signal fed to it. This problem has been addressed for CMOS gate delay estimation in [3, 4, 6]. The traditional approach is to determine the eective input to the equivalent inverter based on fastest (slowest) input signal of the CMOS gate for parallel (series) connected MOSFETs [4, 6]. This approach may result in signi cant errors in delay estimation [3]. In [3], the eective signal is heuristically chosen to be the \average" of the overlapping input signals of the CMOS gate, as shown in Figure 1. Although this approach improves the accuracy of delay prediction, it is not suitable for short circuit estimation. For example, in Figure 1(b), the short circuit current ows from VDD to GND from time t1 to t4 . This is because after t4 one of the PMOS transistors will be turned o and no conducting path from VDD to GND exists. However in the approximation shown in Figure 1(b), the eective signal (plotted

in dotted line) will be presented beyond t4 . Therefore using the eective input signal in Figure 1(b) for short circuit power estimation will lead to inaccurate results. t3

GND

t1 t2

t4

t4

Vdd

GND t1

(a)

t3

Vdd

t2 (b)

Figure 1: Derivation of eective input signal toward estimating the output falling propagation delay of a 2-input NOR gate in [3]. The solid lines are the original input signals and the dotted lines are the eective input to the equivalent inverter for dierent relative delays of input signals. The traditional approach to compute the channel width of the equivalent transistor is also straightforward [6, 3]. For example, the equivalent transistor width of MOSFETs connected in series is the inverse of the sum of the reciprocal of the channel width of each individual transistor; and the equivalent transistor width of parallel connected MOSFETs is simply the sum of the width of each individual transistor. In [4] a much better approximation for the equivalent transistor width is given where the equivalent transistor width depends on the relative delays of input signals. One shortcoming of this method is that it requires computing technology dependent parameters using HSPICE simulation. In this paper, we propose a new approach to the problem of Psc modeling for complex gates. The new solution can be viewed as a generalization of the methods in [3] and [4] in that both equivalent channel width and the eective input signal are dependent on the relative delays of the input signals of the CMOS gate. Additionally, the models for computing the equivalent channel width and eective input signal are dierent from [4] and [3] respectively. We start with a 2-input NAND gate as shown in Figure 2(a). The model of an equivalent inverter of the 2-input NAND for Psc estimation for dierent input combinations is described in Section 2. The extension of the model to other complex CMOS gates is discussed in Section 3. Experimental results on the proposed model for 2-input NAND gates are shown in Section 4. Finally, conclusions and future directions of the work are given in Section 5.

2 P Model for 2-input NAND Gates sc

In this section, we present a new approach toward reducing a 2-input CMOS NAND gate to an equivalent inverter for Psc estimation. Given the equivalent inverter and the input signal, the Psc model for CMOS inverters proposed by [10] is used to estimate the short circuit power of the NAND gate. One key dierence between the approach to be presented next and other approaches [6, 3, 4] is that the derived equivalent inverter and input signal will depend on the relative delays of the input signals. This will be further elaborated upon in Sections 2.1 to 2.3. For a switching signal k, let tk be the time the transition starts, sk

be the transition time and rk be the time when the transition completes, i.e. rk = tk + sk . The Transition window ( ) of a gate is de ned as the time interval when there exists a direct path from VDD to GND during the input and output transitions. Henceforth, it will be referred to simply as a window. Vdd Pa

Pb a

a

b

Na Nb

b

CL ta

(a)

t b rb ra

(b)

Figure 2: An example for eective input signal and equivalent inverter approximation of a 2-input NAND gate for Psc estimation. (a) A 2-input NAND gate. (b) The input waveforms.

2.1 Case 1. Both Inputs Changing from 0 to 1

When both inputs of a 2-input NAND gate change from 0 to 1, the output of the NAND gate will drop from 1 to 0. Note that in this case the driving path consists of the two NMOS transistors connected in series and the output will not change if any one of the inputs is 01 . The transistors responsible for the short circuit current are the two PMOS transistors connected in parallel. There will be a short circuit current as long as one of the inputs has not reached 1. Therefore, the window of the NAND gate when both inputs are rising can be simply approximated by:

= max(ra ; rb ) , max(ta ; tb ) (1) For example in Figure 2(b), the output voltage will not start to drop until tb since before tb the input b is 0. The total short circuit current will become 0 at ra since both PMOS transistors are o at that time. Therefore the time interval [tb ; ra ] is the only interval then there exists a direct path from VDD to GND. The loading factor (L) for each input signal is de ned as the ratio of the portion of each input signal transition within the window to the size of the window. For example, for the input waveforms of the NAND gate shown in Figure 2(b), = ra , tb ; La = (ra , tb )= = 1; Lb = (rb , tb )= . The loading factor indicates how much each signal and the corresponding transistor (the signal it is connected to) contributes to the overall short To be more precise, the output will not change if any one of the inputs is less than the NMOS threshold voltage,V . Using logic value 0 or 1 instead of the threshold voltage values of PMOS and NMOS simplify the discussion. 1

t;n

circuit current. In this example, the PMOS transistor Pa in Figure 2(a), is on within the whole window period so its loading factor is 1. On the other hand, the PMOS transistor Pb will be o after rb , hence it contributes to the total short circuit current only during the time interval [tb ; rb ], i.e. Lb = (rb , tb )= . In general, the loading factor for the input signal k of a 2-input NAND gate when both inputs are rising can be computed as follows:

Lk =

(

r ,max(t ;t ) max(r ;r ),max(t ;t ) a

k

0;

a

if rk > max(ta ; tb ) otherwise.

b

a

b

b

)

k = 1; 2

(2)

Note that if Lk = 0, it means that signal k will stay at the non-controlling value (logic 1) during the whole transition period (window) of the other input signal. Having de ned the loading factor for each signal, the equivalent channel width of the PMOS and NMOS transistor of the equivalent inverter are calculated as follows:

Wp;eqv = La  WP + Lb  WP (3) (4) Wn;eqv = W(WN(2W,NL(2),+LWa)(2(2,,LLb))) N a N b As an example, assume that WP = WP = WP and WN = WN = WN , and consider the case when La = 1 and Lb = 1, i.e. both input signals start to switch at the same time with the same slope. From Equations 3 and 4, Wp;eqv = 2WP and Wn;eqv = WN =2. These are exactly the same formulas used by the traditional approach for Psc estimation [3]. a

a

b

b

a

b

a

b

a

b

Therefore Equations 3 and 4 are a generalization of the traditional approach to reducing a 2-input NAND gate to an equivalent inverter for delay estimation. As another example, when La = 1 and Lb = 0, Wp;eqv = WP and Wn;eqv = 23 WN . This is as expected since the PMOS transistor Pb is o during the input and output transition time and does not cause any short circuit current to ow during the transition. On the other hand, the pull down path should have better conductivity compared with the case when La = 1; Lb = 1 since Nb will be always on during the period that the output falls. Note that either La or Lb will be 1 all the time, therefore Wn;eqv is in the range of [ 21 WN , 23 WN ]. Finally the slope of the equivalent input signal for the inverter is simply ,1 . Having obtained the channel widths for the transistors of the equivalent inverter and the input slope for the 2-input NAND gate, the Psc model given by [10] for inverters can be used to estimate the Psc of the gate.

2.2 Case 2. Both Inputs Changing from 1 to 0

The analysis of this case is similar to Case 1. The path responsible for the short circuit current consists of the two NMOS transistors in series. The window can be calculated as follows:

= min(ra ; rb ) , min(ta ; tb ) (5) This is because as soon as one of the inputs start to fall, the path from VDD to GND also starts to form. The path will cease to exists if at least one of the inputs becomes 0. The loading factor for the input k can then be calculated as.

Lk =

(

min(r ;r ),t min(r ;r ),min(t ;t ) a

0;

a

b

b

k

a

b

if tk < min(ra ; rb ) otherwise.

)

k = 1; 2:

(6)

The formulas for the Wp and Wn are the same as those in Equation 3 with the exception that dierent loading factors are used. The equivalent input slope of the inverter is still

,1 . Note that the value of here is dierent from the one obtained by Equation 1.

2.3 Case 3. One Input Rising and the Other Input Falling

If two transitions start far enough apart then the problem is reduced to the case where only one input switches. These have been been handled in case 1 and 2 where the loading factor of one input is 1 and the loading factor of the other input is 0. However, if the two transitions are suciently close, then the problem becomes more complicated. If the two transitions start at the same time and have the same transition time, then ideally the output will always stay at logic 1. Consequently no short circuit current ows during the transition. However, if the two transitions start at dierent times or start at the same time but with dierent transition times, then it is possible that a glitch will be presented at the output. In this case there will be some short circuit current. Unfortunately, a reasonably accurate estimation of this current requires complicated transient analysis of a transistor which is not practical. However, the glitch is normally smaller in magnitude compared to the full output swing during a normal transition and therefore the short circuit current will also be smaller. Our solution to this problem is that when the two transitions start at the same time, the Psc is taken to be 0; when the two transitions start far enough apart, the single input transition model, a special case of Case 1 and 2, is used to reduce the gate to an equivalent inverter to estimate Psc .

3 Extension the Model to More Complex CMOS Gates Another advantage of the above procedure is that it is easy to extend the model to more complex CMOS gates. For example, for a k-input NAND gate with all inputs rising, the results are as follows:

Wp;eqv =

k X j =1

Lj WP

(7)

j

Wn;eqv = Pk 1 1 j =11 W (2,L ) ) ( r ,max(t1 ;


;t ) if r > max( t ;


; t ) 1 k k window Lk = 0; otherwise. Nj

k

(8)

j

k

= max(r1 ;


; rk ) , max(t1 ;


; tk )

(9) (10)

In this case the discharging path consists of NMOS transistors connected in series. There will exist a short circuit path when all NMOS transistors are on until all input signals settle to logic 1, i.e. all PMOS being turned o. Given the de nitions of the window ( ) and the loading factor (L), the above equations are easy to understand. The models for other cases of NAND gates and NOR gates can be derived analogously. In general, to reduce k transistors connected in parallel (series) to an equivalent single transistor, Equation 7 (8) should be used. However, the loading factors and the window will be dierent for dierent scenarios. First the window for a particular input transition

pattern and topology of the complex gate is determined. Then the loading factor of each signal can be easily calculated according to the de nition.

4 Experimental Results The proposed model of Psc for CMOS gates was veri ed by HSPICE simulation on a 2-input NAND gate for dierent combinations of input waveforms. The Psc model for the equivalent inverter is from [10] which was shown to be very accurate for current deep submicron technology. The MOSFET model parameters and HSPICE models were obtained from a commercial 0.25 m process. Three sets of experiments were conducted corresponding to the three sets of input waveforms shown in Figure 3. In each set of experiments two dierent load capacitances were considered, one of 50 fF and the other of 100fF. Input a

Input b

.....

(a)

.....

.....

(b)

.....

.....

.....

(c)

Figure 3: Input waveforms for dierent sets of experiments of the Psc estimation of a CMOS 2-input NAND gate. (a) Experiment setup I. (b) Experiment setupII. (c) Experiment setup III. Input waveforms for the experiment set I were shown in Figure 3(a). In this setup, input

a has a 2 nano second transition time for both rising and falling transition. The transition time of the input waveform b varies from 2 nano seconds to 5 nano seconds. Note that all

transitions start at the same time. For the experiment set II, both inputs have the same transition time but the starting time of transitions were dierent. The dierence between the starting time of a and b varies from 0 nano seconds to 5 nano seconds, assuming that a always starts to switch at time 0, as shown in Figure 3(b). Experiment setup III was a combination of I and II. That is, a and b have dierent transition times as well as dierent starting times, as shown in Figure 3(c). The experimental results are shown in Tables 1, 2, and 3. The column labeled CL shows the load capacitance in fF for each experiment. P 0 is the Psc value in micro watts obtained from the HSPICE simulation. P 1 and P 2 were the Psc values obtained from the proposed model and traditional model respectively. The terms error1 and error2 are the relative errors of P 1 and P 2 as a percentage of P 0. In Table 1, the column slew shows the dierent transition times for signal b in the experiment setup I. In Table 2, the column start shows the dierent start times of signal b in the experiment set II. In Table 3, the columns start and slew were the start times and transition times of signal b in the experiment set III. From the experimental results we can see that the proposed Psc model for CMOS gates was much more accurate than the traditional models. For example, for the experiment set

CL (fF) 50 50 50 50 50 50 50 100 100 100 100 100 100 100

slew (ns) 2.0 2.5 3.0 3.5 4.0 4.5 5.0 2.0 2.5 3.0 3.5 4.0 4.5 5.0

P0 ( W) 6.36 6.21 8.15 9.20 10.75 12.32 13.70 5.38 4.85 6.09 7.39 8.59 9.91 11.10

P1 ( W) 6.023 7.29 8.551 9.849 11.196 12.593 14.039 4.68 5.616 6.558 7.538 8.563 9.635 10.752 Avg

error1 -5.4% 17.3% 4.9% 7.0% 4.1% 2.2% 2.5% -13.0% 15.8% 7.7% 2.0% -0.3% -2.8% -3.1% 2.8%

P2 ( W) 6.02 8.14 10.42 12.85 15.41 18.09 20.88 4.68 6.33 8.13 10.07 12.11 14.26 16.51

error2 -5.4% 30.9% 27.8% 39.6% 43.4% 46.8% 52.4% -13.0% 30.6% 33.6% 36.2% 41.1% 43.9% 48.7% 32.6%

Table 1: Comparison of the proposed Psc model and the HSPICE simulation for a 2-input NAND gate given the experiment setup I I, the average error of the new model was within 3% of the HSPICE simulation while the error of the traditional model was about 33%. Overall the new model was within 10% of the HSPICE simulation.

5 Conclusions and Future Work Power estimation and optimization for deep submicron CMOS logic circuits requires accurate modeling of short circuit power dissipation [1]. In this paper we described a new short circuit power model for CMOS complex gates. Unlike the traditional models, the new model is a function of the relative delays of the input transitions of the CMOS gates. Consequently the contributions of each input signal and the connected transistors to the total Psc of each transistor during the switching period can be accurately modeled for dierent input waveforms, e.g. dierent transition starting time and dierent slopes. HSPICE simulations on a 2-input NAND gate with several input waveforms show that the new model is much more accurate than the traditional Psc models for CMOS gates which are normally based on the worst case analysis. Since limited computation is required in the new models, these models can be used for accurate short circuit power estimation for modern VLSI circuits with millions of gates. Future directions of the work in this area can be pursued in the following ways: (1) verifying the model with more complex CMOS gates, i.e. AOI gates, by HSPICE simulation; (2) solving the problem of Psc estimation for simultaneous and opposite input switching; (3) utilizing the new models at the gate level for the short circuit power minimization of CMOS circuits.

CL start P0 P1 (fF) (ns) ( W) ( W) 50 1.0 6.35 6.02 50 1.5 5.67 6.12 50 2.0 5.91 6.02 50 2.5 5.48 5.74 50 3.0 5.52 5.27 50 3.5 5.48 5.27 50 4.0 5.47 5.27 50 4.5 5.46 5.27 50 5.0 5.45 5.27 100 1.0 5.35 4.68 100 1.5 4.44 4.71 100 2.0 4.32 4.60 100 2.5 4.17 4.35 100 3.0 3.98 3.96 100 3.5 3.89 3.96 100 4.0 3.87 3.96 100 4.5 3.85 3.96 100 5.0 3.85 3.96 Avg

error1 -5.1% 8.0% 1.9% 4.7% -4.5% -3.8% -3.5% -3.4% -3.2% -12.4% 6.2% 6.3% 4.2% -0.5% 1.9% 2.4% 3.0% 3.0% 0.3%

P2 ( W) 6.02 6.02 6.02 6.02 6.02 6.02 6.02 6.02 6.02 4.68 4.68 4.68 4.68 4.68 4.68 4.68 4.68 4.68

error2 -5.1% 6.2% 1.9% 9.8% 9.1% 9.8% 10.1% 10.4% 10.5% -12.4% 5.5% 8.2% 12.2% 17.6% 20.3% 20.9% 21.7% 21.6% 9.9%

Table 2: Comparison of the proposed Psc model and the HSPICE simulation for a 2-input NAND gate given the experiment setup II

6 Acknowledgement

We wish to thank Dr. Tom Dillinger with the Rockwell Semiconductor Systems, in San Diego, California for his support of this work. This work is also supported by Center for Low Power Electronics (CLPE). CLPE is an NSF S/IUCRC center with industrial support by Analog Devices, Analogy, Ambit, Burr Brown, Gain Technology, interHDL, Intel, Microchip, Motorola, Rathyeon, Rockwell, Texas Instruments, and Western Design.

References [1] M. Borah, R.M. Owens, and M.J. Irwin. Transistor sizing for low power CMOS circuits. IEEE Transactions on Computer Aided Design, 15(6):665{671, June 1996. [2] N. Hedenstierna and K. O. Jeppson. CMOS circuit speed and buer optimization. IEEE Transactions on Computer Aided Design, 6(2):270{281, March 1987. [3] Y.-H. Jun, K. Jun, and S.-B. Park. An accurate and ecient delay time modeling for MOS logic circuits using polynomial approximation. IEEE Transactions on Computer Aided Design, 8(9):1027{1032, 1989.

CL start slew P0 P1 (fF) (ns) (ns) ( W) ( W) 50 1.0 5 10.82 10.37 50 1.5 4 8.48 8.17 50 2.0 3 6.13 6.11 50 2.5 2 4.42 4.21 50 3.0 1 3.28 2.46 100 1.0 5 8.47 7.85 100 1.5 4 6.60 6.18 100 2.0 3 4.84 4.63 100 2.5 2 3.61 3.22 100 3.0 1 2.61 1.94 Avg

error1 -4.1% -3.7% -0.3% -4.8% -25.0% -7.4% -6.5% -4.4% -10.9% -25.7% -9.3%

P2 ( W) 20.88 15.41 10.42 6.02 2.46 16.51 12.11 8.13 4.68 1.94

error2 93.0% 81.8% 70.0% 36.2% -25.0% 94.9% 83.4% 67.9% 29.5% -25.7% 50.6%

Table 3: Comparison of the proposed Psc model and the HSPICE simulation for a 2-input NAND gate given the experiment setup III [4] A. Nabavi-Lishi and N.C. Rumin. Inverter models of CMOS gates for supply current and delay evaluation. IEEE Transactions on Computer Aided Design, 13(10):1271{ 1279, 1994. [5] M. Pedram. Power minimization in IC design: Principles and applications. ACM Transactions on Design Automation of Electronic Systems, 1(1):3{56, January 1996. [6] V.B. Rao and T.N. Trick. Accurate multiple delay calculations for MOS circuits. In Proceedings of International Symposium of Circuits Systems, pages 761{764, 1982. [7] S. Turgis, N. Azemard, and D. Auvergne. Explicit evaluation of short circuit power dissipation for CMOS logic structures. In Proceedings of International Symposium on Low Power Design, pages 129{134, Montery,CA, August 1995. [8] H.J.M. Veendrick. Short-circuit dissipation of static CMOS circuitry and its impact on the design of buer circuits. IEEE Journal of Solid State Circuits, 19(4):468{473, August 1984. [9] S. R. Vemuru and N. Scheinberg. Short-circuit power dissipation estimation for CMOS logic gates. IEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications, 41(11):762{765, November 1994. [10] Qi Wang and Sarma B.K. Vrudhula. On short circuit power estimation of CMOS inverters. In International Conference on Computer Design, pages 70{75, Austin, Texas, October 1998.