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A Review of Core Compact Models for Undoped Double-Gate SOI MOSFETs Adelmo Ortiz-Conde, Senior Member, IEEE, Francisco J. García-Sánchez, Senior Member, IEEE, Juan Muci, Slavica Malobabic, Student Member, IEEE, and Juin J. Liou, Senior Member, IEEE

Abstract—In this paper, we review the compact-modeling framework for undoped double-gate (DG) silicon-on-insulator (SOI) MOSFETs. The use of multiple gates has emerged as a new technology to possibly replace the conventional planar MOSFET when its feature size is scaled to the sub-50-nm regime. MOSFET technology has been the choice for mainstream digital circuits for very large scale integration as well as for other high-frequency applications in the low-gigahertz range. But the continuing scaling of MOSFET presents many challenges, and multiple-gate, particularly DG, SOI devices seem to be attractive alternatives as they can effectively reduce the short-channel effects and yield higher current drive. Core compact models, including the analysis for surface potential and drain–current, for both the symmetric and asymmetric DG SOI MOSFETs, are discussed and compared. Numerical simulations are also included in order to assess the validity of the models reviewed. Index Terms—Asymmetric double-gate (DG) MOSFET, drain–current model, intrinsic channel, MOS compact modeling, multigate MOSFET, silicon-on-insulator (SOI) MOSFET, symmetric DG MOSFET, undoped body MOS.

I. INTRODUCTION

T

HE CONTINUING downscaling of the conventional complementary MOS (CMOS) has been hindered by the growing deleterious presence of the short-channel effects (SCEs) [1], [2]. Silicon-on-insulator (SOI) MOSFETs, on the other hand, are poised to become a prominent next-generation technology because of their inherent thin channel region which can effectively suppress SCEs [1]–[4], and in this respect, they are an ideal candidate to enable further dimension downscaling below the sub-50-nm regime [5], [6]. In fact, nanoscale SOI MOSFETs are nowadays gradually replacing conventional bulk devices in some very large scale integration (VLSI) and highfrequency CMOS applications. The advantage of reduced SCEs means that SOI CMOS structures have a smaller power-delay product than the bulk technology for a given technology node (i.e., a minimum mask channel length). Moreover, as the CMOS technology advances with time (i.e., the dimension decreases), Manuscript received March 3, 2006; revised July 25, 2006. The review of this paper was arranged by Editor C. Lu. A. Ortiz-Conde, F. J. García-Sánchez, and J. Muci are with the Solid State Electronics Laboratory, Simón Bolívar University, 89000 Caracas, Venezuela (e-mail: [email protected]; [email protected]; [email protected]). S. Malobabic is with the School of Electrical Engineering and Computer Science, University of Central Florida, Orlando, FL 32816 USA (e-mail: [email protected]). J. J. Liou is with the School of Electrical Engineering and Computer Science, University of Central Florida, Orlando, FL 32816 USA and also with Department of Information Science and Electronic Engineering, Zhejiang University, Hangzhou 310027, China (e-mail: [email protected]). Digital Object Identifier 10.1109/TED.2006.887046

the advantage of SOI in power-delay product increases. This was clearly illustrated by the work of Shahidi of IBM [7] in a comparison of bulk and SOI CMOS technologies of 0.13, 0.18, and 0.22 µm. Two recent applications showing evidence of the superiority of the SOI over bulk technology are SOI microprocessors with more than 20% percent speed improvement [7], [8] and SOI RF power amplifiers with higher power efficiency [9]. The ongoing downscaling of the bulk technology has resulted in an increase in the transistor count and chip size [10], [11]. Thus, the number of metal layers has been increasing in order to be able to connect the growing number of transistors. Because of this inevitable trend, interconnect complexity and thus interconnect delay is becoming a more dominant factor in the circuit performance. According to the research work at Intel [11], the SOI technology should emerge very soon as the core CMOS technology because it allows for three-dimensional integration, and therefore reduces interconnect complexity. IBM and AMD [7], [12] are already using the SOI technology in their commercial microprocessors. In a plenary presentation in 2004 [13], Iwai described how the end of Moore’s Law has been predicted several times without success during the last two decades using different arguments. Moore’s Law is still valid today, and some optimistic predictions [13] suggest that it will remain valid until 2035 when the feature size approaches 0.3 nm which is about the distance between two atoms in the silicon crystal. A 5-nm gate length MOSFET was reported in 2003 [14], which is probably the smallest workable MOS device to date. It is important to point out that 5 nm is only 17 times the distance between two atoms in the silicon crystal. In addition to its dominance in digital applications, CMOS has been rapidly taking on the RF market, which for many years was dominated by bipolar, MESFET, and BiCMOS technologies. Review articles written recently by Abidi [15], Liou and Schwierz [16], and Ortiz-Conde and García-Sánchez [17] gave detailed descriptions of such a trend. The evolution of CMOS into RF technology started since the first bulk CMOS RF amplifier was reported in 1993 [18]. Recently, SOI technology is being used in RF applications such as a 1-V transceiver [19] and low-noise amplifiers in the low-gigahertz range [20]. Nanoscale double-gate (DG) SOI MOSFETs with an undoped body (sometimes referred to as “intrinsic channel” MOSFETs) are particularly attractive [21]. These devices permit the suppression of SCEs by means of an undoped ultrathin body instead of the usual high channel doping density. The absence of dopant atoms in the channel further reduces mobility

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models and analyzing the motivations and general benefits of using SOI in integrated circuits. In the following sections, we will provide a unified review of the recent compact models developed for the drain–current of symmetric and asymmetric DG SOI MOSFETs.

II. FUNDAMENTALS OF DG SOI MOSFETS

Fig. 1. Schematic structure of a generalized asymmetric DG n-MOSFET.

degradation by eliminating impurity scattering and avoiding random microscopic dopant fluctuations [22], [23]. Accurate and physics-based compact models are useful for the design and development of MOSFETs for digital and analog circuits. These models are highly desirable because they offer better computational efficiency than their numerical alternatives without loss of physical insights [24]. Many of the recent compact models [25]–[29] for DG MOSFET have been developed based on the classical physics. Thus, the focus of this paper is the review of classical physics-based formulations, upon which a core compact model could be built. It should be noted that developing classical physics-based formulations is a critical step to construct a compact model. Advanced physical effects, such as quantization effects and velocity overshoot, are often considered as add-ons to such formulations if necessary [30], [31]. For example, typical approximate methods to include the quantum mechanical effects consist of incorporating a quantum correction term into the conventional drift-diffusion equation [32]. This method, called the quantum drift-diffusion equation or density gradient, is computationally efficient, and approximate analytical solutions calculated from this method have been presented [32]. For DG SOI devices, core compact models can in general be surface potential or charge based, and the traditional thresholdvoltage-based approach is not applicable due to the presence of an undoped silicon body in such devices. For example, Taur [33], [34] developed a framework of two equations to describe the electrostatic potential in the silicon film of the DG MOSFET. A charge-based drain–current model (designated as surface potential plus) was developed in 2004 by He et al. [35] to avoid the numerical solution of the transcendental equation used in the surface potential-based models. Recently, a unified model for DG MOSFETs was derived by Taur et al. [36] based on the Pao–Sah’s integral [37]. Ortiz-Conde and coworkers [27], [29] have also proposed a surface potentialbased drain–current model for DG MOSFETs, which was an extension of their previously proposed Lambert functionbased analytic solution for the surface potential of single-gate undoped-body bulk devices [28], [38]. Several good-review articles have appeared recently [39]–[43] for describing and comparing the various SOI

Fig. 1 presents the schematic structure of an asymmetric DG n-MOSFET. This device possesses two gates and two different oxide thicknesses. The second gate at the bottom allows for full depletion of the semiconductor film (i.e., channel). The symmetric device is a special case of the asymmetric device; that is, the symmetric device’s two oxide thicknesses are equal, the two gates have the same flatband voltage, and the gates are connected together. We will first discuss the electrostatic potential and drain– current modeling of the symmetric DG SOI MOSFETs and will later extend the analysis to the generalized and more complex asymmetric case.

A. Description of Potentials for Symmetric Devices Consider an undoped-body symmetric DG n-channel MOSFET, in which x is the vertical direction across the channel thickness and y is the horizontal direction along the channel. Symmetric means that the two gates have the same work function, both the top and bottom gate oxides are of the same material and thickness, and the same bias is applied to the two gates. It can be assumed that the quasi-Fermi level is constant along the x direction, and current flows mainly in the y direction. The energy levels are referenced to the electron quasi-Fermi level of the n+ source region. Considering the case that the contribution of holes is negligible and the electrostatic potentials ψ
kT /q, the solution of the one-dimensional Poisson equation in the x direction of the channel region, under the quasi-equilibrium approximation, leads to the following two equations [33], [34]: √


2kT ni εs e−βV (eβψS − eβψo ) (1) Co      2n β(ψo −V ) (tSi − x0 ) q 2  i  ψS = ψo − ln cos  e 2  β  2kT εs 2

V G = ψS +

(2) where VG is the difference between the applied gate-to-source voltage and the flatband voltage, β = q/kT is the inverse of the thermal voltage, ni is the intrinsic free carrier density, ψS is electrostatic potential at the surface (x = tSi /2), ψo is the potential extremum at the center of the silicon film (x = 0), Co is the gate oxide capacitance per unit area, εS is the permittivity of the semiconductor, tSi is the semiconductor film thickness, and V is the potential difference between electron and hole quasi-Fermi levels along the channel (i.e., voltage drop in the

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channel), which is equal to zero at the source and VDS at the drain. Equations (1) and (2) must be solved to obtain the surface potential ψS and the center-of-film potential extremum, ψo , both at the source, y = 0, and at the drain, y = L. The solution at the source end, with V = 0, gives: ψS = ψS0 and ψo = ψo0 . Analogously, solving at the drain end, with V = VDS , produces ψS = ψSL and ψo = ψoL . B. Generalized Double Integral Formulation for Drain–Current The drain–current can be described following the idea of Pao and Sah that includes both the drift and diffusion transport tendencies in the silicon film, resulting in a current description with smooth transitions between the linear and saturation operating regions. Under the approximation that the mobility is independent of the position in the channel, the drain–current ID can be expressed as [35], [36] W =µ L

ID

VDS

QI dV

(3)

0

where µ is the effective electron mobility, W is the channel width, L is the effective channel length, and QI is the total (integrated in the transverse direction) inversion charge density inside the silicon film of a symmetric DG MOSFET at a given location y defined by t Si /2

QI ≡ −2q

ψS

(n − ni ) dx = −2q 0

n − ni dψ F

α≡−

ψS VDS

0

qn dψ dV F

(5)

(6)

ψo

with n = ni exp (β(ψ − V )). The electric field in the semiconductor film is given by  F =−

2kT ni β(ψ−V ) e +α εs

(8)

is defined as an interaction factor representing the charge coupling between the two gates [44]. III. DRAIN–CURRENT MODELS FOR SYMMETRIC DEVICES In this section, we will review various analytic models for the drain–current of symmetric DG MOSFETs. In order to easily compare the different models, we will use the same notations defined in this paper instead of the original notations used in the papers under review. A. Surface Potential-Based Models Two surface potential-based models by Ortiz-Conde et al. [27] and Taur et al. [36] have been reported; their final expressions look very different, although they are actually equivalent to each other. 1) Ortiz-Conde et al. Model: Following the idea of Pierret and Shields [45] for bulk MOS devices, the double integral equation in (6) can be transformed, without making any additional approximations, into the following explicit expression for the drain–current of DG SOI devices [27]: ID

W =µ L



   1 2 2 ψ − ψS0 2Co VGF (ψSL − ψS0 ) − 2 SL

kT Co (ψSL − ψS0 ) q   β(ψoL −VDS ) βψo0 + tSi kT ni e −e

(4)

where FS is the electric field at the surface, and the term “2” comes from the symmetry. An equivalent to the Pao–Sah’s equation for the SOI MOSFET may be obtained by substituting (4) into (3), which yields the following generalized two integral formulation for the drain–current: W = 2µ L

2kT ni β(ψo −V ) e εs

+4

where F is the electric field. Since n
ni and there is no fixed charge in the undoped body, QI can be taken as being the total charge in the semiconductor:

ID

where

ψo

QI = 2εs Fs = −2Co (VGF − ψS )

133

(7)

(9)

where ψS0 , ψo0 , ψSL , and ψoL are obtained from the numerical solutions of (1) and (2) at the source (V = 0) and at the drain (V = VDS ). The last term in (9) is negligible for all practical cases [44]. 2) Taur et al. Model: Introducing a new auxiliary variable βT into the double integral in (6), Taur et al. [36] obtained the following expression for the drain–current of DG SOI MOSFETs: ID

 2 W εs kT = 16µ L tSi q   1 2 β − βT2 0 + βT 0 tan (βT 0 ) × 2 TL εs − βTL tan (βTL ) + tSi Co   2  2 2 2 × βT 0 tan (βT 0 ) − βTL tan (βTL )

(10)

where βT 0 and βTL are the corresponding values of βT evaluated at the source (V = 0) and drain (V = VDS ), respectively,

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and are obtained from the numerical solution of the following equation:

C. Correlation Between Charge and Surface Potential-Based Models

q (VGF − VO − V ) 2kT   2εs = ln(βT ) − ln (cos (βT )) + βT tan (βT ) tSi Co

We will show in this section that surface potential-based models can easily be transformed into charge-based models for undoped MOS devices. Evaluating (1) and (5) at the source and drain ends yields   kT Q2IL β(ψSL −VDS ) ln e − (15) ψoL = VDS + q 8kT ni εs   kT Q2I0 βψS0 ln e ψo0 = − . (16) q 8kT ni εs

(11)


where VO = (2kT /q) ln((2/tSi ) 2εs kT /q 2 ni ). The parameter βT is dimensionless, and its values are in the range of 0 < βT < (π/2). It is important to point out that βT can be related to the charge coupling factor α between the two gates, defined in (8) and originally proposed by Ortiz-Conde et al. [44] as 

βT2

kT ≡ −α/ 4 q tSi

2 .

(12)

Substituting (8) into the above equation, and after some algebraic manipulations, yield the following identities:  2 n /2ε kT eβ(ψo −V ) β = (t /2) q and tan(βT ) = Si i s √T β(ψ −ψ ) S o e − 1. Using these identities, one can prove that Taur et al. model, given in (10), is equivalent to Ortiz-Conde et al. model, given in (9). B. Charge-Based Models Since there is no depletion charge in an intrinsic material, the inversion charge is equal to the total charge in the undoped channel. Thus, (5) allows for the correlation between the inversion charge and the surface potential. At the source end, QI = QI0 and ψS = ψS0 . Analogously, at the drain end, QI = QIL and ψS = ψSL . Two different charge-based models proposed by He et al. [35] and Sallese et al. [46] will now be reviewed. 1) He et al. Model: The following expression for the drain–current was developed by He et al. [35]: ID = µ

W L





Q2IL − Q2I0 2kT (QIL − QI0 ) − q 4Co

 .

(13)

It was developed based on the approximation tSi q ni eβ(ψo −V )  (εs /tSi )(kT /q) and the use of an empirical smoothing function. It can be shown that (13) is not equivalent to the two surface potential-based models discussed in Section III-A. 2) Sallese et al. Model: Sallese et al. presented the following expression for the drain–current [46]: ID

 2  QIL − Q2I0 W 2kT (QIL − QI0 ) − =µ L q 4Co   2  kT εs qtSi (QIL − QI0 ) +8 ln 1 − . q tSi 8εs kT

(14)

This was derived based on the approximation α ≈ −(2QI /βεs tSi ).

The surface potential-based model given in (9) can be transformed into a charge-based model by combining (9), (15) and (16):    W 2kT 1 1 tSi (QIL − QI0 ) − ID = µ + L q 4 Co 2εs   × Q2IL − Q2I0 + tSi kT ni eβVGF  Q   QI0    β 2CIL −V β DS o − e 2Co × e . (17) We wish to point out that the above charge-based equation is completely equivalent to the surface potential-based current equations given by (9) and (10). In addition, the first two terms of (17) correspond, for the case of vanishing tSi , to He et al. model given in (13). These two terms also correspond, for the case of vanishing tSi , to the first two terms of Sallese et al. model given in (14). The third term of Sallese et al. model in (14) is an improvement over He et al. model. Therefore, both He et al. and Sallese et al. models are in fact simplified versions of (17), whose accuracy will be illustrated later. D. Comparison of Charge and Surface Potential-Based Models Here, various compact models for the symmetric MOS device will be compared and their accuracies verified. The Ortiz-Conde et al. model in (9) (hereafter called the analytic model) was essentially derived from the generalized formulation without additional approximations and should produce the same results as those calculated first from numerically integrating the carrier charge along the channel in (4) and then the drain–current in (3). This is indeed the case, as shown in Fig. 2, where an excellent accuracy between the drain–currents calculated from the analytic model and obtained from numerical solution is demonstrated. The error of the analytic model is below 10−17 for all the voltages considered. The currents are for convenience normalized by µW/L. The surface and centerof-film potentials needed in (9), and the carrier charge used for the direct numerical integration, were obtained by solving (1) and (2) iteratively. Alternatively, the surface and centerof-film potentials can also be obtained using an approximated analytical solution suggested in [28]. Figs. 3 and 4 show the normalized drain–currents as a function of gate voltage calculated from the transformed

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Fig. 2. Drain–current as a function of drain voltage for several values of gate voltage calculated using (9) (solid lines) and obtained from numerical integration (symbols).

Fig. 5. Drain–current and relative errors plotted versus gate voltage obtained from two charge-based models.

Fig. 3. Effect of semiconductor film thickness on drain–current, plotted in both the log and linear scales.

Fig. 5 depicts the drain–currents and their relative errors as a function of gate voltage calculated from the transformed charge-based model in (17) and the other two charge-based models: He et al. model in (13) and Sallese et al. model in (14). The transformed charge-based model is used as the base to determine the relative errors of the other two models. We observe in this figure that for strong conduction, both models exhibit small errors, but for weak conduction, the errors are relatively large. Moreover, Sallese et al. model in general gives a better accuracy than He et al. model. We next examine the weak- and strong-inversion currents separately. For the case of weak inversion, the first term in (9) is negligible. The third term is negative, but together with the second term gives the following weak-inversion current IDw : IDw ≈ µ

  W tSi kT ni eβψo0 − eβ(ψoL −VDS ) . L

(18)

Note that the experimentally observed drain–current increase with increasing semiconductor film thickness in Fig. 3 can be readily explained with the tSi dependence found in (18). The strong-inversion current IDS can be obtained by subtracting the weak-inversion component IDw from the total drain–current: IDS = ID − IDw . Fig. 4. Effect of gate oxide thickness on drain–current, plotted in both the log and linear scales.

charge-based model in (17) for different tSi and tox , respectively. Note that this model is completely equivalent to (9) (Ortiz-Conde et al. model) and (10) (Taur et al. model).

(19)

Fig. 6 shows the normalized ID , IDw , and IDS plotted versus gate voltage calculated from the Ortiz-Conde et al. model to illustrate their relative importance. Clearly, the total currents for the above and below threshold operations can be approximated by IDS and IDw , respectively.

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and C0f and C0b are the front and back oxide capacitances per unit area. Depending on the value of αn (i.e., positive, negative, or zero), the integration term in (20) can be carried out analytically to yield three different solutions for the potential [26]. In addition, two possible cases with respect to the electric field exist [48]: 1) The electric field vanishes inside the silicon film at the point where the channel potential reaches an extremum, ψ(x = x0 ) = ψo and 2) the electric field is always positive inside the silicon film. A. αn is Negative Fig. 6. Total strong-inversion and weak-inversion drain–currents calculated from (9).

IV. DESCRIPTION OF POTENTIALS FOR ASYMMETRIC DEVICES For the generalized case of asymmetric devices, the electric field may not vanish inside the semiconductor film [25], [47], [48]. Therefore, it is not convenient to select the origin of the x-axis at the center of the silicon. For this case, we select the origin of the x-axis at the front surface and focus on the variable α, defined in (8), instead of ψo , as a key parameter in the analysis. The asymmetry could be due to any of the following conditions: different flatband voltages at the two gates, different oxide thicknesses, and/or different gate biases. For simplicity, the distance is normalized with respect to the silicon thickness tSi , and both ψ and V are normalized to the thermal voltage (1/β), so we get xn = x/tSi , ψn = βψ, ψsfn = βψsf , ψsbn = βψsb , VGfn = βVGF , VGbn = βVGb , and Vn = βV . Integrating (7) from an arbitrary point x to the front surface, we obtain ψ

sfn



xn = ψn

dψn αn + K exp(ψn − Vn )

(20)

where αn ≡ α(βtSi )2 , K ≡ (2q ni tSi β/CSi ) and CSi ≡ (εs /tSi ) is the capacitance of the silicon. Combining the front boundary condition, VGF = ψsf + (εs /Cof )Fsf , and the expression in (7) evaluated at the front surface yields the normalized αn 

Cof CSi

2 (VGfn − ψsfn )2 − K exp (ψsfn − Vn ) = αn .

(21)

Analogously, combining the back boundary condition, VGb = ψsb − (εs /Cob )Fsb , and the expression in (7) evaluated at the back surface yields 

Cob CSi

2 (VGbn − ψsbn )2 − K exp(ψsbn − Vn ) = αn (22)

where VGF and VGb are the front and back gate-to-source voltages with the corresponding flatband voltages included,

This case is analogous to the dual-gate MOSFET presented by Taur [34]. The integration of (20) for this case gives    2 αn xn = √ exp(−ψn + Vn ) − arcsin K −αn   αn − arcsin exp(−ψsfn + Vn ) . (23) − K Since the argument of arcsin should be between zero and one, we obtain the following condition:  αn exp(−ψn + Vn ) < 1. 0< − (24) K A plot of xn (ψn ) will always present a point x0n at which the electric field vanishes and the channel potential reaches an extremum, ψ(xn = x0n ) = ψ0n . For the particular case of a symmetric DG MOSFET with the same bias applied to both gates, the point will be at the center of the semiconductor: x0n = 0.5. Since ψ0n is the minimum value of the potential, it can be obtained by evaluating (24):  α  n . (25) ψ0n = Vn + ln − K Therefore, two more cases are possible: 1) The point x0n does not exist inside the semiconductor, i.e., 1 < x0n , and the electric field does not vanish; and 2) the point x0n exists inside the semiconductor, i.e., 0 < x0n < 1, and the electric field changes sign. 1) αn is Negative and x0n > 1: For this case, we can evaluate (23) at ψn = ψsbn and x0n should be a unity    2 αn 1= √ exp (−ψsbn + Vn ) − arcsin K −αn   αn − arcsin exp (−ψsfn + Vn ) . (26) − K The simultaneous solution of (21), (22), and (26) allows one to find ψsfn , ψsbn , and αn , when αn < 0 and x0n > 1. 2) αn is Negative and x0n < 1: For this case, x0n can be obtained by evaluating (23) at ψn = ψ0 and using (25)    π 2 αn x0n = √ − arcsin exp(−ψsfn +Vn ) . − K −αn 2 (27)

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Analogously, (1 − x0n ) can be obtained by evaluating (23) at ψn = ψ0 and replacing ψsfn with ψsbn (1 − x0n ) = √

2 −αn

   π αn − arcsin exp(−ψsbn + Vn ) × − . (28) 2 K Adding the two previous equations    2 αn 1= √ exp(−ψsbn + Vn ) − arcsin K −αn   αn +arcsin exp(−ψsfn +Vn ) − . (29) K Fig. 7. Effect of front- and back-gate biases on the drain–current of symmetric DG MOSFET calculated from the analytic model (33) (lines) and simulated from Atlas device simulator (symbols).

B. αn is Positive The integration of (20), in the case of positive αn , gives    αn 2 exp(−ψn + Vn ) xn = √ arcsinh K αn   αn − arcsinh exp(−ψsfn + Vn ) . (30) K Evaluating the previous equation at ψn = ψsbn    αn 2 exp(−ψsbn + Vn ) 1= √ arcsinh αn K   αn − arcsinh exp(−ψsfn + Vn ) . (31) K

equation in (6), without making any additional approximations, into the following explicit expression for the drain–current of asymmetric DG SOI devices: ID = µ

   W 2 Cof VGf + (ψsfL −ψSf0 ) L β   εs tSi 1 2 2 (α0 − αL ) − ψsfL −ψSf0 + 2 2  + Cob

The simultaneous solution of (21), (22), and (31) allows one to obtain ψsfn , ψsbn , and αn , when αn is positive.

−

C. αn is Zero The integration of (20), for a zero αn , gives   exp(−ψn + Vn ) exp(−ψsfn + Vn ) −2 . xn = 2 K K

 2 VGb + (ψsbL −ψsb0 ) β  1 2 2 ψsbL −ψsb0 2



 − ni kT tSi (βVD +exp(−βVD )−1)

(33)

(32)

In this section, we will review existing models for the drain–current of asymmetric DG MOSFETs.

where ψSf0 , ψSfL , ψSb0 , ψSbL , α0 , and αL are obtained from the numerical solutions described in the previous section. This equation is valid for any asymmetric condition as long as the electric field does not vanish inside the film. The last term in (33) is negligible for all practical cases [44]. Fig. 7 shows the drain–current versus front-gate voltage calculated using (33) (lines) and simulated from ATLAS device simulator (symbols) for three different back-gate voltages. The device considered consists of a front-gate oxide thickness of 2 nm, back-oxide thickness of 40 nm, and semiconductor film thicknesses of 10 nm. Excellent agreement between the analytic model in [26] and simulation is illustrated.

A. Ortiz-Conde et al. Model

B. Lu and Taur Model

Following the idea of Pierret and Shields [45] for bulk MOS devices, Ortiz-Conde et al. [26] transformed the double integral

Lu and Taur [25] analyzed the DG MOS devices having asymmetry arising from the different flatband voltages at the

This result can also be obtained by evaluating the limits of the two previous solutions, (23) and (30), when αn = 0. This is important because it is the case of a bulk device. It should be pointed out that both solutions, (23) for αn < 0 and (30) for αn > 0, are completely equivalent. This can be verified by using the complex identity arcsin(Z) = i arcsinh(iZ), where i is the imaginary number and Z is a dummy variable. V. DRAIN–CURRENT MODELS FOR ASYMMETRIC DEVICES

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two gates and obtained the drain–current by numerically integrating (3). This approach is less analytic but yields results similar to those obtained from the model in (33). C. Roy et al. Model Roy et al. presented the following semi-empirical expression for the drain–current of the asymmetric device [49]: W ID = µ L



 2  Q −Q2I0 2 (QI0 −QIL )− IL β 4Co +

    4 εs 1 Vdm + β tSi β 

βQI0 4εs + × ln Co tSi Co



1 Vdm + β



    4 εs 1 − Vdm + β tSi β  × ln

βQIL 4εs + Co tSi Co

  1 Vdm + β

!   1 1 QIL 2 + 2 − CoVdm arctan √ 2 2 1+λ 2 2βCo Vdm √

!   1 1 Q I0 2 arctan √ − 2 − Co Vdm 2 2 1+λ 2 2βCo Vdm √

(34) and Vdm ≡ where λ ≡ (εs /tSi )/((εs /tSi ) + Co ) (VGF − VGb )/2. This equation was obtained from combining several different regional expressions via an interpolation function in order to construct a continuous analytical formulation for a wide range of bias conditions. VI. CONCLUSION A comprehensive review of physics-based compact models for symmetric and asymmetric DG SOI MOSFETs has been presented in this paper. The fundamental issues related to the surface potential and current formulations were first discussed, and the existing compact models for the DG SOI devices were then reviewed and compared. These core models can in general be categorized into either surface potential or charge based, but some similarities do exist among some of the models developed from the two different approaches. Quantum mechanical modeling was not included in this paper, but such a subject can be found in the extensive references cited in this paper. This paper should provide a valuable knowledge to researchers who are engaged or interested in the modeling, design, and characterization of the increasingly important multigate SOI MOS devices.

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Adelmo Ortiz-Conde (S’82–M’85–SM’97) was born in Caracas, Venezuela, on November 28, 1956. He received the B.S. degree in electronics from Universidad Simón Bolívar, Caracas, Venezuela, in 1979 and the M.E. and Ph.D. degrees from the University of Florida, Gainesville, in 1982 and 1985, respectively. His doctoral research was in the area of semiconductor device modeling under the guidance of Prof. J. G. Fossum. From 1979 to 1980, he served as an Instructor with the Department of Electronics at Universidad Simón Bolívar, Caracas. In 1985, he was a member of the Technical Staff of Bell Laboratories, Reading, PA, where he was engaged in the development of high-voltage integrated circuits. Since 1987, he has been with the Department of Electronics at Universidad Simón Bolívar and he was promoted to Full Professor in 1995. He was on sabbatical leave with Florida International University, Miami, from September to December 1993, and with the University of Central Florida (UCF), Orlando, from January to August 1994, and again from July to December 1998, and with CINVESTAV, Mexico City, Mexico, from October 2000 to February 2001. He has authored one textbook, Analysis and Design of MOSFETs: Modeling, Simulation and Parameter Extraction (Kluwer, 1998), 73 refereed journal articles (including four invited review articles), and 59 papers (including 8 invited papers) in international conference proceedings. His current research interest includes the modeling and parameter extraction of semiconductor devices. Dr. Ortiz-Conde is a member of Eta Kappa Nu, Tau Beta Pi, Phi Kappa Phi, and the Galilean Society. He is an EDS Distinguished Lecturer, and he is the Chair of IEEE’s CAS/ED/PE Venezuelan Chapter. He was the Editor for Region 9 of the IEEE EDS Newsletter from 2000 to 2005. He is a member of the Editorial Advisory Board of Microelectronics and Reliability. He was in the Engineering and Applied Sciences Commission of the National System for the Promotion of Research. He has served as Reviewer for national and international journals and conferences. He was the General Chairperson of the first IEEE International Caracas Conference on Devices, Circuits, and Systems in 1995, the Technical Chairperson of the second, fourth, and fifth editions of this conference in 1998, 2002, and 2004, respectively, and the Chairperson of the Steering Committee in 2000.

Francisco J. García-Sánchez (M’76–SM’97) was born in Madrid, Spain. He received the B.E.E., M.E.E., and Ph.D. degrees in electrical engineering all from Catholic University of America, Washington, DC, in 1970, 1972, and 1976, respectively. Since 1977, he has been a Faculty Member with the Electronics Department, Universidad Simón Bolívar (USB), Caracas, Venezuela, where he is currently a Full Professor. He has held several directive academic and administrative positions with USB. He has performed research on polycrystalline compound semiconductors, their thin- and thick-film deposition techniques, and their use in photovoltaic solar cells and sensors, electrical characterization and modeling of biological tissues, ceramics and other composite materials. In 1979, he founded the USB’s Solid State Electronics Laboratory. Currently, his research interests lay mainly in the area of semiconductor device modeling, especially MOSFETs. He has published over a hundred articles, including invited, in national and international refereed technical journals and conferences. He is the coauthor of a book on MOSFET modeling, and has been the editor of specialized collective books. Prof. García-Sánchez has been the recipient of several awards for excellence in research. He has been actively involved, both locally and internationally, in the promotion, planning, direction, administration, and evaluation of R&D endeavors, as well as in editorial responsibilities and conference organization activities. Since 1994, he has been part of the organization of IEEE International Caribbean Conference on Devices, Circuits and Systems (ICCDCS). He is a member of the Venezuelan Association for the Advancement of Science, a founding member and past Vice-President of the Galilean Society, and an EDS Distinguished Lecturer. He is a past Chair of IEEE’s CAS /ED/PE Societies Venezuela Joint Chapter. Currently, he is an elected member of the EDS Administrative Committee, a member of EDS Graduate Student Fellowship Subcommittee, the Vice-Chair of EDS Subcommittee for Regions and Chapters for Latin America (SRC-LA), and a member of IEEE Undergraduate and Graduate Teaching Awards Committee.

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Juan Muci was born in Valencia, Venezuela, on July 29, 1957. He received the B.S. degree in electronics engineering from Universidad Simón Bolívar, Caracas, Venezuela, in 1979 and the M.S. degree in electrical engineering from Pennsylvania State University, State College, where he worked on gated diode modeling, in 1983. He later joined the faculty with the Electronics Department at the Universidad Simón Bolívar, where he is currently an Associate Professor. His current research interests include semiconductor device modeling and characterization. Prof. Muci is a member of Tau Beta Pi and Eta Kappa Nu.

Juin J. Liou (M’87–SM’92) received the B.S. (with honors), M.S., and Ph.D. degrees in electrical engineering from the University of Florida, Gainesville, in 1982, 1983, and 1987, respectively. In 1987, he joined the Department of Electrical and Computer Engineering, University of Central Florida (UCF), Orlando, where he is currently a Professor. He has filed 3 patents, and has published 6 textbooks (another in progress), 1 book chapter, more than 200 journal papers (including 13 invited articles), and more than 150 papers (including 50 keynote or invited papers) in international and national conference proceedings. Dr. Liou was awarded the UCF Distinguished Researcher Award three times (1992, 1998, and 2002), UCF Research Incentive Award two times (2000 and 2005), and IEEE Joseph M. Biedenbach Outstanding Engineering Educator Award in 2004 for his exemplary teaching, research, and international collaboration. His other honors include fellow of the Institution of Electrical Engineers, IEEE Electron Device Society (EDS) Distinguished Lecturer, and Cao Guang-Biao Endowed Professor of Zhejiang University, China. He is the IEEE EDS Vice-President for Regions/Chapters and an elected member of IEEE EDS Administrative Committee.

Slavica Malobabic (S’00) was born in Belgrade, Serbia and Montenegro in 1978. She received the Professional Electronics Engineer degree in 2005, and the M.E. (with honors) degree from Universidad Simón Bolívar, Caracas, Venezuela. She is currently working toward the Ph.D. degree in electrical engineering at the University of Central Florida, Orlando. She has coauthored two articles in specialized technical journals and four in international conferences. Ms. Malobabic received the IEEE Electron Devices Society’s 2005 Region 9 Outstanding Student Paper award. She has done a volunteer work for three IEEE sponsored conferences as a part of publications and meeting facilities committees.