A Stereo Audio Σ∆ ADC Architecture with Embedded SNDR Self-Test Luis Rolíndez1,2, Salvador Mir2, Jean-Louis Carbonéro1, Dimitri Goguet1 and Nabil Chouba3 1 STMicroelectronics, 850 rue Jean Monnet, Crolles, France 2 TIMA Laboratory, 46 Avenue Félix Viallet, Grenoble, France 3 STMicroelectronics, 2083 La Gazelle Ariana, Tunis, Tunisia

Abstract In this paper we present a new architecture for audio Analog-to-Digital Converters (ADCs) that includes a Built-In Self-Test (BIST) technique for the test of the Signal-to-Noise and Distortion Ratio (SNDR). A periodical binary stream is generated in the chip in order to stimulate the converter. The reuse of the bandgap circuit already existing in the converter allows us to generate the test stimulus with a very small analog area overhead. The output response analysis is performed by means of a sinewave fitting algorithm. The reuse of the digital filter already existing in the converter allows us to generate a synchronized reference signal necessary for the fitting algorithm. The BIST technique is equivalent to a standard test carried out with a sinusoidal signal at -12 decibels Full-Scale (dBFS). The total test time is 60 ms and the estimated BIST overhead area is 7.5% of the whole stereo converter area in a 0.13 µm CMOS technology. Experimental results show that the correlation between the embedded self-test and a sinusoidal standard test is excellent, with a SNDR error smaller than 1 dB.

1.

Introduction

In order to satisfy the rising demand for high quality audio devices, the performances of Sigma-Delta Analog-toDigital Converters (Σ∆ ADCs) are continuously improving with larger modulator bandwidths and higher dynamic ranges. As the performances of these circuits increase, its test is in turn more difficult and costly. Built-In Self-Test (BIST) techniques can reduce this cost by integrating the test approach in the design phase. In the last years, an intense research effort has been carried out in order to find BIST solutions for ADCs. The Oscillation-based Built-In Self-Test (OBIST) was proposed in [1] for the calculation of the input transition voltages and non-linearity errors. The main advantage of this method is that we do not need to generate an analog input stimulus for the test. However, it does not measure dynamic parameters and it takes a long test time for high-resolution converters. The oscillation-based BIST has also been applied to the test of Σ∆ modulators [2], where the modulator is reconfigured to be an oscillator. Both the frequency and the amplitude of the oscillation are measured in order to separate faulty-circuits from fault-

free ones. The need to modify the circuit and the sensibility to process variations can deteriorate the quality of this BIST approach. Other authors [3,4,5,6] have proposed the estimation of the leakage in the modulator integrators, which is directly related to the quantization noise present in the bandwidth of the modulator at its output. Additionally, the same approach is used in [6] for the estimation of the settlingtime. These approaches do not allow for a complete validation of the modulator and additional tests may be necessary. Furthermore, in [3] and [4] large digital resources are required. The histogram-based technique has also been applied to the BIST of ADCs in [7]. However, only static information is obtained and long test times are necessary when the number of ADC bits increases. Moreover, a high-precision ramp or sinusoidal signal generator is required to stimulate the converter. Additionally, a large digital overhead area is needed to save the experimental histogram and to memorize the theoretical histogram in the case of sinusoidal test signal. These digital resources can be drastically reduced by using the time-decomposition technique proposed in [8], but this considerably increases the test time. A proposal that overcomes the problem concerning the high-precision analog stimulus was presented in [9]. A staircase-like exponential waveform replaces the linear ramp. This waveform is easily generated from Pulse Width Modulation (PWM) waveforms. The output response analysis is performed by means of a third-order best-fitted polynomial [10]. Experimental results have shown that this technique can measure the Total Harmonic Distortion (THD) of ADCs with a precision of 13 bits. Large dynamic errors (for example, sparkles) cannot be detected with this strategy. Additionally, it is not possible to measure noise. The use of Σ∆-modulated binary streams to generate onchip high-precision analog test stimuli was proposed in [11]. These binary stimuli can be generated by integrating a Σ∆ digital oscillator or by periodically repeating an optimized bit-stream. However, there are two issues that need to be considered. Firstly, a 1-bit Digital-to-Analog Converter (DAC) is needed to apply the stimulus to an analog block. This converter has to be 2 or 3 bits more precise than the Circuit Under Test (CUT) [12]. Any noise

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coming from this DAC will be directly coupled to the input of the CUT. Secondly, the out-of-band quantization noise present in the bit-stream can disturb the functionality of the CUT. In [11,13] an on-chip filter has been implemented to remove this quantization noise, but the quality of the analog signal was strongly reduced. In [14], the anti-aliasing filter present in the Σ∆ ADC was reused to filter the high-frequency noise, but this filter must be capable of accepting rail-to-rail input levels without causing distortions, which dramatically complicates its design and it is not feasible in high-resolution ADCs. To overcome these drawbacks, in [15] a softwaregenerated binary stream was directly sent to the input of the analog modulator, in the same way as the output binary feedback is injected in every Σ∆ modulator. In order to avoid the saturation of the modulator, the stimulus has to be attenuated. For the injection of this stimulus, it was necessary to use an additional high-precision voltage reference [16]. In this paper, we consider as test stimulus a periodic bit stream. We reuse the high-precision bandgap voltage circuit already existing in the converter to generate both the modulator reference voltage and the attenuated voltage needed for the stimulus injection in BIST mode. In this way we can obtain a very high quality test stimulus with a reduced area overhead. In order to complete the BIST technique, we have to carry out the output response analysis. Methods like the Fast Fourier Transform (FFT) analysis or the digital filtering permit to calculate the Signal-to-Noise Ratio (SNR), but these methods require large digital resources that considerably increase the cost of the BIST. Another possibility is the integration of a sine-wave curve-fitting algorithm [14] for the calculation of the Signal-to-Noiseplus-Distortion Ratio (SNDR). However, two reasons make difficult the implementation of this algorithm on chip. Firstly, the values of a high-precision digital sine and cosine must be calculated or be available in a look-up table. Secondly, we do not know a priori the phase of the output response, which is quite difficult to calculate. Aiming at reducing the complexity of the sine-wave fitting algorithm, we have proposed in [17] to reuse the digital decimation filter already existing in the converter to generate a reference signal synchronized with the output response. This strategy reduces the digital overhead area, but we still need a memory to save both signals: output response and reference signal. In this paper we propose the use of the hardware redundancy existing in stereo audio converters. Taking advantage of the existence of two identical channels in a stereo converter, we use the right channel digital decimation filter to test the left channel converter and vice versa. In this way, we avoid the need for a memory and the digital overhead area for the BIST is significantly decreased. Furthermore, we show in this paper that this

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integrated test technique is equivalent to a conventional test carried out with a sinusoidal signal at -12 dBFS (decibels Full-Scale). This paper is organized as follows. In Section 2 we detail the stereo converter architecture proposed for the calculation of the SNDR and we explain the design modifications required for the BIST implementation. Simulation results illustrated in Section 3 show the capacity of the embedded self-test strategy to measure the converter SNDR. In Section 4 we present experimental results that confirm the results obtained by simulation. The correlation between the embedded self-test and a classical sinusoidal test is excellent, with a SNDR error smaller than 1 dB. In Section 5 we discuss the limitations of the proposed BIST technique and we describe the applications where it can be used. Finally, conclusions are given in Section 6.

2. Embedded SNDR Self-Test Technique for Stereo Σ∆ ADCs 2.1

BIST Architecture

Figure 1 shows the architecture of a stereo Σ∆ ADC incorporating the BIST strategy. The converter works with input signal frequencies up to 22.05 kHz. The sampling frequency of the converter is 12.288 MHz and the digital output rate is 48 kHz. In normal mode, a 2nd order analog Σ∆ modulator converts the input signal into a 1-bit stream and next a four-stage digital decimation filter eliminates the high-frequency noise contained in the binary stream to provide a 16-bit digital output. Table 1 shows the five main noise power contributions that limit the resolution of the modulator: KT/C noise, opamp noise, voltage reference noise, quantization noise and distortion. The total power noise in the audio bandwidth is equal to 248 pV2. Considering that the full range of our modulator is 1.44 Vpp, the modulator SNDR is equal to 96.78 dB. In BIST mode, a bit-stream that has been saved in a shift register is periodically repeated to generate a binary stimulus with a precision of 19-bit in the audio bandwidth. This stimulus is injected into one of the modulators (Right channel, for example) by reusing the bandgap reference circuit existing in the converter. At the same time, the same binary stimulus is sent to the input of the symmetrical decimation filter (Left channel, in our case). This filter eliminates the high-frequency noise present in the binary stimulus to generate a high-precision (19-bit) digital sinusoidal that is used as reference signal for the output response analysis performed by means of a sinewave fitting algorithm. The synchronization of both signals (output response and reference signal) is possible thanks to the z-2 digital block which introduces in the digital signal the same delay that the analog test signal This undergoes in the 2nd order modulator. synchronization allows us to avoid the calculation of the phase and the frequency of the output response,

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Figure 1

Self-testable 16-bit Stereo Σ∆ ADC Architecture

Noise Source

Noise Power Contribution

KT/C Noise Voltage Reference Opamp Flicker Noise Opamp White Noise Quantization Noise+Distorsion Total Inband Noise Power

43.1 pV 12.1 pV2 88.2 pV2 50.0 pV2 2 55.2 pV 2 248.6 pV

TABLE 1

2

Noise Budget

calculation that takes very large digital resources in a standard sine-wave fitting approach [18]. Figure 2 shows the spectrum of the 2252-bit stream used as stimulus in the BIST mode. This stimulus is obtained by the periodical reproduction of an optimized binary train recorded from the output of a software 3rd order Σ∆ modulator [17]. When we clock this stimulus at the

Figure 2

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Spectrum of a 2252-bit stream

sampling frequency, the test signal is at fstimulus = fsampling /2252 = 5456 Hz, with the first three harmonics (10912 kHz, 16369 Hz and 21825 Hz) falling in the audio bandwidth. The quality of the stimulus is better than 19-bit (117.23 dB in terms of Signal to Total Harmonic Distortion power ratio) in the audio bandwidth, which allows us to use it as test stimulus for a 16-bit ADC. We inject the test binary stimulus into the analog modulator by simply adding a path, identical to the path that inserts the feedback binary stream (Figure 3). No extra capacitors are needed and the noise performance of the modulator (KT/C noise and input-referred noise operational amplifier) is consequently not modified. The only concern is the need for two new high-precision noisefree voltage references (VBIST+ and VBIST-) to inject the attenuated stimulus. But these two new voltages can be easily generated by reusing the high-precision bandgap

Figure 3

Modulator Input Stage for BIST

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Figure 4

Bandgap circuit with generation of BIST reference voltages

reference already existing in the converter for the generation of VREF+ and VREF-. Figure 4 shows the bandgap voltage architecture used in our circuit, with a very low 2 inband noise (12.1 pV , see Table 1). By using additional external passive components (three resistors and one capacitor) we can generate the BIST voltages with very low overhead area: only two additional analog pads are added. The decoupling capacitors between VREF+/ VREFand VDD/GND are anyway required for optimal performances of the converter. The converter analog area (bandgap + modulator) is 1.03 mm2 and the analog overhead area for BIST (just two analog pads) is consequently only a 2.3 % of the whole analog part. The only new noise contribution comes from the additional BIST voltages references. However these voltages are generated from the same bandgap circuit but with attenuated values (∆VBIST=0.3125·∆VREF), so the new noise contribution in BIST mode (Pn,BIST=1.17 pV2) is negligible.

Figure 5 Spectrum of the reference signal obtained with the decimation filter

th

The digital filter includes a 4 order sinc FIR (FiniteImpulse Response) filter in the first stage, two IIR (Infinite-Impulse Response) elliptic filters in the second and third stages, respectively, and finally a FIR compensator filter. When designing this filter, a special design effort is necessary for its application to the BIST technique. Usually a 3rd order sinc filter is enough when a 2nd order modulator is used, but since we use as test stimulus a binary stream which already contains much quantization noise, we need to increase the order of this filter up to 4. Moreover, paths of 22 and 23 bits are used in the last two filter stages, when normally paths of 21 bits are large enough. This extra design effort is necessary to reuse the decimation filter for the generation of a highprecision reference signal. Figure 5 shows the spectrum of the 563-point reference signal. The quality of the signal is of 19 bits (113.89 dB in terms of S/THD) so it can be used as reference signal in the sine-wave fitting algorithm.

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2.2

Data Analysis Algorithm

For the output response analysis, we perform a sine-wave fitting algorithm, whose complexity is reduced because we have a reference signal synchronized with the test response (same frequency and phase). The number of samples M used for the analysis must respect a coherent sampling [19]. We need to sample an exact number of periods from the input test signal and also we have to avoid taking samples that contain the same information. Taking into account that the output sample rate is equal to the sampling frequency divided by the decimation factor DEC=256, the ratio between the input test signal and the output rate is given by:

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f sampling

f stimulus f output - rate

=

f sampling

N

DEC

563

DEC = N

(1)

By replacing the values corresponding to our case we have: Toutput ⋅ 563 = Tstimulus ⋅ 64

(2)

Equation (2) means that, in order to respect a coherent sampling, we need to sample 563 samples from the output converter, which corresponds to 64 periods of the input signal. The test time needed for the sine-wave fitting calculation with 563 samples is about 30 ms. In a first step, we calculate the DC value of the test response signal: DC =

1 563 ⋅ ∑ S out [i ] 563 i =1

(3)

In a second step we perform a point-by-point correlation between the test response signal and the reference signal. By considering that the amplitude of the filtered sinusoidal reference signal is AmpREF, the amplitude of the test response signal is given by: Amp = 2 ⋅

563 1 1 ⋅ ⋅ ∑ Sout [i ] ⋅ S ref [i ] (4) 563 Amp REF i =1

Once we know the DC value and the amplitude of the test response signal we can fit the reference signal to match the response signal: S ref,fitted [i ] = Amp ⋅

1 ⋅ S ref [i ] + DC Amp REF

(5)

The fitted reference signal can now be compared with the test response to obtain the power of the error:

KTC Noise 43.1 pV²

∑ (Sout [i ] − S ref, fitted [i

Perror = i =1

563

2

])

(6)

All constant values in Eqs. (3), (4), (5) and (6) are known a priori and can be implemented as coefficient taps. In the simulations we have calculated the logarithm of the power ratio to obtain a measure of the SNDR in dB, but in the real circuit implementation we would use digital signatures. The power of the noise and the power of the signal have to be inside the limits defined by these signatures. The calculations performed in this sine-wave curve-fitting algorithm require an adder and a multiplier of 25 bits. Considering that the output rate is very low (48 kHz), the additional digital sources needed for the output response analysis are very small. The estimated silicon area of the original decimation filter is 0.5 mm2. The total digital overhead area for the BIST (filter modification, analysis, binary stimulus generation and control logic) is estimated to be less than 20% of the digital block, that is to say, less than 0.1 mm2. Considering both the analog and the digital blocks, the estimated total overhead area for the converter BIST is 7.6 %. With the new technologies, where the digital blocks are ever smaller, the BIST strategy can be even more areaeffective, because the overhead area is mainly digital.

3.

Simulation Results

In order to demonstrate the capability of this technique, we have introduced in the 2nd order analog modulator model some of the non-idealities that appear in a switchedcapacitor implementation (Figure 6), as it was proposed in [20]. KT/C noise, input-referred operational amplifier noise, bandgap noise, integrator leakage, integrator output clipping, power supply noise and non-linear capacitors

Opamp Flicker Noise 88.2 pV² Comparator

Input

Non-Linearity Sampling Capacitors

Non-Linearity Integration Capacitors

Opamp Thermal Noise 50 pV²

Reference Voltage Noise 12.1 pV²

DAC Output 2.2 Vpp

Figure 6

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nd

2

order analog modulator model with non-linearities

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(dB) Σ∆ Modulator Non-idealities

SNDRADC [A] (-0 dBFS)

SNDRADC [B] (-12 dBFS)

SNDRBIST [C]

BIST Error [C] - [A]

BIST Error [C] - [B]

Free-Fault Modulator NoiseKTC (C=0.1pF) NoiseKTC (C=0.05pF) NoiseOPAMP=20µVrms NoiseOPAMP=100µVrms NoiseBANDGAP=50µVrms NoiseBANDGAP=500µVrms 1ST Integrator Leakage (Lg=0.995) 1ST Integrator Leakage (Lg=0.99) 1ST Integrator Leakage (Lg=0.98) 1ST Integrator Leakage (Lg=0.95) β2=-0.02% β2=-0.002% β3=-0.04% β3=-0.004% α2=-0.02% α3=-0.05% Vsat=±1.50V (instead of ±1.60V) Vsat=±1.25V (instead of ±1.60V)

96.66 90.44 87.74 95.20 80.40 94.43 77.36 96.19 94.20 91.23 85.72 72.00 90.78 70.53 91.28 77.67 73.73 72.34 46.78

98.68 90.62 87.88 96.03 80.39 95.23 77.32 98.34 97.57 94.98 88.18 92.57 98.43 92.77 98.73 96.80 98.41 98.44 98.53

98.07 90.67 87.98 96.25 80.49 95.02 77.39 96.53 93.49 88.63 81.66 90.65 97.70 86.98 97.69 98.10 97.84 98.04 63.86

1.41 0.23 0.24 1.05 0.09 0.59 0.03 0.34 -0.71 -2.60 -4.06 18.65 6.92 16.45 6.41 20.43 24.11 26.06 17.08

-0.61 0.05 0.10 0.22 0.10 -0.21 0.07 -1.81 -4.08 -6.35 -6.52 -1.92 -0.73 -5.79 -1.04 1.30 -0.57 -0.40 -34.67

Table 2

deteriorate the modulator resolution. In Table 2 we show the simulation results obtained for these typical modulator non-idealities. These results have been obtained in Matlab@ because transistor-level simulations take too long. The converter SNDR obtained with the BIST technique (column [C]) is compared with the SNDR values obtained by means of standard tests carried out with sinusoidal signals at -0 dBFS (column [A]) and at -12 dBFS (column [B]). In the cases [B] and [C], the measured SNDR has been corrected taking into account the attenuation (-12 dB) applied to the stimulus. By comparing the BIST results [C] with the SNDR values obtained with a full-scale sinusoidal test [A], we can observe that the accuracy of the measurement error is very much dependent on the type of fault injected. The technique gives a very precise estimation of the SNDR when introducing different noise sources (KT/C noise, input operational amplifier noise and bandgap reference noise). For all the different noise levels, the BIST error is always less than 1.5 dB. Consequently, the technique provides a very good noise measurement. The degradation of the integrator leakage (Lg<1) is also detected by the BIST. The estimation of the SNDR is very good for integrator leakages close to 1 (Lg= 0.995 and Lg= 0.99) with BIST errors again less than 1 dB. For larger integrator leakages (Lg= 0.98 and Lg= 0.95) the measurement error is greater (up to 4.06 dB) because the SNDR obtained with the BIST technique is smaller. This BIST error is due to two reasons. First, when using a binary stream instead of a sinusoidal input signal, some of the high-frequency quantization noise present in the test stimulus is modulated to the audio bandwidth if the

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BIST simulation results

integrator leakage degrades. Second, the leakage modifies the delay undergone by the signal when passing through the analog modulator. Since the reference signal is synchronized with an output response signal that undergoes a theoretical delay of z-², large deviations of the integrator leakage produce an important reduction of the SNDR measured with the BIST. Consequently, our BIST technique has a very good capability to detect degradations of the integrator leakage. When introducing non-linearities that produce harmonic distortion (integrator output clipping and non-linear capacitors) we see that the capacity of the technique to detect distortion is reduced. Second and third order non-linearities introduced by the sampling capacitors (α2= -0.02% and α3= -0.05%) cannot be detected by the BIST technique. Due to the nature of the input signal test, coefficients α2 and α3 can modify the gain and the offset of the modulator but they cannot produce distortion when using a binary stimulus just composed of two different voltages. The BIST technique is capable of detecting strong second and third order non-linearities introduced by the integration capacitors (β2= -0.02% and β3= -0.04%) and strong integrator output clipping (Vsat= ±1.25V) but it cannot detect weak non-linarities (β2= -0.002% and β3= -0.004%) and weak integrator output clipping (Vsat= ±1.50V). In any case, the BIST errors for the case of non-linearity faults are large. The fact that the BIST stimulus is not a full-range test signal makes the harmonic distortion less important than in the case of a full-range sinusoidal test.

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If we compare now the BIST results with the SNDR values measured with a standard test carried out with a sinusoidal signal at -12 dBFS [B], we can observe that the errors are again very small (< 0.75 dB) for all the different source noise levels. For the case of integrator leakage and non-linearities, the capability of detection of the BIST technique is always better than the case of a -12 dBFS standard test. Consequently, the BIST technique can be considered as a test equivalent to the sinusoidal test at -12 dB with an improved potential to detect integrator leakage and harmonic distortion.

4.

Experimental Results

Figure 7 shows the prototype of the Σ∆ modulator that has been designed using a STMicroelectronics CMOS 0.13 µm technology so as to experimentally validate the BIST approach. This prototype includes all the analog blocks of

the Σ∆ converter. The digital blocks are emulated by means of Matlab@. In the test board (Figure 8) we have included, for comparison purposes, the possibility to test the converter either with a sinusoidal standard test or with the embedded self-test strategy. For a standard test (Figure 9.a.) we generate a highprecision test signal by means of an Audio Precision@ equipment. Before getting into the converter, we need to filter the high-frequency noise that could alias into the audio bandwidth. The modulator binary output is sampled by means of a Tektronix@ logic analyzer. The output response analysis is carried out in Matlab@ by means of a sine-wave fitting algorithm with 4 variables: amplitude, offset, phase and frequency. We need to consider the frequency as a variable because any input signal frequency shift produces a very large error in the SNDR calculated by the fitting algorithm.

Analog Power Digital Power AntiAudio Aliasing Inputs Filter

Outputs Σ∆ ••Modulato

Clk

Stimulus

Figure 7 Photograph of the Σ∆ modulator (two different versions) used in the 16-bit converter

Figure 8

Photograph of the test board

(a)

(b) Figure 9

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Test environment for (a) standard test and (b) for embedded self-test

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For the embedded self-test (Figure 9.b.), we do not need to use a high-precision test signal generator. Instead, we use the binary stream presented in figure 2 and we inject it into the converter by reusing the on-chip converter bandgap circuit. Furthermore, the anti-aliasing filter at the input stage can be removed from the test board. The reduction of the test cost is consequently very significant. The response analysis is performed by means of sine-wave fitting algorithm with 2 variables: amplitude and offset. The frequency and the phase do not need to be calculated because the output response and reference are synchronized. In this prototype the modulator binary output is analyzed off-chip with Matlab@, but in a completely integrated implementation the analysis can be performed on-chip with a very reduced overhead. Figure 10.a presents the SNDR expected by simulation and the SNDR we have measured by means of a standard test. The integration of the testing strategy has not degraded the converter performances. The measured Dynamic Range (DR) is 96.26 dB, only 3 dB less than the expected DR by simulations. This little difference can be very well explained by the jitter and the white noise present in the test board. The Figure 10.b shows the SNDR measured with a standard test and with the BIST technique. The error is very small (always smaller than 2 dB) for input amplitudes up to -12 dB. As expected by simulation results, for higher amplitudes the high-frequency quantization noise of the binary stimulus causes the saturation of the converter and the SNDR degradation. Additionally, for input amplitudes between -60 and -12 dBFS, the error is smaller that 1dB.

5.

Limitations and Discussion

The measurements presented in Section 4 were performed in only a few circuit samples on nominal test conditions:

25°C, 3.3 V power supply for the analog circuits and 1.2 V for the digital blocks. The process was slightly slow, with a current consumption smaller than expected in the typical model card. In order to experimentally determine the test yield and the defect level, we would need to test many more chips in all the process corners. Most of the additional BIST circuitry is digital. The modifications over the analog blocks are minimal: only a few additional switches are required. The self-test strategy is immune to deviations of the reference voltages generated by the bandgap circuit. In fact, any modification of the BIST voltages will cause a variation of the amplitude and offset of the stimulus. Since these parameters are calculated by the sine-wave fitting algorithm, the SNDR value measured is not affected by these deviations. For the same reason, the method is also immune to variations of the external resistors. Consequently, we can state that the yield loss should be very small. In this paper we have used a 2252-bit binary stream to generate a stimulus at 5.4 kHz. However, it is possible to change the stimulus frequency by simply varying the stream length. For example, we can generate a stimulus at 2.2 kHz by using a binary train of 4504 bits. It is also possible to apply the same approach with multi-frequency stimuli [21]. The embedded self-testing has been applied to a 16-bit 2nd order converter, but the same strategy can also be applied to other ADC architectures of higher resolution. By increasing the length of the stimulus or the order of the modulator used for the generation, we can obtain stimuli with a precision better than 132 dB [21], which is enough to extend the BIST to converters with a resolution of 19 bits. This strategy is able to measure, with an error smaller than 1 dB, the SNDR of the converter when we stimulate it

(a) Figure 10

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(b) (a) Simulated and measured SNDR for the converter (b) SNDR measured by standard and self-test approaches

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with a sinusoidal signal attenuated at –12 dBFS. If we use this technique to measure the SNDR with a full-range signal, aliasing and test escapes can happen. This technique can be used to completely validate the converter only in applications where we are sure that the device will never work with input signals close to the full-range. Otherwise, we need to perform additional tests to quantify the distortion of high-amplitude input signals. It is also very interesting to compare the self-test strategy presented in this paper with the BIST presented by Roy et al. in [9]. In that approach, the authors were able to measure the distortion (in terms of THD) of a 13-bit Σ∆ converter. However, it is not possible to measure the noise and large dynamic errors (sparkles) cannot be detected. In the proposal presented in this paper, we are able to measure the SNDR but we cannot measure weak distortion created by a full-range signal. Since both BIST strategies apply a binary stimulus to the input of the converter, they could be integrated together in the same circuit in order to test all the main parameters of high-resolution converters: noise and distortion.

6.

Conclusions

In this paper we present a new stereo audio ADC architecture with an embedded SNDR self-test. A highprecision binary stimulus is injected into the converter by reusing the bandgap circuit already existing in the converter. The analog overhead area for the BIST is consequently very small: we only need two additional analog pads. The digital overhead area necessary for the analysis is also very reduced by taking advantage of the hardware redundancy of a stereo converter. By reusing the two identical digital decimation filters existing in a twochannel converter, we can generate a high-precision reference signal and carry out a synchronized sine-wave fitting algorithm. The estimated total overhead area is 7.5% in the case of stereo converters. Additionally, most of the additional BIST circuitry is digital, which is very convenient for the smaller new technologies. The total test time is 30 ms for each channel. The test cost is considerably reduced because we do not need a high-precision generator equipment. Moreover, we do not need an anti-aliasing filter in the test board. Simulation results show that the BIST technique is equivalent to a standard test carried out with a sinusoidal signal at -12 dBFS. Experimental results are excellent and confirm the results expected by simulations. The comparison of the BIST technique with a sinusoidal standard test shows an SNDR error smaller than 1 dB.

7.

Acknowledgments

The authors would like to acknowledge Christian Badard and Willy Beule at STMicroelectronics for the realization of the test board layout, Ahcène Bounceur at TIMA Laboratory for his contribution to the test stimuli

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generation and Milos Klusal and Emmanuel Simeu also at TIMA Laboratory for their collaboration in the development of the decimation filter VHDL description. This work has being carried in the frame of the European MEDEA+ project NanoTest.

8.

References

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Journal of Solid-State Circuits, Vol. 34, No. 3, pp. 318-330, March 1999. [12] K. Parthasarathy, T. Kuyel, D. Price, L. Jin, D. Chen and R. Geiger, “BIST and Production Testing of ADCs Using Imprecise Stimulus”, ACM Transactions on Design Automation of Electronic Systems, Vol. 8, No. 4, pp. 522-545, Oct. 2003. [13] L. Rolíndez, S. Mir, G. Prenat and A. Bounceur, “A 0.18 µm CMOS implementation of on-chip analog test signal generation from digital test patterns”, Proceedings IEEE Design, Automation and Test in Europe Conference, Paris, France, pp. 704-705, Feb. 2004. [14] M.F. Toner and G.W. Roberts, “A BIST Scheme for an SNR Test of a Sigma-Delta ADC”, Proceedings IEEE International Test Conference, Baltimore, USA, pp. 805-814, Oct. 1993. [15] C.K. Ong, K.T. Cheng and L.C. Wang, “A new sigma-delta modulator architecture for testing using digital stimulus”, IEEE Transaction of Circuit and System I, V. 51, pp. 206-213, Jan. 2004. [16] C.K. Ong, P.W. Luo, Y.J. Chang, K.T. Cheng and W.C. Wu, “DfT Sigma-Delta Modulator Architecture

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