Master Informatique Recherche Mod`eles et M´ethodes pour les Syst`emes Intelligents R´epartis et la R´ealit´e Virtuelle (MMSIRRV) Universit´e de Bretagne Occidentale

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NANO CAD: D ESIGN AUTOMATION M ETHODS F OR E MERGING NANOSCALE T ECHNOLOGIES A Survey of Nanoscale Computing Architectures and Associated CAD Tools. by Ciprian TEODOROV

under the guidance of Loic Lagadec, Catherine Dezan, Bernard Pottier

LESTER - Architecture & Syst`eme, FRE CNRS 2734 Universit´e de Bretagne Occidentale February 25, 2008

N ANO CAD: D ESIGN AUTOMATION M ETHODS F OR E MERGING N ANOSCALE T ECHNOLOGIES A Survey of Nanoscale Computing Architectures and Associated CAD Tools. Ciprian Teodorov LESTER/AS FRE CNRS 2734 – U.B.O. [email protected] February 25, 2008 Abstract In 1959 Richard Feynman, the father of nanotechnology, suggested, in his famous lecture ”There’s plenty of room at the bottom”, the possibility to directly manipulate individual atoms in order to be able to create denser devices. Half a century later, the scientists are able to create and manipulate a wide range of nanoscale devices. A set of nanoscale technologies emerged as an alternative or complement to traditional CMOS1 circuits. They bring certain promises such as high density, reduced manufacturing costs, new functionality, but they also present a new set of challenges. In this article we look at the current state-of-the-art research in nanoscale technologies used for computing. The major existing nano computing architectures(NCA) are presented, along with the principal issues arising when creating and using such architectures. Furthermore, some of the CAD2 tools targeting application design automation on these architectures are investigated in order to extract the main characteristics such a CAD tool should have.

1 Introduction Over the last half century, computer architects have followed the trend imposed by the Moore’s law satisfying the need for ever-increasing performances. CMOS technology has scaled along with Moore’s law for many years, allowing the architects to build performant systems. Unfortunately, CMOS technology suffers from a problem that deepens everyday. As the technology progresses, CMOS devices become smaller and smaller, nowadays reaching deep sub-micron range(less than 100nm); at this order of magnitude, sooner or later, CMOS devices will cease to scale because of their physical properties. But this is not the only problem, as the devices shrink the cost for a fabrication plant increases exponentially while the ability to handle fabrication process variations decreases. The evolution of CMOS technology followed closely the business S-Curve (see Figure: 1) now being in the maturity period, thus approaching the physical, and economical limits by the year 2010 (according to the ITRS road-map[23]). In order to cope with these problems a number of scientists are trying to find some alternative technologies that will scale to even smaller sizes than CMOS. The result is the development of a set of devices known as nanoelectronic devices. They are the product of sustained research in physics, chemistry and electronics and offer the possibility to reach feature sizes on the order of a few nanometers. Some examples of these devices are quantum-dot cellular automata (QCA)[8, 3], single electron transistors (SET)[25], spintronics(SPIN)[5], resonant-tunnel diodes(RTD)[25], carbon nanotubes(CNT)[42], and semiconductor nanowires[33]. Even though each of these devices has unique features, there are a set of characteristics that span across all of them, defining the class of nanoelectronics. These characteristics include, for example, the stochastic self-assembly approach 1 Complementary

Metal Oxide Semi-conductor Design

2 Computer-Aided

1

Limit: technical, economic,...

Performance

Maturity, slow growth

Exponential growth

Time

Figure 1: The business S-Curve to bottom-up fabrication process, which implies extremely high rate of defects and inherent regularity in assembly. The self-assembly approach is used because, even though some researchers managed to manipulate individual devices[27], their small size render the classical top-down approach to fabrication unusable for large scale integration. Due to the stochastic nature of the assembly process the defect rates are expected to be as high as 10−1 (the defect rate in today’s CMOS technology is 10−9). Regularity in assembly is a result of the specific properties of these devices and of the fabrication process. Today the field of nanoeletronics, and nanotechnologies in general, can be positioned near the origin of the business S-Curve, Figure 1. The innovations in this field have a great impact in all scientific areas. All over the world the research in these areas is sustained with a considerable financial support, 10,5 billion dollars in 2006, with an annual increase estimated at 40%[19]. In this context it is important to say that in Europe the contribution of the private sector, in research and development, is still reduced in comparison with the total investment. So, there is a gap between the European Union and the United States and Japan, where the private sector sustain more than a half of the total investments in these fields[19]. The possibility to create, synthesize and manipulate molecules and objects of nano scale size that behave like electronic devices gives new opportunities for the development of information technologies. But the processes and tools used to realize these devices are not mature enough, and also the devices obtained are not fully understood. This implies that in order for these devices to reach mass market, and eventually replace current CMOS technologies, the researchers should try to improve the quality of the produced nanodevices, but not only. They also must find ways to assemble them together into fabrics and use these fabrics for building usable circuits like: microprocessors, memories, FPGAs3 , PLAs4 , etc. A number of nanofabrics has already been proposed each one presenting its own advantages and challenges. Still, in order for these fabrics to become usable, the community needs a right set of abstractions (models) along with a set of tools (CAD tools) for application design automation on these emerging fabrics. The design of these CAD tools poses a new set of challenges for engineers not encountered with conventional CMOS technology. These challenges come basically from the intrinsic characteristics of the nanodevices used (like high defect rates), and from the way they are assembled together. Some of the proposed fabric architectures resembles today FPGA, other PLAs, and there are even novel approaches like QCA[8, 3]. This paper is a survey of the work that has been done in designing computing architectures using nanoelectronics. The effort of designing nano computing architectures includes the actual design of the fabric as well as the models and software tools used by the engineers in order to design and use the proposed fabric. The layout of the paper will be as follows. In Section 2 some of the design issues regarding these fabrics will be discussed. Section 3 will present some of the proposed organizations of the computational fabric. Section 4 will present each step in a conventional CAD flow focusing on ways to tackle the issues arising with these novel architectures. And, finally, Section 5 will conclude this paper.

2 Design Challenges of Nano-Scale Computational Fabrics To be able to follow the trend imposed by Moore’s law we need to obtain higher and higher device densities at the lowest possible cost. Thus, providing abundant resources used to craft basic computational fabrics. 3 Field

Programmable Gate Arrays Logic Arrays

4 Programmable

2

Nanoelectronic devices provide today an alternative way of increasing device density by using nanoscale electronic components. But even though many nanoelectronics devices have been demonstrated in research laboratories[8, 3, 25, 5, 25, 42, 33], a crucial step is to integrate these devices into an architecture that takes advantage of their strengths and overcomes their limitations. Firstly, the nanoelectronic devices cannot be assembled into architectures that comprise only nano scale elements. Thus, first generation of fabrics using these tiny devices will consist of hybrid architectures with the CMOS technology playing an important role in the design and development of these circuits. The purpose of this section is to introduce some of the challenges imposed by the use of nanoelectronic devices on the computing architecture designers.

2.1 Assembly process With nanoelectronics one of the major problems is their small feature size that makes almost impossible the use of traditional lithography. Current approaches to overcome this problem include three major ideas: • Self-assembly: let the circuits assemble themselves; • Manipulation at a higher level: guide a group of wires so they line up in the same direction; • Stochastic assembly: place enough elements until they statistically form the desired device. This bottom-up approach to assembly has a number of consequences that should be taken in account by fabric designers. The regularity of assembly is one of the constraints imposed by this assembly approach, this means that the computational fabrics will no longer be made of custom circuits but, more likely, of generic circuits configured with respect to the application needs. With the exception of QCA[3] and Nanocell[28] all the hybrid architectures[26, 21, 29, 37, 2] proposed in the literature are using nanowire crossbars rather than arbitrary geometries as current designers are using in top-down VLSI. This regularity in the nanoscale structures is driving researchers to build architectures that resembles today’s PLA and FPGA fabrics[26, 21, 29, 37]. The Nanocell approach[28], even though it does not use nanowire crossbars, it has a similar concept, as it uses identical cells for computations, the difference being made by the training applied to each cell and the defects arising during fabrication5. This inherent regularity in assembly can also play an important role in coping with the high rate of defects, that is yet another consequence of the bottom-up assembly techniques.

2.2 Defective Nanoscale Fabrics The sources of error expected to be present on the nanoscale fabric are, mainly, due to the bottom-up fabrication process, proposed as a cheaper fabrication technique. They can be classified into three categories: • Permanent Defects are definitive changes in the fabric structure. The manufacturing process is the principal source for such defects. The small nanowires and the bottom up assembly process are expected to contribute to high rates of defects in nanoscale fabrics. They also may appear during the circuit operations. Some examples of this type of defects are: broken nanowires, stuck open/short FETs. • Process Variations[34] are caused by speed deviations due to device parameter variations. They can occur for certain input parameters as a result of large unexpected delay for that combinations. They will occur due to doping variations of NW used for channels or by length variations caused by the metallization process used to separate FETs one from another. • Transient Faults are the variations of a circuit parameters during its lifetime due to internal or external noise(alpha particles, neutron, proton, etc). The circuits presenting this kind of faults are not permanently damaged, the faulty behavior disappearing once the noise source disappears. 5 Each

cell will be unique due to the unique defects arising during fabrication

3

A number of fault tolerance techniques where proposed in literature to make the circuits more or less resistant to these possible faults. Some of these are: • Configuration around defects[4] approach used in the Teramac project. It consist in building a defect map of a circuit using special tester circuits. Once the defect map built, the application is placed and routed around the defects. This technique implies that the underlying fabric is reconfigurable, which is not a problem with the nanoscale architectures since the assembly process produces regular structures. This approach is used by most of the hybrid nano/CMOS architectures [26, 21, 29, 37]. • Circuit level built-in redundancy[16] implies replication of NWs and of FET transistors in order to mask faulty signals, thus rendering a self healing fabric. This way the need for defect map extraction and special nano/CMOS interface for reconfiguration is eliminated. For further enhancing the fabric fault tolerance, along with this technique, at different granularity levels, other techniques can be used: – Interleaving of redundant NWs[16] thus limiting the area of the circuit where built-in redundancy does not work (the so called ”hard to mask regions”) . – Insertion of weak pull-up/down micro/nano wires[16] for broken NWs in order to be able to correct a faulty 1 before an OR gate. – Error correcting circuits[34] is the use of error correcting codes not at application level like in telecommunication applications but at circuit level. This implies adding redundant signals to the original input signals in order to achieve the desired Hamming distance. Furthermore error correcting FET are added in order to maintain a valid circuit. – Triple modular redundancy[40] at tile level in order to further improve the fault tolerance. Each tile may be replicated 2 times and voting can be done at each stage or on the final output. The implementation of the voter circuit in CMOS is required in order to have trustworthy voters. As we can see, a large number of fault tolerance techniques has been proposed by the researchers on different projects. The NASIC team[16, 40, 15, 34] is building a self healing fabric which is a radically different approach to others[26, 21, 29, 37] which are using, mainly, the defect map extraction and routing around defects technique to cope with the inherent defects at nanoscale level.

2.3 Nano/CMOS interface As discussed earlier in this section, the first architectures using nano scale devices will be hybrid architectures having nano and CMOS parts. So, another important aspect, in designing computational fabrics using nanoelectronics, is the role played by CMOS technology in the resulting circuit. In table 1, one can see that the CMOS can be used, depending on the architecture, for logic, for interconnect, clocking, power, ground, configuration wires, I/O. In order to be able to use CMOS devices and nanoelectronic devices on the same circuit an interface between the two have to be made, for addressing the nanoscale wires from the microscale ones. Directly driving the nanowires with microscale wires is not feasible because the feature size of the microscale wires will negate the potential benefits of the minuscule devices. To solve this problem different approaches where proposed. In nanoPLA[21], the approach is to use a stochastic decoder proposed by DeHon in [20]. In CMOL[17] and FPNI[37] a 3D structure of the fabric is used. The nano layer is on top of the CMOS layer and connection pins provide the communication between the two.

3 Nanoelectronics Computational Architectures In this section, we will summarize several of the current proposals for building computational fabrics using nanoelectronic devices. In table 1, we present roughly these architectures showing some of their characteristics. Many of these proposals draw heavily from those ideas introduced by PLA and FPGA, but they are not limited to these, there are novel approaches like Nanocell[28, 22]. Crossbar circuit architecture is by far the most popular, but QCA[36, 35, 24] and Nanocell[28, 22] investigate other possibilities like quantum interaction between nano dots and, respectively, random assembly followed by cell training. 4

The logic type proposed for each architecture is one point where the diversity can be pointed out. The fabrication constraints impose rather simple logic types for some architectures. In these conditions the 2-level logic with complementary signals is employed. For example, DeHon’s nanoPLA approach[21] uses either an NOR plane followed by an OR plane or two consecutive NOR planes, CMOL[31] uses NOR-NOR logic, NASIC[2] uses the more traditional AND-OR logic (used by today’s PLAs) or equivalent 2-level logic family such as NAND-NAND logic. In [13] the NASIC team investigates also the use of a combination of 2-level types namely AND-OR and NOR. The other architectures, nanoFabrics[26], FPNI[37], QCA[36, 24], nanoCell[22] , presented in table 1, are not constrained to one particular logic family because their basic cells are supposelly able to implement arbitrary logic functions. Table 1: Nano-Architecures comparison Proposed by

References

Nanofabrics

NanoPLA

Carnegie Mellon University

University of Pennsylvania

[26]

[21, 20]

NASIC University of Massachusetts, Amherst [2, 7, 14, 16, 40, 15, 34, 13]

CMOL

FPNI

NanoCell

QCA

Stony Brook University

HewlettPackard

University of Notre Dame

Rice University

[17, 29, 31, 30]

[37]

[28, 22]

3D Crossbar

FPGA

FPGA, PLA, ASIC

logic devices, memory

nanowires

-

gold and platinum particles

[8, 3, 11, 36, 35, 24] Custom 2D Random 2D 3D Crossbar Structure Structure Heterogeneous Heterogeneous Regular

2D Crossbar

2D Crossbar

2D Crossbar

Architecture Regularity

Regular

Regular

Computing Architecture

FPGA

PLA

metal nanowires

semiconductor nanowires

Heterogeneous Regular memory, FPGA, CrossASIC Net Neu(µProcessor) romorphic networks silicon nanowires nanowires

molecular switch

programmable diodes, FET

FET

latching switches

latching switches

molecular QCA

molecular switches

logic and routing clocking, power, ground, configuration wires, I/O, basic control

NOR-NOR arrays

logic, interconnect

OR-logic, signal routing

interconnect, routing

logic, routing, interconnect

logic devices, memory

addressing and reading results from nanowires

control

inversion, gain, demultiplexers

arbitrary logic

clocking

gain, nanocell programming

Permanent

Permanent

Permanent, Transient

Permanent

Permanent

Permanent

Permanent

Circuit Architecture

Nano technology used

passive devices active devices

Nano Role

CMOS Role

Fault Tolerance Scheme

Regarding table 1, one interesting aspect, from a political point of view, is that all these fabrics are proposed by research teams from the United States. Another, this time technical, aspect is that most of these architectures have a 2D structure which imply that the nano and CMOS layers are on the same level, this having an impact on the way the two are interfaced. Another observation, that is worth mentioning, is the lack of passive devices for the QCA[8, 3] fabric, this is due to QCA’s unique characteristics, namely everything, from wires to logic gates, is based on quantum interactions between the quantum dots, which are the active devices. More details on these architectures will be presented in the following subsections, where each architecture, in table 1, is presented in depth.

3.1 Nanofabrics One of the first attempts to build useful computing architectures, out of nanoscale devices, has been made by Goldstein and Budiu in [26]. In their paper, they proposed a FPGA like architecture named Nanofabric, shown in Fig. 2a. The Nanofabric is composed of a large number of reconfigurable blocks (nanoBlocks) which can act as computational units or as switches to route signals. The nanoBlocks are composed of three parts. (1) A molecular logic array (MLA), consisting of a crossbar array with a configurable molecular switch at the crosspoints. (2) The latches, negative differential resistors (NDRs) added to the output of each nanowire. These NDRs provide also signal inversion and gain functions not available because the nanoBlock rely on diodes for operation. (3) The I/O area, used to connect the nanoBlock to its neighbors through the switch block. Compared to the FPGA LUTs6 , which can implement any function of 6 Look-Up

Table

5

a)

b)

Figure 2: a) The layout of the nanoFabric with the partial blowup of a single cluster and some of the adjacent long lines [26]; b) NanoPLA nanowire PLA structure [21] n inputs, the nanoBlocks are limited to simple gates such as AND, OR, XOR. The nanoBlocks are connected in a 2-D mesh, alternating the switch blocks with the computational blocks. The signal routing is done by the switch blocks between neighboring nanoBlocks. The nanoBlocks are organized in clusters, with long lines used to provide inter-cluster communication. Only the nanoBlocks on the perimeter of the cluster are connected to these long lines. All of the logic operations, as well as routing, of Nanofabrics are performed using nanoelectronic devices. A CMOS interface is supposed to provide basic functionalities as clocking, power, ground, configuration wires, basic control, I/O. According to the authors, the density of the fabric can be as high as 1M blocks/cm2 [26]. In order to tackle the defect tolerance problem imposed by the use of nanoscale devices, the authors proposed an approach similar to the one used in Teramac project[4], exploiting the reconfigurability and rich interconnect of the Nanofabric. In their paper [26], the authors, just briefly, discuss the configuration of the Nanofabric. The proposed architecture can be used as factory-programmable devices configured by the manufacturer to emulate a processor or other computing device or, more generally, as reconfigurable computing devices.

3.2 nanoPLA In 2004, Andr´e DeHon in[21] proposed a PLA-like approach to building a computational fabric out of nanoscale devices. The basic logic structure of this fabric, named nanoPLA, is based on a crossed set of parallel semiconductor nanowires with programmable diodes at crosspoints, see Fig. 2b. For overcoming the limitations of diode logic the authors propose to insert rectifying field-effect stages between diode stages. These restoration stages can provide inversion, such that the pair of planes provides a programmable NOR gate. In order to address the nanowires forming the NOR and OR arrays DeHon proposes the use of a special decoder(see section 2 for details) thus the programmable crosspoints can be used in a custom way, to avoid defective wires and crosspoints or to implement a deterministic function despite the fabrication defects and stochastic assembly of the fabric. This fabric organization makes it possible to adapt conventional PLA and FPGA mapping tool (PLAMAP[9], VPR[12]) to map logic to the fabric. In [20] DeHon showed that mapping of Toronto 20 benchmark suite to 10nm pitch nanowires result in two orders of magnitude higher density than defect-free 22nm lithographic FPGAs.

3.3 NASIC Moritz et al. proposed a hierarchical nanofabric architecture that can be tuned towards an application domain. The basic building blocks of this proposal are the nanotiles, built up as a grid of SiNW having

6

a)

b)

Figure 3: a) Pipelined 2-bit Full Adder in NASIC [14]; b) On the left, CMOL interconnect between CMOS and nano[29]. On the right, CMOS cell in CMOL FPGA [29] the junctions acting as FET. The Fig. 3a is presenting a pipelined 2-bit full adder implemented by using 2 nanotiles. NASIC architecture has raised many interesting issues in designing nano/CMOS integrated circuits. Some of these are: (1) Latching on the wire[7, 15] in order to build pipelined circuits without the use of explicit latching (which implies the use of registers); (2) In one of the latest papers [13] Moritz et al. showed the possibility to combine AND-OR and NOR-NOR logic styles in order to obtain denser logic (up to 48% better than the original WISP-0[14] processor using AND-OR logic); (3) While in the first stages of the development[2] the fabric was conceived as being reconfigurable, in the later papers[16] the authors renounced at the reconfigurability. This new version of the fabric did not need a nano/CMOS interface for reconfiguration, this enabling denser circuits. But, on the other hand, without a reconfigurable fabric, another approach was needed in order to render the fabric fault tolerant. (4)To solve this problem, in [16, 40, 15, 34], novel fault tolerance techniques were proposed (ex.circuit level redundancy, Error correcting circuits, etc). These techniques are discussed in section 2. An advantage of using this stack of fault tolerant techniques at once is that the obtained circuit can correctly behave also in the presence of transient faults.

3.4 CMOL The problem of addressing the nanowires with microscale wires is one of the thoughest. One approach to solve this problem is the stochastic decoder proposed by DeHon for nanoPLA. This section will present a radically new approach for this problem, proposed by Strukov and Likharev in their work on CMOL [31, 30]. Instead of trying to integrate the microscale and nanoscale devices on the same level, in CMOL, a three dimensional approach is taken. So the nanoelectronic part of the circuit is on a layer on the top of the microscale (implemented using CMOS). The way the interconnection is done between nanoscale and microscale in CMOL is a key concept which enables each nanowire to be connected with exactly one pin to microwires. On the left of Fig. 3b one can see the way the interconnect is done. There are two types of vertical pins (red and blue in Fig. 3b) that connect the layers. The purpose of using two pins is to have one connecting to the wires in the crossbar in one direction, and the other connecting the wires on the perpendicular direction. The nanodevice layer is rotated by an angle α = arcsin(Fnano/βFCMOS ) relative to the CMOS pin array, where Fnano (FCMOS ) is the nanowire (microwire) half-pitch and β is a dimensionless factor larger than 1 that depends on the CMOS cell complexity. The CMOL FPGA [29] is based on concepts from traditional cell based FPGAs. For example, cells like the CMOS cell, in Figure 3b at right, are tiled across the chip forming a highly regular structure. These cells include two pins to connect to the nano-layer and four transistors, two of them acting as pass transistors to control the access at the pins. The other two transistors form a CMOS inverter. This inverter has one of the pins as input and the other as output, thus the signals from nano-layer enter the CMOS layer where they are inverted before being re-injected in the nano layer. In CMOL FPGA, the nano layer is used as a large OR array using diodes for operation. A NOR gate can be implemented by having an OR gate in the nano crossbar and having the input of this gate inverted

7

a)

b)

Figure 4: a) Nanocell structure. The black rectangles on the edges are the I/O leads[22]; b) Left, QCA cell polarizations; Right, QCA majority gate into the CMOS layer. In conclusion, in CMOL FPGAs the nano layer is used for OR logic and signal routing, while the CMOS layer is used for signal inversion, gain and demultiplexing. Having a highly regular structure enables CMOL to use routing around defects techniques in order to cope with the high rates of defects of the nano layer. The CMOL architecture is not limited to FPGA like structures, in [17] the authors presented other possible uses of CMOL fabrics like memories or crossnet neuromorphic networks.

3.5 FPNI At the beginning of 2007, Snider and Williams, at HP labs, introduced a generalization of CMOL circuits, namely Field-Programmable Nanowire Interconnect (FPNI) [37]. The FPNI architecture trades of some of the advantages of CMOL, such as speed, density, defect tolerance, in exchange for easier fabrication, lower power dissipation and easier routing. In FPNI, all the logic computations are done only in CMOS and use the nano-layer just for signal routing. The logic implemented in CMOS cells is not limited to NOR gates, thus rendering FPNI a heterogeneous fabric. This heterogeneity allows to fine tune the cells for the desired function. FPNI approach is more like traditional cell-based FPGA where cells implement arbitrary logic. The difference being the signal routing which is done entirely using the nano layer. Thus achieving better densities than traditional CMOS only FPGAs, which dedicate a large part of their area just for interconnect. However, FPNI does not achieve the logic density of CMOL circuits. This being the result of implementing all logic in CMOS. Another draw back of this approach is that now the cells are heterogeneous and the designer of the circuit must choose which functionality each cell must have.

3.6 Nanocell One of the first proposed computational architectures that make use of nanoelectronical devices is Tour’s Nanocell[22]. This fabric is conceived to harness the random nature of nano scale devices by randomly depositing very small conductive particles of gold or platinum on a substrate and then adding molecules having NDR properties to each of these particles. Thus obtaining a random network of switchable nanodevices, namely Nanocell shown in Fig. 4a. This network is then trained to perform the desired function using a genetic algorithm. The building block for computational fabrics, using Nanocell approach, are presented in [28]. The main advantage of this approach is that it has inherent fault tolerance by harnessing the random nature of nanotechnology instead of trying to create some order. On the other hand this proposal has some drawbacks too. One is the huge amount of computational resources needed to train a Nanocell using the proposed genetic algorithm.

8

3.7 Quantum-dot cellular automata Quantum-dot cellular automata[8, 3], introduced in 1993 by Lent et al., and fabricated in 1997 represents completely novel approach in implementing circuits. Based on quantum interactions between electrons, it provides an alternative way to current CMOS technology and also to the Nano/CMOS hybrid architectures presented in the last subsections. A QCA cell can be seen as a set of four charge containers or dots positioned at the corners of a square. Each cell contain two mobile electrons that can quantum mechanically tunnel between the dots but, by construction, cannot tunnel between cells. In Fig. 4b, we show an abstract view of a QCA cell with the two possible states binary 1 at left and binary 0 at right. The state of each QCA cell is influenced by the state of neighboring cell. So basically, if we place the cell at left in Fig. 4b in the neighborhood of the cell at right in the figure, the last one will change its state to a binary 1 value. This way a set of computational interesting devices can be obtained (ex. majority gate[35] in Fig. 4b on right). In [36], the authors presented a FPGA-like architecture using these revolutionary devices. Some of the particularities of this approach compared to traditional FPGA are: (1) instead of implicit latching of signals QCA FPGA use QCA wires’ self-latching capabilities; (2) the clock for QCA FPGA has four phases instead of just two in traditional circuits; (3) the use of a QCA wire loop for storing state. In 2006, a PLA architecture using QCAs was proposed[24]. This PLA fabric is reconfigurable and defect tolerant. The basic building blocks used in this approach are PLA cells made up by one AND gate, one OR gate and one select bit. The AND and OR gates are obtained by constraining a majority gate to perform the desired function. The select bit is used to indicate if the PLA cell acts as a wire or as a logic gate. The PLA logic is build up by using 2 logic planes one AND plane followed by an OR plane. These logic planes are made up of PLA cells which act as AND gates or OR gates according to the position of the two gates inside the PLA cell. The issues of configurability and fault tolerance were also addressed in the same paper. Also the nature of the clocking circuitry and structure were discussed. But, at the end, one can observe that even though the research in the area of QCA started 15 years ago the field is still young, and the published works are just pointing the needs for further research in order to render these technologies a veritable candidate to replace ”current flow” based technologies.

4 CAD Tools for Nano-architectures The transition to hybrid nano/CMOS architecture, at first, and to nano architectures afterwards, will imply modifications and additions to current computer-aided design tools, in order to accommodate the unique properties of these novel technologies. These tools assist the circuit designer in different ways. Some of them help the architecture designers to investigate different approaches for building computational fabrics, others will help to automatically implement a circuit provided an object oriented specification (MADEO[1]) on a target fabric, and yet others will offer just a simple GUI to the user which have to implement the circuit manually (QCADesigner[41]). Over the years the importance of CAD tools increased proportionally, we can say, with the increase in size and complexity of the computing architecture at hand. So the introduction of nanotechnologies, the huge number of devices per cm2 and the presence of defects, will increase also the importance of the CAD tools, rendering the architecture and the circuit design impossible without automatized tools. As we could see, in section 3, many of the hybrid circuits presented [26, 21, 17, 37] resemble closely to FPGA, or PLA designs. The direct effect of this is that many of the tools already available, for these type of architectures, can be easily migrated for the novel fabrics. In this section we will present, firstly, each step in a traditional CAD flow, shown in Figure 5, in order to point some possible modifications to this flow in the case of re-targeting it to nano devices based circuits. In the last part of this section we present one generic CAD tool that, based on four models, aims at targeting a wide range of nano scale fabrics. The first step in a CAD flow is to convert the user circuit description into a format that can be executed on the target technology. This, namely logic synthesis in figure 5, is done in two steps, logic synthesis, and technology mapping. Logic synthesis is in charge of translating the high level description of the circuit into a netlist of logic gates and interconnections. For example a+b is implemented with a specific adder circuit. Theoretically logic synthesis can produce technology independent circuits, but in practice having

9

Logic Synthesis

HDL

Partitioning

Placement

Routing

Configuration File

Physical Tools

Figure 5: CAD Flow knowledge about the target architecture can produce better implementations. For example, if we know that the a+b circuit is targeted to NASIC fabric (error correcting circuit[34]) we will be able to add the redundant bits in order to improve the yield of the resulting circuit. The technology mapping is responsible for implementing the circuit netlist using the basic components that are available on the target architecture.At this stage many optimizations for power, area, and performance can be made by the intelligent use of FPGA’s resources. Partitioning has a similar role as technology mapping, but at a higher hierarchical level. If technology mapping is about mapping the netlist to available components on the fabric, partitioning will try to split the technologically mapped netlist into small clusters such that the signal crossing cluster boundaries are minimized, for example. The idea behind this is to obtain small enough clusters that can fit into a module of a target fabric. Placement, the next step in the CAD flow, decides exactly what components on the chip will be used to implement each logic function. Basically the goal at this level is to minimize the communication cost by keeping communicating cells close to each other. Other optimization goals at this level are: balancing the wire density across the fabric (routability-driven placement), maximization of the circuit speed (timingdriven placement). After placement, routing selects the interconnect resources to carry the signals across the chip from one module to another. The goal of routing is to reduce the circuit delay without overusing routing resources. Most of the routing algorithms are trying to find systematically paths from the source to target. Special congestion avoidance techniques are used to prevent overusing of routing channels(routing 2 signal over the same channel). Once this step finished, with the generated configuration file, the circuit can be deployed.

4.1 CAD Challenges and used tools For nano fabric, logic synthesis and technology mapping will use largely the algorithms already used in FPGAs and PLAs, because of the regular structure employed by these architectures. The main difference will be the use of crossbar arrays instead of LUTs. Homogeneous nature of nanoscale devices may render technology mapping easier. The simple logic elements presented in the proposed architecture eliminate the need to target embedded multipliers or carry chains, etc. The possible defects present on target architecture will have a reduced impact at this stages. However different fault tolerance schemes may be used in order to prepare the design for accommodating defects, this helping at realizing self-healing designs. An example of fault tolerance scheme that can be used at this level is the NASIC error correcting policy[34]. As can be seen in table 2, currently, most architectures are using Sis[18] for these steps. Table 2: CAD tools used for different fabrics

Logic Tools

Nanofabrics[26] NanoPLA[21] Sis[18] Sis

Partitioning T-VPACK[12]

Physical Tools

PLAMAP[10]

Placement

Simulated Annealing[18]

VPR[12]

Routing

Simulated Annealing[18]

NPR - custom tool (based on Pathfinder)

NASIC[2] nanoMadeo[10]

CMOL[17] Sis

nanoMadeo[10]

T-VPACK[12]

nanoMadeo[10]

Simulated Annealing (VPR-like) modified congestion function

Simulated Annealing (VPRlike)

custom tool[32]

nanoMadeo[10]

Custom tool (based on RSA heuristic)[38]

maze router (Pathfinderlike) with several iterations

cycle breaker[6]

10

FPNI[37] Singh’s greedy algorithm (specific cost)[39]

QCA[11] custom tools custom tool[32]

For partitioning the methods used in the classical FPGA CAD flow can be reused. Eventually, some specific parameters can be introduced. In table 2, the reader can see that at this step the simulated annealing heuristic, the same heuristic implemented by the VPR tool[12], is widely used. The placement on the presented nanofabrics will be similar to FPGA placement, in table 2, we can see that Nanofabrics, NanoPla, CMOL, FPNI architecture already use tools like VPR7 [12] or an adaptation of the simulated annealing algorithm (used by VPR also). However, while minimizing the communication cost the placer must be aware of the defective parts of the circuit so it can place the modules on usable parts. Other constraints can be present according to the target architecture. For example, the small length of the nanowires, can render long distance communications very costly. Similarities exist between FPGA routing and the routing methods needed for the hybrid architectures discussed in this paper (see Section 3). In table 2 on the “Routing” row we are showing the routing methods proposed for these architectures. The routers for these architectures must be defect-aware in order to route around defective fabric resources. This is the reason why, in table 2, for routing, we see that custom tools are used for all the fabrics. For deployment a big difference between a typical FPGA and nanoscale FPGA-like device appears. The difference is that while the FPGA is tested by the manufacturer and the faulty devices are thrown away, the nanoscale fabric has more defects, randomly placed. So, while a FPGA circuit, once synthesized, can be deployed to any number of similar FPGA devices, for the nanoscale fabric this will not be possible since each hardware device will present a unique defect map, around which the circuit has to be placed, routed, etc. So basically the synthesis process, or at least parts of it should be reiterated for each physical nanoscale fabric. Additional steps may be needed in a CAD flow targeted for one or more of the architectures presented in this paper. For example, in order to be able to test and configure around defects[26, 21, 17, 37] a defect map needs to be built. This map, probably, can be constructed the first time the fabric is used, or it can be dynamically computed each time a part of the reconfigurable fabric is reconfigured. If the second approach is taken, this step will be inserted probably before the placement step. On the other hand if the fabric uses software inserted redundancies, like the NASIC approach[34], some steps may be added to the front end of the CAD flow. For example after the synthesis step, the netlist will pass through a series of transformations in order to insert the error correcting signals or the voting circuits. After this step the synthesis process will continue like for any other circuit.

4.2 Towards a generic CAD tool for nanofabrics The generality and evolutivity are two metrics that should not be ignored in the context of the CAD tools targeting the emerging field of nanoelectronics fabrics. By generality we mean the capability of a CAD tool to target more than one hardware architecture. The evolutivity, on the other hand, is the capacity to integrate new architectures, methods, paradigms that, certainly, will apear during the nanoelectronics evolution cycle. A generic CAD tool will permit to circuit and architecture designers to easily do architectural prospections, thus giving them a realistic measure of different aspects related to the designed circuit or to the underlying hardware model. To the best of our knowledge, the only work presenting a generic CAD tool targeting design automation of applications on a wide range of nanofabrics appeared in 2007 [10]. The framework, named nanoMadeo, propose a complete CAD flow based around the notion of model. In order to capture all the key aspects of a fabric 4 principal models are proposed: computational model, architectural model, technological model and fault model. The interaction between these models and the logic and physical tools produce an abstract layout of the design. In their paper[10], the authors used NASIC[2] as a case study. But, even if the result obtained are very promising, this project is not completed, and lots of research work needs to be done especially for the physical design tools. Overall, many parts of the current FPGA CAD flow can be used for programming some of the hybrid nano/CMOS fabrics, but the problems to solve will be more difficult. Technology mapping, partitioning, placement, and routing will not be very different once the defect maps are built, the only problem that will 7 VPR

is a standard tool used for circuit placement and routing onto standard FPGA architectures

11

arise is the problem size. Since the density of the circuits will increase, the computational time, needed to synthesize a design on a nanoscale fabric, will increase too. On the other hand, there are projects like nanoMadeo[10] that try to bridge the gap between the nanofabrics and also between the circuit designer and the fabric architect and the actual chip. Such projects will, hopefully, find the much needed answers that will make the nanoelectronics the devices of the future.

5 Conclusions Since it’s invention, in 1947, the transistor became smaller and smaller. Unfortunately, the scaling down process will stop. This is due to increasing power, capital costs, and reaching the theoretical size limitations. Nanoelectronics is the technology that promises to continue the miniaturization of integrated circuits(IC). However, it is not determined if the nanoelectronic devices will totally replace the conventional ICs. It has been shown that components such as wires, diodes, transistors can be fabricated and integrated into fabrics. It is also known that these devices will be prone to defects so fault tolerant techniques has to be integrated into any architecture. Finally, the preliminary research indicates that while existing parts of the CAD tools can be reused in the case of nano scale architectures, they will have to be able to integrate the modifications and additions that have to be made to accommodate this novel technology. The greatest progress has been made in the research of the components that will make up nanoelectronics. The chemists have been able to fabricate a number of molecules that behave like nowadays diodes, transistors. Some large scale fabrication methods have been presented, but they impose a number of constraints on the devices that can be realized. But, a lot of research work is, still, needed in order to improve the quality of these devices. One big question for the future of nanoelectronics is whether these devices can be assembled together into useful architectures. Some small scale experiments have been made, but the real benefits of these devices is the enormous integration level they may achieve. Today, the most promising architectures are array based. This is because the array have a simple regular structure that is easier to obtain with bottom-up fabrication techniques. Another advantage of the array structure is that it can be easily configured even in the presence of defects. There are other more random architectures that will require simpler fabrication techniques, but they are not expected to scale very well. Anyhow, today it is difficult to evaluate the proposed architectures as the underlying components are not fully understood. One thing it is clear, though, the fabrics using these devices will have to rely, for at least a few generations, on the conventional lithography for things such as I/O, clocking, configuration, etc. This generate another problem that still needs to be investigates, the interface between the nano scale level and the lithographic level. Some solution have been proposed using special decoders or 3D architectures, but, probably, more efficient solutions can be found. The biggest problem of nanoelectronics seems to be the fault tolerance. As the manufacturing techniques are not able to build defect free chips, the fault tolerance will be the key to usable nano fabrics. The most used technique against manufacturing defects is the detection and configuration around defects. For nanoelectronics this is the most obvious choice since they will be configurable devices. But the problem of detecting the defects is not trivial given the high density of integration of these devices. Another solution, that can handle also transient faults, seems to be the self healing fabrics. This is achieved by adding redundant resources such as nanowires, transistors, etc. Unfortunately, this methods have to be used wisely in order not to negate the benefits of the nano scale devices by adding to much redundancy. The solution to this problem may be the use of both techniques on the same fabric. So, maybe a reconfigurable fabric built up of small self healing blocks will outperform the fabrics presented in this paper. One aspect of the nanoelectronic-based fabrics that resembles existing technology is their CAD flow. Most of the software tools for exploiting these fabrics will be much like that of current FPGAs. The flow will still contain logic synthesis, partitioning, placement and routing steps to produce configuration files, with some additional steps. The addition will consist in some routines used to detect the defects before placement, or to add the necessary logic level redundancy in order to ensure the correct behavior of the circuit. One big issue is the deployment of a circuit, since each nanofabric is unique. With current reliable fabrication process, the same design can be used to produce millions of chips. If the nanofabrics are to be the future of electronics, a deployment method has to be developed to reduce the costs of testing and deployment. Some additional software tools may be needed for the hardware architects, tools that can 12

analyze, predict and optimize statistical designs (since statistical design techniques are used at hardware level). These tools should be able to integrate different defect models, in order to help the designers create better fabrics. One idea might be to build some generic CAD tools that are able to target design automation of applications on a large number of hardware architectures in order to help the designer explore the available design possibilities. Once build, this tools will have to be able to adapt easily to any new architecture that may appear, thus giving the architecture designer an idea of how the new fabric performs under different cost models. Many countries invest a substantial amount of money and research in the field of nanoelectronics. Many devices have been designed and fabricated, but there are still big problems to overcome in order for these technologies to replace CMOS. With a decade before the projected end of scaling for lithography-based circuits [23], the answers to these questions are more than desired.

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