intJ
APPLICATION BRIEF
AB-18
October 1988
TTL Macro Library Listing' for EPLD Designs
PROGRAMMABLE LOGIC APPLICATIONS INTEL CORPORATION
Order Number: 292037-003 .
4-33
inter
AB-18
TTL Macros
MSI FUNCTIONS
The following is a list of TTL macros that are in TTL.LIB version 3.6. This libraty is available through the Intel EPLD customer hot line.
Decoders/Demultiplexers 7442 7444 7447X
These macros are called from an Advanced Design File (ADF). Schematic capture packages such as Schema 11PLD create ADFs with the correct macro invocation for each TTL device listed here.
7449 Macros listed here are grouped by general function. 74138 74139 74145 74154 74155 74156
SSIGATES 7400 7402 7404 7408 7410 7411 7420 7421 7427 7430 7432 7486
2 Input 2 Input 1 Input 2 Input 3 Input 3 Input 4 Input 4 Input 3 Input 8 Input 2 Input 2 Input
NAND NOR INVERTER AND NAND AND NAND AND NOR NAND OR XOR
(10) BCD to Decimal (10) Excess-3-Gray to Decimal (7) BCD to 7-Segment-Active Low Output (7) BCD to 7-Segment-Active High Output (8) l-of-8 Decoder (4) Single l-of-4 Decoder (10) BCD to Decimal (16) l-of-16 Decoder (8) Dual l-of-4 (8) Dual l-of-4
Multiplexers
4-34
74151 74153. 74157 74158 74253 74257X
(2) (2) (4) (4) (2) (4)
74258X
(4)
74298XA
(4)
74298XB
(4)
74352
(2)
8-to-l Dual 4-to-l-Active High Output Quad 2-to-l-Active High Output Quad 2-to-I-Active Low Output DuaI4-to-l-Three-State Output Quad 2-to-I-Active High, ThreeState Output Quad 2-to-l-Active Low, ThreeState Output Quad 2-io-l-Active High with Storage Quad 2-to-l-Active High with Storage Dual 4-to-l-Active Low Output
inter
AB-18
Counters 7490XD 7490XQ 74160 74161 74162 74163 74168 74169 74176XD 74176XQ 74177X 74190XA 74190XB 74191XA 74290XD 74290XQ 74390X 74393XA 74393XB S A 9
(4) (4) ·(5) (5) (5) (5) (5) (5) (4) (4) (4) (6) (6) (7) (4) (4) (4) (4) (4)
Type BCD Decade Bi-Quinary BCD Decade 4-Bit Binary BCD Decade 4-Bit Binary BCD Decade 4-Bit Binary BCD Decade Bi-Quinary 4-Bit Binary BCD Decade BCD Decade 4-Bit Binary BCD Decade Bi-Quinary' Bi-QuinatYfBCD 4-Bit Binary 4-Bit Binary
= Synchronous = Asynchronous = Synchronous Set-to-9
U/D RCO MM
= = =
Clear
Load 9 9
S S
S S S S S S S S S S S S
A A
S S
A A A
S S
9 9
R F
RCa RCa RCa RCa UfD,RCO UfO, RCa
UlD,RCO,MM UfD, RCa, MM UfD, RCa, MM
= Rising-Edge Triggered = Falling-Edge Triggered
Up/Down Ripple Carry Output Max/Min Output
7472XA 7472XB 7473X 7474X 74112XA 74112XB
Latches
(2) AND-Gated JK Master/Slave (2) AND-Gated JK Master/Slave (2) JK with Clear (2)D with Preset and Clear (3) JK with Preset and Clear (2) JK with Clear
7475X 7477X 74259XA 74259XB 74373X
Multiple Flip-Flops (Registers) 74174X 74175X 74273X 74378
Extras
F F F
A A A
Single Flip-Flops
74377
Clk R R R R R R R R R R R R R R R R
(6) (8) (8) (8) (6)
Hex D Quad D with Q and /Q Octal D Octal D with Common Enable Hex D
4-35
(8) (4) (8) (8) (8)
4-Bit Bistable Quad D-Type Octal Addressable D-Type Octal Addressable D-Type Octal D-Type
AB·18
Shift Registers 7491 7495XA 7495XB 7495XC 7496X 74164 74165X
(8) 8-Bit-Serial-In, SeriaI-Out (4) 4-Bit-Serial-InlParailel-In, Parallel-Out (4) 4-Bit-S~rial-InlPai-iillel-In, Parallel-Oui' (4) 4-Bit-SeriaJ~InlParallel-In, Parallel-Out (5) 5-Bit-,-Serial~In/Parallel-In, Parallel-Out . (8) 8-Bit-Serial-In, Parallel-Out (9).8-Bit-Serial-In/Parallel-In, Serial ~Out . .. '
74194 74395XA 74395XB
,',
.
(4). 4-Bit Bi-Directional-,Serial-IniParailel-In, Parallel-Out (5) 4-Bit CascadableSerial-IniParailel-In,. Parallel-Out (5) 4-Bit Cascadable- ..' Serial-In/Parallel-In" Parallel-Out
Miscellaneous 7482X 7483X 7485X 7487 74143X 74180X 74180XA 74182 74183 74280X
(4) (8) (7) (4) (17)
2-Bit Adder 4-Bit Adder 4-Bit Magnitude Comparator 4-Bit True/Complement Element 4-Bit Counter; 4-Bit Latch; 7 Seginent Decoder '" (4) 8-Bit Parity Qenerlitor.(Checker .(4) . 8-11itParity. Gen~rato~/Checker: (5) L09k"Ah~d Carry Generator (2) Single-Bit Full Adder with Carry/Save (5) 9-Bit Odd/Even Parity Generator/ Checker
DE MORGAN EQUIVALENTS (BUBBLE GATES) Bubble 2 Input Sinput 4 Input Sinput Sinput 12 Input
AND (NOR) BAND2 BANDS BAND4 BANDS BAND8 BAND12
Bubble
. Bubble
Bubble
, NOR NAND. 'OR (OR) ·.(AND) (NAND) BNAND2 EiNOR 2 ,BOR2 BNANDS ' BNORS BORS BNAND4 BNOR4 BOR4 BNAND6 BNORS BORS SNAND8 SNORS BORS BNAND12 BNOR12 BOR12
INPUTIOUTPUT MACROS INPUT
N/A Generates Input Pin. and. Node in ADF OUTPUT (1) Generates Enabled Output Buffer in ADF ." .OUTP. 74125.· :74126
(1) Output Pi~(Used in SCHEMA 11PLD) (1) Single Three-State Output, Active Low Enable (1) Single Three-State Outp~t, Active High Enable NOTES:
1. All TTL macros duplicate TTL function only. They
DO NOT DUPLICATE performance characteristics such as open-collector, totem-pole, or high-drive out. . . put.' 2. Any TTL macros which deviate in some way from standard TTL function' are denoted with. an appended "X" (see device .DOC· file for details). Appended "D"s and "Q"s' indicate counters configured to Decimal or bi-Quinary mode; appended "A"s and "B"s indicate a macro configured for a. family of EPLD de. .. vices (e.g. 5C060, 5C090, 5CI80). 3. The (#) indicates the maxhD.um number of EPLD macrocells consumed if all' outputs are used. If an output is not used, the macro compression phase of the Macro Expander will remove the signal ~less it is used as feedback inside the' macro defmition. 4. /Q's should be avoided' as pin outputs if possible. The EPLD is structured such ,that the. Q is readily available as a pin output and both the Q and /Q are readily available as feedbacks. Using /Q as a pin output, however, requires an extra macrocell and adds to the propagation delay. . .
