ACT (Audio Comparison Tool)

Created By: Zeddy He Nate Wennyk, Benny Zhang Brian Zhang March 6, 2010

1. Design Introduction This team proposes to create an audio track processing system on the DE1 FPGA board. The purpose of this system is to compare how similar two audio tracks are based on various factors such as frequencies and beats. This project will consist of three phases each exploring a different process and using different functionalities of the DE1 FPGA board. Part 1: Perform an Analog to Digital Conversion using the built-in wm8731 chip on the DE1 FPGA board. The sampled data from the chip will be sent to registers built in on the board. Part 2: A comparison system needs to be made to fulfill the purpose of this design. An algorithm will be designed to compare a new input audio track to another audio track in the storage registers. The algorithm is based on comparing bits in sampled points on both audio tracks. Part 3: The last part of the system is to output the results to the Seven Segment Display. A designed interface will be used to communicate with the Seven Segment components on the board which will output information found in part 2. The currently planned output is the number of match bits between the two tracks.

2. Function Description The Audio Comparison Tool (ACT) was implemented using VHDL hardware logic as well as using several board components on the Altera DE 1 board. The hardware logic was implemented as a finite state machine composed of three main states and a one setup state. The following diagram summarizes the finite state machine. In terms of components, the ACT device interfaces with the 7 Segment Display output, the Altera DE 1 board’s registers and the Altera DE1 WM8731 audio chip.

SETUP

Counter = 30 Counter = 100

PAUSE

sw(7) = 1

STORE

sw(8) = 1

Counter = 100

COMPARE

Diagram 1. Finite State Machine Representation of ACT Device

The DE 1 board, once turned on, starts at the SETUP state which initializes the audio chip. Each of the main states could be broken down into several states (30 to 100 states) but, instead, has a counter associated with. Once the counter reached a certain value, the device proceeds to the next main state. This was done because in order to interface with WM8731, I2C must be used to send data to the device which can only take one bit at a time per clock cycle. The device enters the other states when the user gives inputs using switches 7 and 8. The STORE state reads 100 bits from the audio in line and stores them to the registers. The COMPARE state reads 100 bits from the audio line in and compares the read bits with the bits stored in the registers. Any differences in the comparison are output to the Seven Segment Display.

3. Performance Parameters The main performance parameter was the maximum time delays allowed by the WM8731 chip. The list of constraints can be found on page 17 and 19 of the datasheet which is found at http://www.wolfsonmicro.com/uploads/documents/en/WM8731_Rev4.4.pdf . The BCLK is synchronized with the main clock of the process within the ACT description. This means that there is a maximum frequency that the design can run at. According to the datasheet, this frequency equates to 20MHz. The more constraining frequency is actually the frequency of the audio input itself. The common rate is 44.8KHz meaning that a bit can be parsed in every 22μs. Another performance parameter was put in place by our design. We wanted to utilize the FPGA’s ability to create registers to store bits but storing a full audio file would require too many registers to be effective. We decided to limit ourselves to a 100bit string to represent an audio file. This meant that if we are sampling every bit (1 every 22μs) then we could only store 2ms of audio. To get around this limitation, we expanded the interval between samplings to once every second. This allows a song of a minute and a half in length to be stored and compared. The clock cycle frequency we decided upon was 16Hz. This allows a single audio sample every second as well as staying above the minimum times outlined in the datasheet. Once our design was created, the timing analyzer tool in the Quartus II program found that the longest path takes 42.8ns to travel but it is between the output from the audio chip to the hex1 display. There is 4.5ns between the rising edge of the i2c_sdat and the i2c_sclk but that is below the absolute max of 300ns. When the FPGA was programmed with this file the ACT was tested to verify that all the timing constraints were met. The design acted as expected, allowing a song to be stored and then allowing other songs to be compared to that song in storage. Without the Altera FPGA, it would not have been possible to test this design in the short amount of time made available in this competition period. This ability to shorten the time between design and product is one of the many great features made possible with the Altera FPGA.

4. Design Architecture

5. Design Methodology Detailed Overview of Interfaces The VHDL code of the ACT device contains two main entities. The ‘SevenSegmentDisplay’ entity was used in order to give the user output. The ‘ACT’ entity contains all the logic behind the device. In order to simplify the VHDL code of the device, the following important signals were declared for use within the device. Table 1. Important Signals Used in ACT Device Signal Name state

Signal Type Modes (SETUP, PREP, PAUSED, STORE, COMPARE);

storage

UNSIGNED(99 Downto 0)

MainClk

UNSIGNED(0 Downto 0)

The state signal was used to keep track of which state the device is currently in. Storage is the signal connecting the device to the registers, supporting the storage of bits. The MainClk is the main driving clock for the device running at a frequency of 16Hz. This frequency was achieved with a clock divider using the board’s 50 MHz clock.

The interface with WM8731 was built using I2C and several pins on the chip. The pins used are summarized in the table below along with its respective signal type. Table 2. Pins Used to Interface with WM8731 Pin Assignment

Signal Type

Direction From Chip

i2c_sdat

STD_LOGIC

In/Out

i2c_sclk

STD_LOGIC

In

aud_adcdat

STD_LOGIC

Out

aud_adclrck

STD_LOGIC

In

aud_bclk

STD_LOGIC

In

aud_xclk

STD_LOGIC

In

The i2c_sclk, aud_bclk and aud_xclk are all fed from the 16Hz clock from the MainClk signal. These clocks are used by the audio chip to determine the rate that signals are being sent in and out of the audio chip. The i2c_sdat signal was exclusively used for sending data to the audio chip during the SETUP state. The aud_adcdat and aud_adclrck signals are used during the STORE and COMPARE states. The aud_adcdat signal is used to send output data from the audio chip and the aud_adclrck signal determines which audio input to output (left or right line in) to use.

Several pins were used to communicate with the user as well. These pins are summarized in the table below along with its respective signal type. The main types of output and input devices used are the switches, the LED displays and the 7 Segment Displays. Table 3. Pins Used to Interface with the User Pin Assignment sw

Signal Type

Direction From Device

UNSIGNED

In

hex0 STD_LOGIC_VECTOR

Out

hex1 STD_LOGIC_VECTOR

Out

hex3 STD_LOGIC_VECTOR

Out

ledr STD_LOGIC_VECTOR

Out

ledg STD_LOGIC_VECTOR

Out

Detailed Overview of States SETUP State The setup state runs as soon as the device turns on. Two separate 30-bit sequences are sent to the audio chip, one bit at a time, through the I2C signal in order to set it up for use. The following table summarizes the information sent in the SETUP state.

Table 4. Bit Sequences Sent to Audio Chip in SETUP and PREP State. Bits

Description

SETUP

PREP

0

Raises the level of i2c_sdat signal to allow a drop to follow

1

1

1

Tells the chip to start accepting bits. Always should be ‘0’ and follow a ‘1’

0

0

2-6

Base address for the WM8731 chip

001101

001101

7

Tells the chip what mode to operate in. (3 wire or 2 wire mode)

0

0

8

Tells the chip that a write was made to it.

0

0

9

Let go of the i2c_sdat signal

X

X

10-18

Tells the chip the address of the register to modify. (also known as the control address bits)

00010010

00001110

19

Let go of the i2c_sdat signal

X

X

20-27

Information bits. Refer to the data sheet for specific meaning.

00000001

00110001

28

Let go of the i2c_sdat signal

X

X

29

Tells the chip to stop accepting bits. Always should be ‘0’.

0

0

SETUP is used to tell the chip to reset (i.e. to turn on). PREP sets the main configurations of the chip. For more information, refer to the WM8731 Datasheet Pages 44 to 53.

PAUSE State This is an intermediate state which waits for user input. Equivalent to an idle state

STORE State The store state utilizes the aud_adcdat and aud_adclrck signals to get data from the audio chip. A counter counts from 0 to 99 at a 1Hz frequency. At every count, the aud_adclrck is inverted to essentially tell the chip to start sending data from the next input. This allows a sample to alternate

from the left line in and right line in. The most significant bit sent is then stored in the storage register. This state essentially samples 100s of audio.

COMPARE State Similar to the STORE State, this state also uses the aud_adcdat and aud_adclrck signals and the 1Hz counter. Instead of storing it this time, the bit is compared to the stored bit. If the bits do not match, then a counter, starting at 100, for the hex display decreases.

6. Design Features Our design, the Audio Comparison Tool, uses the on-board WM8371 sound chip as audio input and the Seven-Segment Displays as our comparison output. Its first feature is a meticulous sample rate capable of recording several minutes of input audio. Each bit is stored in the board's registers eliminating the need for external storage. A second feature is the ability to switch between loading and comparing audio. Therefore, no song libraries need to be imported for a comparison to occur. A percentage on the SevenSegment Displays will show the similarity between the two audio files in real time as the second song is sampled. Due to the flexibility and simplicity of these two features, any length of track between any two songs can be efficiently sampled to great accuracy.

7. Conclusion This project was undertaken during our academic term where we were introduced to VHDL, the Altera DE 2 board and hardware design methodology. The most complex of the topics learned were finite state machine design and its implementation on the Altera DE 2. As a precursor to this project, and as a final lab project in that course, we designed a simple finite state machine system in VHDL. As our team joined the ASIC group on campus, we were naturally looking towards the enrichment of our current knowledge; we decided to put our focus on using the audio chip. Altera provided us with the opportunity through this competition. As an added bonus, we were introduced to the Altera DE 1 board and had to learn about its functionality in performing this project. As this project progressed, we spent time learning the hardware components of the Altera DE 1 board in order to see what kind of project to perform. Some specific elements that we learned during the design included learning about how to use the I2C data communication method used by the WM8731 audio chip, studying the audio chip data sheets on how to interface with the device and interacting with the output devices present on the DE 1 Board. During the process of applying the overview design to specific VHDL code, we learned how to build entities, how to pass data through signals, and how to implicitly store data in signals and variables. This involved us expanding our knowledge in using the Quartus 2 development environment. We found that there was no pin assignment for the CSB pin of the WM8731 chip which forced us to use the 2-wire interface. We applied our knowledge of the I2C bus to circumvent this issue. Learning how to control a device through a bus is important. It does no good to put a device on a board that we cannot control. Altera takes this concept to a new level by making the main controlling chip FPGA so that it can be controlled. In this manner, the flexibility of the DE1 board was instrumental to the success of our design and the growth of our knowledge with regards to ASIC designs.