Chapter 3: Active-Device Realizations of Basic Feedback Systems July 8, 2007
Prof. K. Radhakrishna Rao
[email protected]
Dr. Sundararajan Krishnan (PK)
[email protected]
July 8, 2007
Contents 1 Introduction
2
2 Transistors as Active Elements 2.1 The Bipolar Junction Transistor in the Active Region . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2 The Metal-Oxide-Semiconductor FET (MOSFET) in the Active Region . . . . . . . . . . . . . . . . .
2 3 5
3 The Basic Current Mirror 8 3.1 The Diode-Connected MOSFET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 3.2 The Basic MOSFET Current Mirror . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 4 Feedback Techniques to Design Improved Current-Mirrors 4.1 Small-signal Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.1.1 The Cascode Current-Mirror using MOSFETs: A z-feedback Circuit 4.1.2 The Wilson Current Mirror using MOSFETs: A g-feedback Circuit . 4.1.3 The Basic BJT Current-Mirror . . . . . . . . . . . . . . . . . . . . . 4.1.4 A Technique to Increase the Loop-Gain . . . . . . . . . . . . . . . . 4.1.5 The Wilson Current Mirror using BJTs . . . . . . . . . . . . . . . . 4.2 Large-Signal Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.2.1 The MOSFET-based Cascode Current Mirror . . . . . . . . . . . . . 4.2.2 Wide-swing Cascode Current Mirror . . . . . . . . . . . . . . . . . . 4.2.3 Wilson Current Mirror . . . . . . . . . . . . . . . . . . . . . . . . . .
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11 11 11 13 16 17 17 20 20 22 23
5 The Translinear Principle 5.1 Applications of Translinear Networks 5.1.1 Obtaining Linear Functions . 5.1.2 Multipliers . . . . . . . . . . 5.1.3 Squaring . . . . . . . . . . . . 5.1.4 Vector Sum and Difference . 5.2 Translinear Principle in MOSFETS .
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July 8, 2007
1
Introduction
Our objective in this chapter is to understand active-device realizations of basic feedback systems; We will learn about the diode-connected transistor as a feedback network and use this idea to develop an understanding of current mirrors as biasing structures, as current amplifiers and as current-controlled current sources. We will further extend the idea of current-mirrors using the translinear principle to realize complex signal-processing functions. We will also study some of the well-known current-mirror structures in the context of current-feedback amplifiers. To get there, though, we need to first understand the behaviour of the active devices. We would like to mention here that our purpose in discussing devices is only to derive an equivalent-circuit model that we can use for understanding the behaviour of the various circuits. The discussion on devices will be brief to the point of being simplistic. The reader is referred to [1], [2] and [3] for a detailed discussion on the physics, the fabrication and the modeling of active devices.
2
Transistors as Active Elements
Let us suppose that we are interested in active-devices that behave as voltage-controlled current sources. One can then define the transconductance of these devices to be given by ∂i0 (1) ∂vi where Ioq is the quiescent operating current and Viq is the quiescent operating input voltage at which the device remains active (i.e. capable of giving power gain). One way to classify these devices would be to differentiate between them based on the behaviour of the transconductance, gm . In other words, we can have gm |(I0q ,Viq ) =
1. gm proportional to i0 (or) 2. gm proportional to vi Let us now consider each of these cases in more detail ∂i0 ∂vi ∂i0 i0 ln i0 i0
= k · i0
(2)
= k · ∂vi
(3)
= k · vi + c = Ic0 ekvi
(4) (5)
The other type of active device can be realized as shown below. ∂i0 ∂vi i0
= k · (vi − VT )
(6)
k 2 (vi − VT ) 2
(7)
=
Equations 5 and 7 describe the relationship between output current and input voltage for a Bipolar Junction Transistor (BJT), and a Field Effect Transistor (FET), respectively. Page 2 of 39
July 8, 2007
C
E
ic B ib
ie B ib
ic
ie E
C
Figure 1: n-p-n and p-n-p Bipolar Junction Transistors These devices perform data expansion (by nature of the exponential/squared relationship between current and voltage) and hence, they can be used in signal processing as data expanders. Let us now consider these devices in more detail by considering their action in the active region. We will not delve into great detail on either device, but instead understand the basic principle of operation, and derive a simple equivalent-circuit model for each device. Such a model will suffice for our purposes of understanding the fundamental principles behind the various claases of circuits is vogue today.
2.1
The Bipolar Junction Transistor in the Active Region
A BJT is formed by connecting two p-n junction back to back. To obtain transistor action, one juction is forwardbiased while the other is reverse-biased. In very simple terms, the forward-biased (base-emitter) junction emits carriers that are collected by the reverse-biased (base-collector) junction. The various terminals in a BJT are called emitter, collector and base. Since there are two types of carriers (electrons and holes), we can visualise two different BJT configurations, namely, the npn configuration and the pnp configuration. Figure 1 shows the symbols, and the current and voltage polarities for both configurations. In an npn transistor, the emitter emits electrons which are collected by the collector. When these electrons pass through the base, some of them recombine with the holes in the base. The recombination current is provided by the base and contributes to the base current. The current gain of the BJT is given by the ratio of collector to base current. The current gain of an ideal BJT is infinity. Let us now consider the various equations that describe the behaviour of BJTs. ie is the instantaneous emitter current and ic is the instantaneous collector current. VBE is the base-emitter voltage. ie ic where Vt
= Ie0 eVBE /Vt = αie kT = q = 25 mV at room temp
Ie0 is called the reverse saturation current. Page 3 of 39
(8) (9) (10) (11)
July 8, 2007 The transconductance of the BJT can now be obtained by differentiating the collector current with respect to the base-emitter voltage and is given by,
gm
∂ic ∂vBE Ic Vt qIc kT
= = =
(12) (13) (14)
To understand the practical effects of BJT-based circuits, a more detailed model is necessary. To realize the detailed model, let us first compute the output resistance. The output resistance in a BJT arises because of basewidth modulation; An increasing reverse-bias on the base-collector junction increases the depletion-width of the junction. Depending on the ratio of base to collector doping, the depletion region will extend into the base. This alters the collector current. The effect can be modeled using the following equations.
ic
= αIs0 eVBE /Vt (1 + = Ic (1 +
VCE ) VE
VCE ) VE
(15) (16)
where VE is called the Early Voltage. The output resistance is now given by
gce
= =
rce
=
∂ic ∂vce Icq VE VE Icq
(17) (18) (19)
Depending on the doping of the emitter layer and the dimensions of the emitter ’finger’, a parasitic resistance (Rex ) is present in series with the emitter of the transistor. The effect of this resistance is to make the transistor deviate from the exponential behaviour; In other words, the transconductance will not be proportional to current anymore. This can be modeled as shown below. 1 gm−ef f
=
gm−ef f
=
1 + Rex gm gm 1 + gm · Rex
The effect of recombination current can be modeled using a resistance between the base and emitter.
Page 4 of 39
(20) (21)
July 8, 2007
Ccb
B Cbe
rbe
gmVbe
C
rce
rex E Figure 2: High-Frequency Model for the BJT
Ie Ib
rbe =
VBE Ib
= gm VBE Ie = β+1 gm VBE = β+1 VBE = re (β + 1)
(22)
= re (β + 1)
(26)
(23) (24) (25)
To obtain a reliable high-frequency model, we should also consider the various capacitances. In addition to the depletion capacitances associated with each junction, there are also a number of parasitic capacitances that need to be considered. The overlap between the base and collector semiconductor layers results in a parasitic base-collector capacitance. A parasitic capacitance from the collector to ground is also present (and is typically very small in magnitude). In addition, a diffussion capacitance is present between the base and emitter terminals, and is equal to gm τf , where gm is the transconductance, and τf is the transit time. The complete equivalent circuit is shown in figure 2
2.2
The Metal-Oxide-Semiconductor FET (MOSFET) in the Active Region
The MOS transistor is fundamentally different from the Bipolar transistor in the way it works, although, as we will see later, there is considerable similarity in their small signal behaviour. Let us begin by considering the two-terminal MOS structure shown in figure 3. If the Gate terminal is at a higher potential than the substrate, electrons get accumulated just below the oxide. As the potential-difference is increased, the number of electrons accumulated will also increase. At a certain potentialdifference, the number of electrons near the oxide-substrate interface will be equal to the native holes, rendering the semiconductor neutral. Any further increase in the potential-difference will make the substrate at the oxidesubstrate interface appear n-type in nature. This phenomenon is called inversion, and the potential-difference at which inversion starts to occur is called the threshold voltage, VT . The inverted region is called the channel. To Page 5 of 39
July 8, 2007
Gate(Metal) Oxide
Semiconductor p−type
Figure 3: A two-terminal MOS structure obtain transistor action, the channel is contacted by two terminals, located at either end of the channel as shown in figure 4. These terminals are called the Drain and Source terminals. The current through the channel is determined by the potential-difference applied across the drain and source terminals. To summarize, the presence of a channel is determined by the gate-source voltage, while the current through the channel is determined by the drain-source voltage. We will now consider each of these dependencies in more detail. Depending on the potential-difference between the gate and the source terminals (VGS ), the channel is either absent, depleted of heavily inverted. We can hence define three regions of operation as shown below 1. Cutoff when VGS << VT 2. Subthreshold when VT > VGS > VT - 0.3 3. Inversion when VGS > VT The resistance of the channel is modulated by the difference between the gate-source voltage (VGS ) and the threshold voltage (VT ), and this voltage difference is called the over-drive voltage and is denoted by VEF F , VON or . As one would expect, the current through the channel depends on the conductance of the channel, as well as the potential-difference across the drain and source terminals (VDS ). At zero bias, the channel is uniform from drain to source. As the drain voltage is increased relative to the source, the depletion width near the drain terminal increases. As a result, the channel near the drain becomes less inverted. At a certain drain-source bias, the channel ceases to exist near the drain terminal. This occurs when VDS is equal to VON . If VDS is increased further, the carriers that flow in the channel will simply be swept across the depletion region. In other words, the current in the channel shows only a weak dependence on the drain-source bias once the drain-source bias exceeds the over-drive voltage. The device is then said to be in saturation. The weak dependence of the channel current on the drain-source bias is due to channel-length modulation. Re-phrasing the idea using equations, we can think of two regions of operation for the MOSFET. 1. Linear when VDS < VON 2. Saturation when VDS > VON Let us now compute the drain current (the current through the channel) in the various regions. The source current is equal to the drain current since the gate is isolated by the oxide and takes no DC current ). 1. Cutoff Region ID = 0; Page 6 of 39
July 8, 2007
G D
S
n+
n+ Semiconductor p−type
channel
Figure 4: An n-channel MOSFET 2. Subtreshold Region ID = ID0 e
qVGS nkT
(1 − e
qVDS nkT
)
(27)
Where n is typically close to 1 For large VDS , ID = ID0 e
qVGS nkT
(28)
3. Inversion Region (a) Linear ID = µCox
W (VGS − VT )VDS (1 − VDS /2) L
(29)
W 2 (VGS − VT ) (1 + λVDS ) 2L
(30)
(b) Saturation ID = µCox
Assuming that the MOSFET is now biased as desired, we can obtain a linear, small-signal model in a manner similar to what we adopted for the bipolar transistor. Saturation Region
Page 7 of 39
July 8, 2007
gm
= = =
gds
= = =
Cgs
=
∂id ∂vgs r
(31)
µCox
W ID L
2ID VGS − VT ∂id ∂vds W 2 µCox (VGS − VT ) λ 2L λID 2 Cox W L 3
(32) (33) (34) (35) (36) (37)
Cgd = overlap capacitance of Gate and Drain Linear Region gm
=
∂id ∂vgs
= µCox gds
=
(38) W VDS L
∂id ∂vds W (VGS − VT ) L Cox W L 2 Cox W L 2
(39) (40)
= µCox
(41)
Cgs
=
(42)
Cgd
=
(43)
Subthreshold Region Since the expression of the current is exponential with VGS , the gm and g( ds) expressions are similar to the bipolar transistor and is left as an exercise for the reader. We have just seen the low frequency small signal model of a MOS transistor. For high frequencies, we need to add the parasitic capacitances of the reverse biased junction diodes formed by the source and drain to the substrate to the model.
3 3.1
The Basic Current Mirror The Diode-Connected MOSFET
Consider the diode-connected MOSFET shown in figure 5. To analyze this circuit, let us first consider its nullatornorator equivalent. Starting from the nullator-norator equivalent of a MOS transistor, we can obtain the equivalent of the diode-connected MOSFET by simply shorting the gate and the drain terminals (shown in figure 6). Page 8 of 39
July 8, 2007
i
Figure 5: The Diode-Connected MOSFET
G
D
S MOS transistor
Diode-Connected MOS
Figure 6: Nullator-Norator Equivalent of the Diode-connected Transistor The equivalent circuit realized for the diode-connected MOSFET is the same as the nullator-norator equivalent for a Short Circuit. Hence, this structure can sink any amount of current. In practice, it develops the voltage to sustain any current through it automatically. Here, drain current is the independent variable, and gate-source voltage is the dependent variable. We can also analyze this as a feedback circuit. The output current is fed back to the input. Further, since the current gain is infinity, the loop gain is infinity. As a result, this circuit will perform the inverse function. In other words, in the forward direction, the relation between input voltage (VGS ), and output current (ID ) is a squaring function. Now, due to the large forward gain, the drain current will generate a gate-source voltage that exhibits a square-root dependence on the current. This is explained in the following equations.
ID r VGS = VT +
2ID k
=
k 2 (VGS − VT ) 2
= VT +
(44) (45)
The same circuit can also be realized by using a BJT instead of a MOS transistor. The input voltage (VBE ) would then have a logarithmic relation to the current.
Page 9 of 39
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I
M
S
Figure 7: The Current-Mirror Concept
3.2
The Basic MOSFET Current Mirror
Returning to the MOS diode-connected transistor, we can now treat this as a master transistor that develops the voltage necessary to sustain any current iD across other slave transistors. Let us consider the circuit shown in figure 7 The equations that govern the behaviour of the two transistors, M (master) and S (slave) are given below r VGSM VGSS r
2iDM + VT M kM
=
2iDM + VT M kM
= VGSM r 2iDS = + VT S kS
(46) (47) (48)
If the MOSFETs are identical, then we have VT S = VT M ; kM = kS In general, though, as g0 . Then,
kM kS
is the gain of the current-mirror. In the subsequent equations, we will refer to this term
iDS = iDM = I
(49)
This is the basis of what is popularly known as the current mirror. The slave MOSFETs simply reflect the current of the master as long as they are also biased under similar operating conditions. Such a circuit can also be viewed as a CCCS obtained by cascading a CCVS (the diode-connected master MOSFET) with a VCCS (the slave MOSFET). The ideal current-mirror (CCCS) would be described by the following h-matrix.
Page 10 of 39
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h=
0 g0
0 0
(50)
Let us now compute the h-matrix for the basic current-mirror to understand its limitations. 1. h11 : The input impedance of the circuit is decided by the diode-connected MOSFET and is
1 gm−M
2. h12 : h12 = 0 3. h21 : Let us assume that the master transistor has a drain-source voltage of VDSM while the slave transistor has a drain-source voltage of VDSS . The ratio of output to input currents can then be expressed as h21 =
iS kM (1 + λVDSM ) = ≈ g0 [1 + λ (VDSM − VDSS )] iM kS (1 + λVDSS )
(51)
4. h22 : The output impedance is rds−S of the slave transistor; h22 is hence gds−S . The h-matrix is hence given by h=
1 gm−M
0
g0 [1 + λ (VDSM − VDSS )] gds−S
(52)
By comparing the matrices in equations 50 and 52, we can see that the limitations of the basic current-mirror are its relatively-low output resistance and the mismatch between the input and output currents. (Note that we have not modeled any random mismatch that might arise between devices; we will discuss the effect of random mismatch when we discuss offsets - The static mismatch in the currents is also called the systematic gain error ). One technique to make the CCCS more ideal is to use feedback.
4
Feedback Techniques to Design Improved Current-Mirrors
We will consider several circuits and to facilitate a proper comparison between them, we will look at the small-signal performance as well as the head-room requirements for the various circuits.
4.1 4.1.1
Small-signal Performance The Cascode Current-Mirror using MOSFETs: A z-feedback Circuit
The output resistance of the basic current-mirror is decided by the VCCS. Hence, one can envision Z-feedback (series at the input, series at the output) as a possible method to improve the output resistance. The simplest way to do it is to degenerate both the master and slave transistors of the basic current mirror with a resistance R. Better still, we can degenerate the master and slave transistors with another pair of transistors as shown in figure 8. This circuit is known as the Cascode Current Mirror. Let us consider only the VCCS-section of the circuit. The VCCS comprises of transistors M3 and M4. Let us now compute the loop gain by using the composite matrix.We will assume that the small-signal parameters of M3 and M4 are equal for ease of calculation. The Z-parameters of the forward block (M3) is given by
Page 11 of 39
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I
M1
M3
M2
M4
Figure 8: The Cascode Current-Mirror
Zf =
Ri −gm · Ri · rds
0 rds
(53)
where Ri , gm and rds refer to the input resistance, transconductance and output resistance of M3, while the Z-parameters of the feedback block are given by rds rds Zr = (54) rds rds The composite matrix, Zcomp , is given by Zcomp =
Ri + rds −gm · Ri · rds + rds
rds 2 · rds
(55)
The output impedance is given by
Rout
Z21−comp · Z12−comp = Z22−comp 1 − Z11−comp · Z22−comp (gm · Ri · rds ) · rds ≈ 2 · rds 1 + Ri · (2 · rds ) 2 ≈ 2 · rds + gm · rds
Page 12 of 39
(56) (57) (58)
July 8, 2007 Alternately, we could have ignored the fact that this is a feedback circuit and simply used nodal analysis to obtain the output impedance (The reader is strongly urged to check that nodal-analysis gives the same result). At this point in time it is quite possible that a number of readers find the composite-matrix method far more tedious than the nodal-analysis technique. With some practice, we will be able to write the composite matrix, and hence, the expression for the loop-gain by inspection. We will then be able to compute the driving-point impedances at the input and output without writing any equations. Considering that familiarity might be a substantial reason for favouring nodal-analysis at this point, we suggest that the readers try the composite-matrix technique on several single-stage and multi-stage feedback amplifiers (discussed in Chapter 4 of this text) before attempting a comparison on the relative merits of each technique. Let us now see how the cascode-mirror performs with respect to the mismatch in current between the input and the output. Referring to figure 8, and assuming appropriately sized transistors, we have ≈ VGS4 ≈ VGS3 = VDS2
(59) (60) (61)
= VDS2 + VGS1 − VGS3 ≈ VDS2
(62) (63)
VGS2 VGS1 VGS2 Let us now compute VDS4 using equations 59 - 61 VDS4
Since M2 and M4 (the tail transistors) have the same drain-source voltage, the mismatch between the currents in the cascode current-mirror would be much lesser than the mismatch in the basic current-mirror (refer equation 51) The reader should note here that the two advantages (better output resistance, better matching) that the cascode current-mirror offers over the basic current-mirror arise because of different reasons. The higher output resistance is due to the series feedback (in other words, due to current-buffering) while the matching improves because we forced the drain-source voltage of M2 and M4 to be the same by adding a gate-source voltage drop in the loop using transistor M1. In this technique, the idea was to improve the output resistance by employing series-feedback on the VCCS section of the CCCS. As an alternative, we can use g-feedback (shunt at the input; series at the output) to design a near-ideal CCCS. We will consider this in the following section. 4.1.2
The Wilson Current Mirror using MOSFETs: A g-feedback Circuit
To build an ideal CCCS, we need to sense the output current and feed it back as voltage at the input. One candidate for the feedback network is the current-mirror. We know that the diode-connected transistor is capable to sustaining any current through it. In other words, it can sense the current flowing through it and adjust its gate-source voltage to sustain this current. This gate-source voltage can now be fed to a slave transistor. By making the load impedance of this slave transistor high, we can get sufficient gain. The resulting schematic is shown in figure 9. One way to compute the loop gain is to use the composite-matrix method. The other technique is to break the loop at a certain point, and traverse the loop to compute the loop gain. For example, we can break the loop at point A in figure 9. The modified figure is shown in figure 10. The loop gain can be expressed as a product of the transfer function between successive nodes in the loop as shown in equation 65
Page 13 of 39
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Iin
I0 A
M1
M2
M3
Figure 9: The Wilson Current-Mirror
vi v0
M2
M1
M3
Figure 10: Loop-Gain for the Wilson Mirror
Page 14 of 39
July 8, 2007
Iin I0 M4
M2
M1
M3
Figure 11: The Wilson Current-Mirror - Final Schematic
gl
= =
v0 vi v0 va · va vi
(64) (65)
MOSFETs M2 and M3 form a potential divider and assuming equal gm ’s va 1 = vi 2 The other term in equation 65 can be computed as v0 = gm · rds va Substituting equations 66 and 67 in equation 65, we can calculate the loop gain to be gl =
gm · rds 2
(66)
(67)
(68)
The output resistance can now be easily calculated r0
= rds (1 + gl ) (69) gm · rds = rds 1 + (70) 2 The circuit proposed in figure 9 suffers from ’lambda-effect’ since the VDS of M1 is greater than the VDS of M3 by a diode voltage. This problem can be solved by adding a diode in the master path as shown in figure 11. It must be noted that the diode does not affect the ac signal-picture. Page 15 of 39
July 8, 2007
I
Figure 12: The Diode-Connected BJT 4.1.3
The Basic BJT Current-Mirror
The ideas detailed in the previous section do not use a characteristic particular to the MOSFET and can hence be used in bipolar transistor design as well. Bipolar transistors, though, have finite collector current-gain (β) and hence, the mismatch in static currents is primarily due to the various base currents. For example, consider the diode-connected transistor shown in figure 12. Analyzing this as a feedback circuit with forward gain, β, the output current (in this case, the collector current of Q1) is given by Ic−Q1 =
β · Iin β+1
(71)
One can now realize a basic BJT current-controlled current-source by applying the base-emitter voltage developed by the master transistor (Q1) to a slave transistor (Q2) as shown in figure 13. Assuming that the emitter-junction area of Q2 is n-times that of Q1 and further assuming that the current-gains of the transistors are the same, we can compute the h-matrix of the CCCS to be The h-matrix is hence given by # " 1 0 gm−Q1 (72) h= β gce−S n β+n+1 A difference between the MOSFET and BJT current-mirrors is clear from equation 72. In the absence of random mismatch, the MOSFET current-mirror is more immune to large mirroring-ratios than the BJT current-mirror. If the MOSFET transistor were to exhibit considerable gate-leakage, though, its behaviour would be very similar to that of a BJT current-mirror. Let us now look at some techniques that can be employed to make the BJT CCCS more ideal. To achieve this, we need to reduce the static mismatch and increase the output resistance.
Page 16 of 39
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Iin I0
Q1
Q2
Figure 13: The Basic BJT Current-Mirror/CCCS 4.1.4
A Technique to Increase the Loop-Gain
The mismatch between the input current and the collector current in the diode-connected BJT (shown in figure 12) is due to the finite loop-gain, β. If we could somehow increase the loop-gain, we can decrease the mismatch between the input current and the collector current. One way to achieve this is to use another transistor - as shown in figure 14 - between the collector and base of Q1. This increases the loop-gain from β to β (β + 1). We can now realize a current-controlled current-source by applying the base-emitter voltage developed by Q1 to Q2 as shown in figure 15 The h-matrix is given by " # 1 0 gm−Q1 h= (73) β(β+1) n β(β+1)+n+1 gce−S Since the feedback operates only on the master transistor, this technique does not improve the output resistance of the CCCS. In the following section, we will see how to modify the current-mirror of figure 15 to enhance the output resistance. 4.1.5
The Wilson Current Mirror using BJTs
To enhance, the output resistance, we need to modify the circuit shown in figure 15 in such a way that the feedback is not restricted to the master path. One way to do this is to make Q2 a diode-connected transistor and use the collector current of Q3 as the output current as shown in figure 16. This circuit is known as the Wilson current-mirror [4]. Let us compute the error between the input and output currents as well as the output resistance for this circuit. 0 To compute IIin for this circuit, let us redraw the circuit as a control system. (We must remember that the block-diagram approach used by control-system engineers is an easy way to calculate the transfer function and does not account for the effect of loading - To compute the entire matrix, we should use the composite-matrix method or nodal analysis) The block diagram is shown in figure 17.
Page 17 of 39
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Iin Q3 Q1
Figure 14: The Modified Diode-Connected BJT
Iin I0 Q3 Q2
Q1
Figure 15: The Modified CCCS
Page 18 of 39
July 8, 2007
I0 Iin Q3
Q1
Q2
Figure 16: The Wilson Current-Mirror using BJTs
Ιin
+
Ι0 Σ −
β
β+2
β+1
β+1
β
Figure 17: Block Diagram for Computing the Transfer Function
Page 19 of 39
July 8, 2007 The block-diagram was derived using the following approach. The current-gain of Q3 is the forward gain and is given by β. Q2 mirrors the emitter-current of Q1, and hence, we need to introduce a β+1 β block in the feedback path. Q2 and Q3 form a basic current-mirror whose transfer function is given by system transfer-function is given by I0 Iin
β β+2
(refer equation 72). The overall
β
=
1+β·
β+1 β
·
β β+2
β
= 1
+ β·(β+1) β+2 2
β + 2β + 2β + 2
=
β2
(74) (75) (76)
The static mismatch (systematic gain-error) between the currents is given by Ie Iin
I0 Iin 2 2 β + 2β + 2
= 1−
(77)
=
(78)
It is clear from equation 78 that the static-mismatch of the Wilson’s current mirror is almost a factor of β better than that of the basic current-mirror. Since we have realized a better CCCS than the basic current-mirror, this circuit will also exhibit a higher output resistance - the scaling factor given by (1 + gl ). To compute the loop-gain, we can use the same approach as we used for the MOSFET realization (refer section 4.1.2 and is left as an exercise to the reader. In a manner similar to what we adopted for the MOSFET realization, we can compensate for any static mismatch due to the different collector-emitter voltages in Q1 and Q2 by adding a diode in the master path. So far, we looked at the small-signal parameters for the various current-source realizations. We will now focus our attention on the large-signal behaviour of these circuits. In other words, we are interested in finding out the I-V characteristics of these circuits.
4.2
Large-Signal Performance
In this section, we will consider the headroom requirements for the cascode and Wilson current-mirrors. We are interested in finding out the minimum output-voltage required to support proper operation of the current-mirror as well as the input voltage required by the master path. Minimizing the former is important so that the current-source functions as desired (by maintaining the various transistors in the active region) over a wider range of voltages; the latter should be minimum to facilitate a low-voltage design. 4.2.1
The MOSFET-based Cascode Current Mirror
The circuit diagram (originally shown in figure 8) is repeated in figure 18 for convenience. The output voltage, v0 , is given by v0 = vDS3 + vDS4 Page 20 of 39
(79)
July 8, 2007
I
M1
M3
M2
M4
Figure 18: The Cascode Current-Mirror We know from equations 62 and 63 that vDS4 = vDS2 = vGS2 = VT +
(80)
vDS3 >
(81)
To maintain M3 in the active-region,
Using equations 80 and 81, we can calculate the minimum drain-source voltage as vout−min
= vDS4 + vDS3−min = VT + 2
(82) (83)
Since the master-path contains two diode-connected transistors (M1 and M2), the input voltage required by this structure is given by vin
= vDS1 + vDS2 = vGS1 + vGS2 = 2VT + 2
(84) (85) (86)
Let us now analyze these results in more detail. The slave path consists of two transistors in series (M3 and M4) and hence, the theoretical minimum for the output voltage is 2. The cascode mirror, though, requires a minimum Page 21 of 39
July 8, 2007
VT + 2ε
VT + ε
M3
M4
Figure 19: Optimum Biasing for Wide-Swing voltage of VT +2. To see if we can design for a lower voltage, let us re-examine our reasoning for the cascode topology. To minimize the gain-error between the input and output currents, we had wanted the drain-source voltages of M2 and M4 to be the same. By choosing M2 as a diode-connected MOSFET, we forced M4 well into the active region providing it with a larger drain-source voltage than required. In the following section, we will see how to meet the dual requirements of low voltage and minimum gain-error. 4.2.2
Wide-swing Cascode Current Mirror
The optimum-design in terms of output voltage is achieved if each transistor is provided with a drain-source voltage that is just sufficient to maintain the transistor in saturation. Figure 19 shows the voltage required at the gate of the two transistors in the cascode configuration. Consider the two-transistor configuration shown in figure 20. M1 is a diode-connected MOSFET and is hence in the active region as long as a channel is present. By proper choice of device size, we can force M2 to be in the linear region. As an example, let us see how we need to choose the device sizes if we were interested in using this configuration for biasing the cascode mirror. Referring to figure 20, we need
v1 v2
= = VT + 2
With M1 in the active region and M2 in the linear region, we have 0 0 W W v12 2 · (v2 − v1 − VT ) = 2k · · (v2 − VT ) · v1 − = Idc k · L 1 L 2 2 Substituting equations 87 and 88 in equation 89, W 1 W = L 2 3 L 1 Page 22 of 39
(87) (88)
(89)
(90)
July 8, 2007
I v2 M1 v1 M2
Figure 20: Two-transistor Configuration with Transistor in Linear Region This structure can now be used to obtain the wide-swing current mirror. The complete circuit is shown in figure 21. This circuit is called the Sooch cascode current mirror after its inventor [5]. The input voltage required for the wide-swing cascode current-mirror is VT + 2 (the higher gate voltage). Before we present a comparison, let us also look at the Wilson current mirror. 4.2.3
Wilson Current Mirror
The circuit diagram (originally shown in figure 11) is repeated in figure 22 for convenience. Since M3 is also part of the feedback loop, the feedback is inactive until M3 is turned on. Hence, the behaviour of the Wilson mirror at low voltages is considerably different from that of the cascode current mirror. Once the output voltage is greater than VT + 2, both M3 and M2 are in the active region, and the CCCS behaves as designed. The input voltage for this circuit is 2VT + 2.
5
The Translinear Principle
The basic current-mirror owes it’s popularity not just to it’s simplicity, but also to the fact that it has spawned a number of different circuits and circuit-ideas. One of these ideas is the translinear principle. Let us try to understand the translinear principle by looking at its most basic implementation, the current-mirror (shown in figure 23) A simple inspection of the circuit reveals that vbe−Q1 = vbe−Q2
Page 23 of 39
(91)
July 8, 2007
I
I va
M3
M1
vb
M5
vb M4
M2
va
M6
Figure 21: Wide-Swing Cascode Current-Mirror
Iin I0 M4
M2
M1
M3
Figure 22: The Wilson Current-Mirror
Page 24 of 39
July 8, 2007
Iin I0
Q1
Q2
Figure 23: The Basic BJT Current-Mirror/CCCS Equation 91 was arrived at by using Kirchoff’s Voltage Law (KVL) in the loop comprising of the two transistors Q1 and Q2. (Since the equation is very simple in this particular case, we were able to do it by inspection). If we now arrange n such BJTs such that the base-emitter voltages are in series, equation 91 will be modified as n X
vbe−Qi = 0
(92)
i=1
Given the exponential relationship between current and voltage for a BJT, one can safely assume that the baseemitter voltages of the various transistors are close to each other. We can then draw a couple of conclusions on the nature of the circuit. 1. There must be an even number of transistors in the loop 2. The number of transistors contributing a base-emitter voltage (to the total voltage in the loop) in the clock-wise direction will be equal to the number of transistors contributing base-emitter voltage in the counter-clockwise direction Assuming that there are 2n transistors in the loop (shown in figure 24), one can rewrite equation 92 as n n X X vbe−Qi = vbe−Qi i=1
CW
i=1
(93)
CCW
Let us analyze equation 93 in more detail. Assuming that all the devices are at the same temperature (Vt is the same for all devices),
Page 25 of 39
July 8, 2007
Figure 24: A Basic Translinear Circuit
vbe−Qi i=1 CW n X vbe−Qi ⇒ Vt i=1 CW n X ie−Qi ⇒ ln Ie0 i=1 CW n Y ie−Qi ⇒ Ie0 n X
i=1
CW
=
=
=
=
vbe−Qi i=1 CCW n X vbe−Qi Vt i=1 CCW n X ie−Qi ln Ie0 i=1 CCW n Y ie−Qi Ie0
n X
i=1
CW
i=1
(95)
(96)
(97)
CCW
Assuming that Je0 is equal for all the transistors, we can rewrite equation 97 as n n Y Y ie−Qi ie−Qi = Ae−Qi Ae−Qi i=1
(94)
(98)
CCW
In words, one can express the relationship as the product of emitter current-densities in the clockwise direction is equal to the product of emitter current-densities in the anti-clockwise direction
Page 26 of 39
July 8, 2007
I0 Ii1
Ii2 α1Ae
α2Ae
Ae
Ae
Figure 25: A Circuit for obtaining a Weighted-Sum of Two Currents
5.1
Applications of Translinear Networks
One should note that the circuit fundamentally still remains a current-controlled current-source; the main difference now is that there are multiple controlling inputs. Let us now consider some examples. We will start with a trivial case - the basic BJT current mirror of figure 23. JeS IeS AeS IeS 5.1.1
= JeM IeM = AeM AeS = IeM AeM
(99) (100) (101)
Obtaining Linear Functions
To illustrate the power and elegance of the translinear principle, let us try to obtain circuits that can generate basic linear functions such as summation, subtraction and amplification. 1. Summation Here, we are required to generate an output current that is given by the weighted-sum of several input currents. We will develop the circuit for a two-input case, and then show that extending it to multiple inputs is straightforward. Consider the circuit shown in figurefig:currentsummer. It consists of a pair of current-mirrors and the two high-impedance output nodes are shorted to each other to obtain the summing function. The ratio of emitter areas in each mirror can act as the ‘weighting-ratio’ for each current. It is easily seen that the output current of this circuit is given by I0 = α1 Ii1 + α2 Ii2 Page 27 of 39
(102)
July 8, 2007
Ii2 I0
Ii1 Ae
Ae
Ae
Ae
Figure 26: A Circuit to Obtain the Difference between Two Input Currents 0.5*G*(I00+∆Ix) 0.5*G*(I00-∆Ix) 0.5*(I00+∆Ix)
0.5*(I00-∆Ix) GAe
GAe
Ae
Ae
Figure 27: Pseudo-Differential Two-Quadrant CCCS The extension to multiple inputs is readily done by introducing as many additional current-mirrors as required. 2. Current Subtraction The second operation of interest is subtraction. The design can proceed along the same lines as the summer, as long as remember to invert the direction of current flow for the inputs that have to be subtracted. The circuit is shown in figure 26. Here again, the extension to multiple inputs is straight-forward. 3. Current Gain Let us now consider the circuit shown in figure 27. Looking closely, it consists of two basic current-mirrors. The quantity of interest here is the difference in current between the two output transistors of this pseudo-differential circuit. The output differential current is given by
Page 28 of 39
July 8, 2007 0.5*(I01+∆Iy)
0.5*(I01-∆Iy)
0.5*(I00+∆Ix)
0.5*(I00-∆Ix)
I01
I00
Figure 28: Fully-Differential Two-Quadrant CCCS
∆I0
I00 ∆Ix + 2 2 = G · ∆Ix
−G
= G
I00 ∆Ix + 2 2
(103) (104)
We will now see what happens when the pseudo-differential circuit shown in figure 27 is converted to a fullydifferential circuit as shown in figure 28. From the translinear principle, we have
I00 ∆Ix + 2 2
I01 ∆Iy I00 ∆Ix I01 ∆Iy · − = − · + 2 2 2 2 2 2
(105)
Let us now simplify equation 105 to obtain the output differential current, ∆Iy as a function of the input differential current, ∆Ix . I01 2 I01 2
+ −
∆Iy 2 ∆Iy 2
=
∆Iy I01
=
∆Iy
I00 2 I00 2
+ −
∆Ix 2 ∆Ix 2
∆Ix I 00 I01 = ∆Ix I00
(106) (107) (108)
It is clear from equation 108 that figure 28 describes a current amplifier with current gain II01 . An alternate 00 circuit that realizes the same transfer function is shown in figure 29. The circuits shown in figures 28 and 29 are called Gilbert’s Gain-Cells [6] and have found extensive use in IC design. Later in this chapter, we will look at their use in the context of multiplier design. Page 29 of 39
July 8, 2007 I00
0.5*(I01-∆Iy)
0.5*(I00+∆Ix)
0.5*(I01+∆Iy)
I01
0.5*(I00-∆Ix)
Figure 29: An Alternate Fully-Differential Two-Quadrant CCCS In the following sections, we will look at techniques to derive some complex functions such as multiplication, squaring and vector-addition. 5.1.2
Multipliers
The multiplier is a basic analog block that is used for a variety of applications such as balanced modulation, demodulation or synchronous detection, mixing, phase-detection and frequency multiplication. It is also used for generating specific non-linearities for the purpose of compensation in linear system design. The amplifier can be viewed as a special case of a multiplier where one of the variables is a control variable controlling the gain. From such a perspective, one can envision eight kinds of multipliers - there are four types of amplifiers, and in each case, the transfer parameter can be controlled by current or voltage. Let us consider the the simplest of these cases, the current multiplier. In its most general form, the output current can be expressed as
I0
= f (Ix , Iy ) = Iof f set + kx · Ix + ky · Iy + k0 · Ix · Iy + k1 · Ix2 + k2 · Iy2 + ... | {z } | {z } | {z } feed-through desired product undesired products
(109) (110)
The device or circuit configuration is chosen such that the undesired products are minimal within the dynamic range of operation of the multiplier. Any multiplier therefore needs four basic adjustments as shown in equation 111 Iof f set → 0, kx → 0, ky → 0 and k0 =
1 IR
(111)
Consider the basic multiplier circuit shown in figure 30 By inspection, we can compute the output current, I0 , to be i0 =
i1 · i2 IR
Page 30 of 39
(112)
July 8, 2007
i1 i0 Q3
Q1
Q4
Q2 IR
i2
Figure 30: A Basic Multiplier Circuit Let us now suppose that i1 and i2 are the signal currents. Given that the translinear principle (equation 98) is obeyed only when all the transistors are in the active region, what we have just designed is a single-quadrant multiplier (transistors Q1 and Q2 will be in the active region only when i1 and i2 , respectively, are positive). Our intent is to design a multiplier that can handle signals in all the four quadrants. To that end, let us see what happens (from a mathematical perspective) if we were to superpose the signal currents over a bias current such that the overall current is positive for the entire time-period of the signal current.
i0
=
=
ii · i2 I R 0 0 IR + i1 IR + i2 IR
= IR + i1 + i2 +
i1 · i2 IR
(113)
(114) (115)
If we could somehow remove the offset and the feed-through components at the output, we will be able to obtain a four-quadrant multiplier. With this in mind, let us re-visit the Gilbert’s gain-cell (shown in figures 28 and 29). To look at the possbilities that these circuits offer, consider the following example. Example 1 Compute the output current for the circuit shown in figure 29 if ∆Ix = I00 sin (ωc t) and I01 = I00 + I00 sin (ωm t) From equation 108, we have
∆Iy
(I00 + I00 sin (ωm t)) I00 sin (ωc t) I00 = I00 sin (ωc t) + I00 sin (ωm t) sin (ωc t) I00 = I00 sin (ωc t) + (cos (ωc − ωm ) t − cos (ωc + ωm ) t) 2 =
(116) (117) (118)
Equation 118 describes a 100% amplitude-modulated (AM) signal. It is clear that the circuit shown in figure 29 is capable of operating as a two-quadrant multiplier. We will now see how to convert this circuit to a four-quadrant amplifier. Looking at equation 118, we can observe that all we Page 31 of 39
July 8, 2007 I00
Im
In
Q1
Q2 Q3
Q4
0.5*(I01 + ∆Iy)
Q5
Q6
0.5*(I00 + ∆Ix)
0.5*(I00 - ∆Ix) 0.5*(I01 - ∆Iy)
Figure 31: A Four-Quadrant Multiplier need to do is eliminate the feed-through component arising due to the dc-component of I01 . In the example, if we had used I01 = I00 − I00 sin (ωm t) instead, we would have obtained an output current given by I00 (cos (ωc − ωm ) t − cos (ωc + ωm ) t) (119) 2 If we could somehow take the difference between the currents shown in equation 118 and 119, we will be able to obtain a four-quadrant multiplier. To do that, we need to feed the second input (I00 sin (ωm ) in the example), as a differential signal. The circuit is shown in figure 31 Using the same idea as was used to derive equation 118 and 119. we can compute the output differential-current, Im − In , as ∆Iy = I00 sin (ωc t) −
Im − In
= =
∆Ix I01 ∆Iy ∆Ix I01 ∆Iy · + − · − I00 2 2 I00 2 2 ∆Ix · ∆Iy I00
Let us now discuss some applications of this circuit. 1. Balanced Demodulator 0
Let us suppose that ∆Ix = Ip sin (ωc t) and ∆Iy = Ip sin (ωm t) The output current is given by
Page 32 of 39
(120) (121)
July 8, 2007
0
Ip · Ip ∆I0 = (cos (ωc − ωm ) t − cos (ωc + ωm ) t) 2I00
(122)
2. Synchoronous Demodulator 0
If ∆Ix = Ip sin (ωc ± ωm ) t and ∆Iy = Ip sin (ωc t), the output current is 0
Ip · Ip ∆I0 = (cos (ωm t) − cos (2ωc ± ωm t)) 2I00
(123)
The demodulated output is obtained by low-pass filtering this current. 3. Mixer 0
Suppose ∆Ix = Ip sin (ωRF t) and ∆Iy = Ip sin (ωLO t). The output current is given by 0
Ip · Ip ∆I0 = cos (ωRF − ωLO ) t − cos (ωRF + ωLO ) t | {z } 2I00
(124)
ωIF
A post-mixer IF-filter can be used to filter out the undesired component. 4. Phase Detector 0
If we choose ∆Ix = Ip sin (ωt) and ∆Iy = Ip sin (ωt + φ), the output current is given by 0
Ip · Ip (cosφ − cos (2ωt + φ)) ∆I0 = 2I00
(125)
The phase-detector sensitivity, Kpd , is given by
Kpd
=
∂∆I0 ∂φ
(126) 0
= − and is maximum at φ =
Ip · Ip sinφ 2I00
(127)
π 2.
Figure 31 demonstrates a 4-quadrant multiplier that takes current as both its inputs. In some applications, we might be required to obtain a 4-quadrant multiplier that can handle voltage inputs. To achieve that, we need to convert the two voltage inputs (we will call them VX and VY ) into differential currents needed to drive the Gilbert current-multiplier cell. As we will learn in chapter 4, this can be achieved by using differential transconductors. We will hold our discussion on voltage multipliers until we discuss transconductors.
Page 33 of 39
July 8, 2007
ii
i0
Q2
Q3 Q4
Q1
Ir
Figure 32: Squaring Function using the Translinear Principle 5.1.3
Squaring
Squaring functions are required in extracting the RMS value of a signal. In general, they are useful in power measurements. A simple 4-transistor circuit to realize the squaring function in shown in figure 32 Let us verify the relationship between the input and output currents using equation 98. Assuming that all the transistors are of the same size, ie−Q1 · ie−Q2 i2i i0
= ie−Q3 · ie−Q4 = Ir · i0 i2i = Ir
(128) (129) (130)
It must be noted here that the above equations are true only when the BJTs are in the active region. Hence, the circuit shown in figure 32 can only function as a squarer in the first-quadrant. Let us now attempt to realize a circuit that can function as a squarer over two quadrants. To ensure that the transistors are in the active region over the entire signal swing, we can superimpose the time-varying portion of the current over a bias-current which is equal to the maximum value of the time-varying portion. Let us suppose that we made this change to the squaring circuit shown in figure 32. It is easy to show that in addition to the quadratic term, one would also obtain a term at the output that varies linearly with the current. To avoid this problem, we can use the following identity 2
2
(1 + x) + (1 − x) = 2 1 + x2
(131)
By appropriately choosing transistor sizes and diverting the dc-component, one can obtain the squaring function over two quadrants. The circuit is shown in figure 33. In the figure, Q7 is chosen to have twice the area of the other transistors. It is left as an exercise for the reader to prove that i0 = x2 · I
Page 34 of 39
(132)
July 8, 2007
I(1+x)
I(1-x) Vcc I
Q1
Q3
Q4
Q5 i0 Q7
2I
Q2
Q6
Figure 33: A Two-Quadrant Squaring Circuit As an interesting aside, one can view squaring as a more basic operation than multiplication. For example, if we were able to somehow realize a squaring function, we could easily realize a multiplier by using the identity 2
2
(x + y) − (x − y) = 4 · x · y
(133)
Returning to squaring functions are concerned, the alternate technique to obtain two-quadrant operation is to first obtain an absolute-value function, and then use a single-quadrant squarer. Consider the circuit shown in figure 34. The idea is simple. When Ii is positive, the current should flow through the current mirror comprising of Q2 and Q3 . When Ii is negative, the current should flow through Q1 . For the former condition to be satisfied, VR must be chosen such that no current will flow through Q1 when Ii is positive. In other words, we should fix VR to be less than 2Vbe ; This ensures that transistors Q1 and Q2 are not simultaneously turned ON. Now that we have designed an absolute-value function, we can convert all single-quadrant squaring (and squaring-function related) circuits to two-quadrant circuits. We will now realize functions with single-quadrant validity for realizing the vector-sum and vector-difference of currents with the understanding that they can be easily converted to a two-quadrant system by using the absolute-value of the current (as opposed to the current itself) as the input. 5.1.4
Vector Sum and Difference
Consider the circuit shown in figure 35. Assuming that the sum of the currents through Q2 and Q3 is I0 , let us calculate the current through each of those transistors. By observing that Q1 and Q2 form a current-mirror, we can show that
IQ2
=
IQ3
=
I0 + Ii 2 I0 − Ii 2
(134) (135)
We also observe that transistor Q2 and Q3 are placed such that their base-emitter voltages add. In other words, from a translinear-principle point of view, the product of the common-mode and differential-mode currents is readily Page 35 of 39
July 8, 2007
I0
VR
Q3 Ii
Q1
Q2
Figure 34: A Circuit for Realizing the Absolute-Value Function
I0
Q3 I1
Q1
Q2
Figure 35: A Circuit to Realize Common-Mode and Differential-Mode Currents
Page 36 of 39
July 8, 2007
I0
Ii2
Q4
Q3 Ii1
Q5
Q1
Q2
Figure 36: A Circuit to Realize the Vector Summation of Two Currents available. We can use this to obtain a vector-summation circuit as shown in figure 36. For proper scaling, Q4 and Q5 should be one-half the area of the other devices. The vector-difference can be easily obtained by inverting the roles of Ii2 and I0 and is left as an exercise to the reader.
5.2
Translinear Principle in MOSFETS
Consider a loop containing 2n MOSFETs in the current-saturation region such that n MOSFETs contribute a gatesource voltage in the clockwise direction and n MOSFETs contribute a gate-source voltage in the counter-clockwise direction. Assuming that the threshold voltages (VT ) of the transistors are the same, we can express the translinear principle for the MOSFETs as n X
s
i=1
⇒
n X i=1
Ii k· W L i s
Ii W L
= CW
=
i CW
Ij W k · L j j=1 CCW s n X Ij W L j j=1 n X
s
CCW
As an application of this principle, consider the circuit shown in figure 37 [7]. Using equation 137 and assuming equal sizes for all the devices, we have Page 37 of 39
(136)
(137)
July 8, 2007
IB
I0
M5
M3
Ii
M4
M2
M1
Figure 37: A CMOS-based Squaring Circuit
r I0 + Ii I0 − Ii + = 2 2 q = I0 + I02 − Ii2 q = I02 − Ii2 r
p 2 IB 4IB 4IB − I0 2 16IB
I02
=
⇒ I0
=
− 8IB I0 +
I02
Ii2
− 2 16IB + Ii2 8IB
(138) (139) (140) (141) (142)
, a squaring function !! The associated dc-offset can be easily removed. A four-quadrant multiplier is now easily realized using the identity shown in equation 133. Interested readers are referred to [8] for a practical implementation of the multiplier. It must also be mentioned here that the entire discussion on the translinear principle for BJTs is valid for MOSFETs operating in the subthreshold region. With this thought, we will conclude our discussion on the translinear principle. In the following chapter, we will consider the realization of voltage-controlled sources.
References [1] Paul R. Gray, Paul J. Hurst, Stephen H. Lewis, Robert G. Meyer, “Analysis and Design of Analog Integrated Circuits”, Fourth Edition, John Wiley, 2001 [2] Behzad Razavi, “Design of Analog CMOS Integrated Circuits”, Tata McGraw Hill, 2002 [3] Yannis P. Tsividis, “Operation and Modeling of the MOS Transistor”, McGraw-Hill, 1988.
Page 38 of 39
July 8, 2007 [4] G. R. Wilson, “A Monolithic Junction FET - npn Operational Amplifier”, IEEE Journal of Solid-State Circuits, Vol. SC-3, pp. 341-8, December 1968. [5] N. S. Sooch, “MOS Cascode Current Mirror”, U. S. Patent 4,550,284, October 1985. [6] B. Gilbert, “A Four-Quadrant Analog Divider/Multiplier with 0.01% Distortion”, Digest of Technical Papers, International Solid-State Circuits Conference, pp. 248-9, 1983. [7] B. D. Liu, C. Y. Huang and H. Y. Wu, “Modular Current-Mode Defuzzification Circuit for Fuzzy Logic Controllers”, Electronics Letters, vol. 30, no. 16, pp. 1287-8, August 1994 [8] K. Tanno, O. Ishizuka and Z. Tang “Four-Quadrant CMOS Current-Mode Multiplier Independent of Device Parameters”, IEEE Transactions on Circuits and System - II: Analog and Digital Signal Processing, vol. 47, no. 5, May 2000
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