Proceedings of the Argentine School of Micro-Nanoelectronics, Technology and Applications 2009

ADC Post-Compensation Using a Hammerstein Model C. Schmidt, J. E. Cousseau and J. L. Figueroa

R. Wichman and S. Werner

Instituto de Investigaciones en Ingeniería Eléctrica Alfredo Desages UNS CONICET, Avda. Alem 1253, 8000 Bahía Blanca, Argentina Email: [email protected]

Signal Processing Laboratory Helsinki University of Technology P.O. Box 3000. FIN-02015 HUT, FINLAND

briefly described in Section IV. Next, in Section V, the parameter estimation problem is discussed and analyzed. Finally, simulation results are analyzed in Section VI. This article ends in Section VII with some conclusions.

Abstract— In this work, a scheme for the calibration of an ADC model is presented, as well as the process of identification of the compensation block. The model proposed for this compensation block is a Hammerstein box model whose parameters are estimated in a non iterative fashion. A Hammerstein model is composed of a static nonlinearity followed by a linear time invariant (LTI) filter. This model is then to be added at the output of the ADC to obtain the corrected value of the ADC output word. A performance analysis is carried out in terms of the mean squared error (MSE) to determine both the length of the linear part of the Hammerstein model and the order needed for the polynomial nonlinearity used. Also, the Bit Error Rate (BER) is calculated before and after compensation to measure the improvement achieved.

II. BASIC CONCEPTS ON LUT S Post-compensation by look-up tables (LUTs) is one of the most frequently proposed methods for error correction in ADCs [9]. The basic idea behind a LUT correction system is to use the output samples of the converter to generate a memory address (or index). This address gives access to a particular table entry where a correction value (that adds to, or replaces the output sample) has previously been saved (Fig.1).

I. I NTRODUCTION Hammerstein models have been studied for many years in the field of nonlinear systems identification and compensation [7], [11]. This type of system can be seen as a subclass of the more general Volterra model [7], with the particular characteristic of having fewer parameters that can be manipulated so that they appear linearly in the equations [3]. The price for this huge advantage is that fewer physical processes can be represented by Hammerstein systems than those who allow for a general Volterra representation. However, for systems that can be well described by a Hammerstein model, this ease of parameterization leads to more simple estimation algorithms and robustness of the results obtained [3], [7], [10]. Recently, the need for high speed and high resolution analog to digital converters (ADCs) has atracted much attention towards ADC calibration and testing [9], [10]. Several techniques have been studied for the calibration of high speed ADCs and cancellation of their nonlinear effects [5], [9], but not many use Hammerstein approaches for the modelling issue [10]. In this work, a scheme for the calibration of an ADC model is presented, as well as the process of identification of the compensation block. The model proposed for this compensation block is a Hammerstein box model whose parameters are estimated in a non iterative fashion, as proposed in [3]. In the following section, some useful concepts on LUTs are briefly reviewed. In Section III, the proposed compensation scheme is introduced. Volterra and Hammerstein models are

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Fig. 1.

General scheme of a look-up table correction system.

In this manner, the LUT models the error between the ADC under test and an ideal ADC. The elements that compose the look-up table correction system can be divided in: • Indexing scheme: determines in which manner the index I is generated from the ADC output samples. • Correction or replacement: the table can be used either to save the correction values to be added to the output sample, or to save values that directly replace the output sample from the converter (Fig. 2). • Reference signal: There are different ways to obtain a reference signal. It is used to calibrate the table and therefore its selection is very relevant. • Estimation methods: Strategies on how to obtain the correction values with which the table will be filled from the reference signal.

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Indexing schemes: they represent the key part of a LUT system, as they determine the size and structure of the table that will be implemented. The difference between them is basically how they do the mapping of the ADC samples into the corresponding memory address. Some examples are: Static index: the index I is directly the n bit digital word corresponding to the present sample provided by the converter. It does not depend on the values from past samples. As an advantage, it requires the minimum amount of memory. However, this scheme does not take into account the dynamics of the sampled signal, and it has been proven that it can enhance the performance of the converter at some frequencies while deteriorating it at others. State-space indexing: one way to introduce information about the dynamics of the input signal consists of using both the present and previous sample to generate the address index I. Basically, if the converter provides an n bit digital word, the present and previous samples are combined and an index of length equal to 2n bits is obtained. The motivation for the use of this type of indexing is that depending on the dynamics of the system, the ADC may produce different errors for the same output word. Hence, in this manner, the dynamics of the input signal is taken into account during the correction process. This method can be generalized using k past samples along with the present sample to generate the index I, but the memory required to save the table grows exponentially as a function of k. In addition, the amount of memory also grows exponentially as a function of the number of bits in the ADC. Phase-plane indexing: In this case, the address index for the table is generated from a combination of the present sample and an estimate of the slope of the input signal. The estimation of the slope can be obtained as the difference between the present sample and the previous one, using a FIR filter as a derivator, or using an analog derivator sampled by another ADC. This method can also be generalized to use the first k derivatives of the input signal. Another disadvantage of this method is that a very intensive experimental work is needed to detect the value of the errors with which the table will be filled.

Wiener or Volterra models. The parameter estimation can be performed in a non-iterative manner [3] with a small set of input-output measurements. Any other possible measurements will be predicted by the resulting model. Two ADC models developed by the authors in a previous article [1] will be used to test the compensation scheme. The first model is a circuital model of a 4 bit flash ADC and the second is the circuital model of a 7 bit pipelined ADC based on the first model. These models offer a good representation of the static and dynamic nonlinearities of a real ADC [5, 12]. The compensation process can be divided into three stages. The first stage is the calculation of the error committed by the converter compared to an ideal ADC (Fig. 2) for some sets of input-output data, and its storage in memory. The indexing scheme for this data set will be of statespace type with a memory of k past samples, according to the memory effect observed in the circuital ADC model used [1]. However, only some random values will be used, and the rest of the values will be predicted by the Hammerstein model. Thus, a small data set can be used to estimate the parameters of a Hammerstein model that will be predict any other combination of input-output samples.

Fig. 2.

Then, the parameters of the Hammerstein system (described in Section IV) are estimated by least squares using overparameterization as will be discussed later in Section V, such that the model obtained emulates the error behavior using output data from the ADC model (presented in section VI). Finally, the Hammerstein system (G) is added to the output of the ADC and the compensation is performed (Figure 3).

III. P OST- CORRECTION USING A H AMMERSTEIN MODEL In order to solve the disadvantages of LUTs, such as the huge amount of memory required to store the correction values and the very intensive experimental work needed to measure them, a compensation using a Hammerstein model is proposed in this article. A LUT can be seen as a large set of measurements of the errors produced by the ADC compared with an ideal converter. This error is closely related to the nonlinear effects present in the device, which are known to be mainly of third and fifth order [5, 12]. Thus, this knowledge can be exploited to develope a model for the error with the capability of accurately predict the real error. A nonlinear Hammerstein model is proposed for this purpose. This type of model has as advantage the ease of implementation and parameter estimation compared to the more general

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Error identification process.

Fig. 3.

Compensation.

IV. VOLTERRA MODELS The output of a discrete time Volterra model (DTVM) at instant k can be expressed as [7]:

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yk = Φ(yk−1 , · · · , yk−p , uk−1 , · · · , uk−q )

(1)

where the choice of the function Φ and the parameters p and q define the model. In particular, if one analyzes only the NFIR systems (i.e. for p = 0) and focuses on the family of analytic continuous functions Φ (which can be expanded into Taylor series), it is possible to define DTVMs analogous to the continuous time Volterra models. In such a case, the integrals are replaced by discrete convolution sums and the system response becomes: y(k) = y1 (k) + y2 (k) + y3 (k) + · · ·

Fig. 4.

where v(k) = α1 .u(k) + α2 .u2 (k) + · · · + αN .uN (k)

(2)

∞ X

h1 (i).u(k − i)

(3) V. T HE PARAMETER ESTIMATION PROBLEM

i=0

corresponds with the linear convolution model, and the terms of higher order can be written as y2 (k) =

∞ ∞ X X

h2 (i, j).u(k − i).u(k − j)

Once the model structure has been chosen, the problem of parameter estimation arises. The values of the model parameters must be estimated in such a way that a given error criterion is minimized. Several known techniques for this purpose are available, as discussed for example in [6], [7], [8], [11]. The main two approaches found in the literature for the estimation of the parameters of a Hammerstein system are discussed below.

(4)

i=0 j=0

y3 (k) =

∞ X ∞ ∞ X X

(9)

It is easy to show that this type of system is a special case of the finite DTVM class, but with fewer parameters. Indeed, it allows for simpler signal processing and more efficient algorithms for parameter estimation.

where the first term, given by y1 (k) =

Block diagram of a Hammerstein model.

h3 (i, j, l).u(k − i).u(k − j).u(k − l) (5)

i=0 j=0 l=0

A. Traditional approach

and so on. An important result is that discrete time systems with fading memory can be approximated arbitrarily well by DTVMs if an adequate truncation is performed. Furthermore, if we consider that any nonlinear function can be approximated by a polynomial of sufficiently high order, this leads to finite DTVMs, which are the simplest among all Volterra models. Finite DTVMs are composed of a moving average linear model of order M and a polynomial nonlinearity of degree N. For the SISO case, the input-output relationship of such systems is given by y(k) = y0 +

N X

n vM (k)

The block diagram of a Hammerstein system shown in Figure 5 can be redrawn in a more detailed manner as it can be seen in Figure 5.

(6)

n=1

Where Fig. 5. n vM (k) =

M X i1 =0

···

M X

αn (i1 , · · · , in ).u(k − i1 ). · · · u(k − in )

Detailed block diagram of a Hammerstein model.

It is clear that this block diagram represents accurately the mathematical expression in Equation 8, which can be written in matrix form as

in =0

(7) A. The Hammerstein case Hammerstein models are composed of a static nonlinearity followed by a linear time invariant (LTI) system (Figure 4). If the nonlinearity can be approximated by a polynomial of order N and the LTI system by a FIR filter of length M, the input-output relationship is described by y(k) =

M X

v(k − m).h(m)

(10)

[h] = [h(0), h(1), · · · , h(M )]T

(11)

Where

(8)

[v] = [v(k), v(k − 1), · · · , v(k − M )]T = [u].[α]

m=1

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y(k) = [v]T .[h]

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(12)

Proceedings of the Argentine School of Micro-Nanoelectronics, Technology and Applications 2009

   [u] =  

u(k) u(k − 1) .. .

u2 (k) 2 u (k − 1) .. .

uN (k) N u (k − 1) .. .

··· ··· .. .

u(k − M ) u2 (k − M ) · · · uN (k − M )



[θ]T = [α1 .h(M ), · · · , α1 .h(1), α2 .h(M ), · · · , αN .h(1)] (21) Then, the model parameters can be estimated by least squares in one step, and the solution obtained is

    (13)

T

[α] = [α1 , α2 , · · · , αN ]

0 θˆ = [U T .U ]−1 .U T .Y

(14)

VI. S IMULATIONS AND RESULTS The ADC models for simulation described in [1] were used in order to analyze and test the proposed ADC compensation scheme. The first model is the circuital model of a 4 bit flash ADC. The input-output data from this converter are obtained by circuital simulations in Spice. Based on this model, it is also obtained the circuital model of a 7 bit two stage pipelined ADC [1, 4]. An ideal ADC was simulated in MATLAB to allow for comparison of both models with an ideal converter and estimate the resulting error for each of them. First, the amplitude quantization of a sinusoidal signal was simulated using the circuital and ideal ADC models. Then, the time quantization of the signals was performed using a clock determining a sampling frequency 5 times higher than the frequency of the signal. In this manner, a data set of 1650 input-output values was for each of the three mentioned ADC models. Next, given the same input signal, an error vector was calculated as the difference in the output data between the ideal and the circuital models (Fig. 8). This error signal was then saved in a table for later usage. This error vector represents the desired output needed to estimate the parameters of the Hammerstein system, and once it has been obtained, the first phase of the compensation process finishes as described in the previous section. This process was repeated for the circuital model of a 7 bit pipelined ADC, with an effective sampling frequency 20 times higher than the frequency of the input signal. From these data series, two third parts were used for the parameter estimation of the Hammerstein system G, and the rest for validation. For the training phase, a data series of present and past output samples from the circuital models were used as the input to the Hammerstein system and the error vector was used as the desired output. There are basically two main structural characteristics in a finite Hammerstein model to be determined: the length of the LTI FIR filter (M) and the order of the polynomial nonlinearity (N). Thus, these two values have to be estimated before the filter or the polynomial coefficients. In order to do so, the selected criterion was the Mean Square Error (MSE).

This leads to a double estimation problem that can be solved iteratively by least squares as follows [7]: • An initial guess is chosen for the filter coefficients h(i). • The polynomial coefficients αi are then estimated by least squares. • With this estimated polynomial coefficients, h(i) are estimated by least squares. • Go to step two until convergence is reached. This algorithm is due to Narendra et al (1966), and has the mayor drawback of its iterative nature, which makes it useful only for the case of batch estimation. In addition, convergence of the algorithm can not be guaranteed (Soteica, 1982). B. Over-parameterization In the general case, when L input-output measurements from the actual system are available, the model can be expressed in matrix form as [3]: [Y ] = [V ].[h]

(15)

[Y ]T = [y(k), y(k − 1), · · · , y(k − L + M )]

(16)

where



 v(k − 1) · · · v(k − M )  v(k − 2) · · · v(k − M − 1)    [V ] =   .. .. ..   . . . v(k − L + M ) ··· ··· v(k − L) (17) Each element in (17) corresponds with Equation 9. Thus, rearranging the input data vector in matrix form and taking the exponentials, an over-parameterized problem can be formulated as follows: v(k) v(k − 1) .. .

0

[Y ] = [U ].[θ] = [U1 , U2 , · · · , UN ].[θ]

(22)

(18)

where

A. Circuital model 1 - 4 bit flash ADC 0

T

[Y ] = [y(M ), y(M + 1), · · · , y(L)]    [Un ] =  

un (1) un (2) .. .

··· un (M ) n · · · u (M + 1) .. .. . .

un (L − M ) · · ·

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un (L)

First, a series of Hammerstein systems with different lengths for the FIR filter were identified, all for a polynomial nonlinearity of order 5. Then, the MSE in approximation and validation were calculated for each case. The results are plotted in Fig. 6. As it can be seen in Figure 14, the MSE in validation does not decrease significantly for a FIR filter longer than 25. As

(19)     

(20)

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Proceedings of the Argentine School of Micro-Nanoelectronics, Technology and Applications 2009

Fig. 6. Validation (red) and approximation (blue) MSE vs. FIR length for a polynomial nonlinearity of order 5.

Fig. 8. Error signal from de ADC (top) and prediction from the Hammerstein system (bottom) for a 25 tap FIR and a polynomial of order 5.

expected, the MSE in approximation continues to drop as the length of the FIR filter increases, which means that an overadjustment occur. Therefore, we conclude that the length of the system dynamics is about 25 past samples. This result is in agreement with the one obtained for a compensation of the same models using a Neural Network [2]. Next, the length of the FIR filter was fixed to 25 samples, and a series of Hammerstein systems were identified for different orders of the polynomial nonlinearity. Again, the MSE in approximation and validation were computed, and plotted in Figure 7 as a function of N. Fig. 9. Normalized error signal from the system without compensation (top) and from the compensated system (bottom).

compensation is shown. From this figure it can be seen that the error for the compensated ADC will be much smaller, as only a difference of more that ±0.5 LSB will produce an erroneous output word in the converter. Finally, the BER of the system before and after compensation was computed. Before compensation, the system shows a BER = 0.0326 whereas the compensated system exhibits a BER = 0.002. As a conclusion, an improvement of an order of magnitude was obtained. Fig. 7. Validation (red) and approximation (blue) MSE vs. degree of the polynomial nonlinearity for a FIR of length 25.

B. Circuital model 2 - 7 bit pipelined ADC In the same manner as in the previous case, several Hammerstein models were simulated. Then, the MSE in approximation and validation was computed as a function of the order of the polynomial used for a memory length of 10 samples. The plot is shown in Fig. 10. As can be seen from the figure, in this case the order needed in the polynomial is also 5, as no reduction in the MSE is obtained for larger orders. Again, the process of simulation was repeated for several Hammerstein systems with a polynomial of order 5, but varying the length of the FIR to model the memory of the system. It can be seen that the MMSE in validation is obtained for a FIR of length equal to 10 samples, as shown in Fig. 11.

It is clear from Figure 7 that the MSE in validation decreases as higher order components are incorporated, untill the MMSE is reached for a polynomial of order 5. Thus, we conclude that N = 5 is sufficient to capture the main nonlinear behavior of the system. This is in agreement with the results found in the literature [12], where a fifth order model is derived for the nonlinearities due to sampling time uncertainty. Again, an over-adjustment makes the MSE in approximation to be reduced further. In Figure 8, the error signal and the error predicted by the Hammerstein model are shown. It is clear that the prediction obtained is good. In Figure 9, the error in the ADC output with and without

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Fig. 10. Validation (red) and approximation (blue) MSE vs. FIR length for a polynomial nonlinearity of order 5.

Fig. 12. Error signal from de ADC (top) and prediction from the Hammerstein system (bottom) for a 10 tap FIR and a polynomial of order 5.

Fig. 11. Validation (red) and approximation (blue) MSE vs. degree of the polynomial nonlinearity for a FIR of length 10.

Fig. 13. Normalized error signal from the system without compensation (top) and from the compensated system (bottom).

R EFERENCES

Fig. 12. shows the real error committed by the pipelined ADC and the prediction given by the Hammerstein model, both obtained for a data set different from the one used to estimate the parameters of the Hammerstein model. In this case, the structural parameters of the model are those for which the MMSE is obtained, i.e. a polynomial of order 5 and a FIR of length 10 to represent the memory of the system. Finally, in Fig. 13 the error signal from the 7 bit two stages pipelined ADC is shown, before and after compensation.

[1] C. Schmidt, J.E. Cousseau and J.L. Figueroa, "Analog to digital converter characterization", sent to XIII RPIC, Rosario, Argentina, 2009. [2] C. Schmidt, J.E. Cousseau, O. Agamennoni and J.L. Figueroa, "ADC compensation based on Neural Networks", sent to XIII RPIC, Rosario, Argentina, 2009. [3] J. C. Gómez, E. Baeyens, "Identification of block-oriented nonlinear systems using orthonormal bases", Journal of Process Control, ELSEVIER, Vol. 14, No. 6, pp. 685-697, 2004. [4] C. Hammerschmied, "Pipelined A/D Converters for Telecommunication Applications", Workshop on A/D Converters for Telecommunication, Integrated Systems Laboratory, ETH Zürich, October 2001. [5] R. Van de Plassche, CMOS Integrated Analog-to-Digital and Digital-toAnalog Converters, Kluwer Academic Publishers, 2003. [6] O. Nelles, Nonlinear System Identification: From Classical Approaches to Neural Networks and Fuzzy Models, Springer - Verlag, 2001. [7] F. J. Doyle III and R. K. Pearson, Identification and Control Using Volterra Models, Springer, 2002. [8] S. Haykin, Adaptive Filter Theory, Prentice Hall. [9] H. F. Lundin, Characterization and Correction of Analog-to-Digital Converters, Doctoral Thesis in Signal Processing, Stockholm, Sweden 2005. [10] N. Björsell, Modeling Analog to Digital Converters at Radio Frequency, Doctoral Thesis in Telecommunications, Stockholm, Sweden 2007. [11] Anna Hagenblad, Aspects of the Identification of Wiener Models, Linköping Studies in Science and Technology, Thesis No 793, Sweden, 1999. [12] J. Tsimbinos, Identification and Compensation of Nonlinear Distorsion, PhD thesis, University of South Australia, 1995.

VII. C ONCLUSIONS In this work, ADC compensation techniques are described and the results obtained for a compensation based on modelling the error of the ADC by a Hammerstein system, both for the case of a 4 bit flash ADC and a 7 bit two stage pipelined ADC. These models are extracted from previous work of the authors. It is shown that this compensation scheme leads to good results in the prediction and cancellation of errors with a relatively low computational cost. In addition, the optimal parameters for the Hammerstein model used can be uniquely determined for each model, leading to the smallest error possible.

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