All-OPTICAL PACKET-SWITCHED ROUTING BASED ON PULSE-POSITION-MODULATED HEADER M. F. Chiang, Z. Ghassemlooy, Senior Member, IEEE, H. Le Minh, Student Member, IEEE, and Wai Pang Ng, Member, IEEE, Optical Communications Research Group, School of Computing, Engineering and Information Sciences Northumbria University, Newcastle upon Tyne, NE1 8ST, UK Email: [email protected], [email protected], h.le-minh, [email protected]@unn.ac.uk ABSTRACT The paper presents a node architecture for an all-optical packet router where packet header address and the routing table formats are based on the pulse position modulation (PPM). Correlation of a packet header with the PPM based routing table (PPRT) entries is carried out using only a single bit-wise AND gate, thus resulting in reduced processing time and system complexity. It is also shown that the proposed scheme offer unicast/multicast/broadcast transmitting capabilities. We show that the correlated packet header address power and the switched signal on-off contrast ratio largely depends on the switching window width and the timing offset of the PPM header address. KEY WORDS Packet switching, pulse position modulation, address correlation, pulse-position routing table, optical switch

1. Introduction All-optical packet routing is being proposed as an alternative to the existing low-speed packet routing schemes where header processing is implemented in the electrical domain [1, 2]. By replacing the slow optical/electrical/optical (O/E/O) conversions and carrying out header processing in all-optical domain a higher data throughput and lower power consumption can be achieved. At present, nearly all optical header recognition and processing schemes are based packet header address correlation requiring a large scale routing table (> 5×105 entries) [3, 4]. For a small size network (i.e. reduced size routing table) header processing could be implemented using a bank of all-optical mirror-based correlators [5] and all-optical logic gates (OR, XOR, AND) [6]. However, for a larger size network, the correlation task becomes a challenging issue due to the exponential increase in the number of routing table entries. In addition, all-optical logic gates employing an active nonlinear device such as semiconductor optical amplifier (SOA) [7-10] suffer from a long recovery time (~ 1 ns) after each correlation, thus limiting the operational speed to 80 Gbit/s. Therefore to carry out a large number of correlation at high data rates in optical domain with a minimum processing time, one needs to

utilize either a significant number of parallel gates or a small number of gates for sequential correlation However, these solutions are not feasible in the current practical systems. An alternative header processing method based on pulseposition-modulation header processing (PPM-HP) has been proposed in [11, 12], where the incoming packetheader bits and the routing table entries are both converted into a PPM format before being correlated with each other. The advantages of this scheme are (i) significantly reduced routing table entries, where each entry contains more than one header address information in the form of a PPM pulse, (ii) considerably reduced correlation processing time by using only a single bitwise AND gate instead of a large number of gates with a low response-time, and (iii) offering multiple transmitting modes (unicast, multi-cast and broadcast) embedded in optical layer. However, PPM-HP will require a serial to parallel converter (SPC) to extract individual bits from the incoming packet header, an array of 1×2 switches and delay lines [11]. For packets with a long header bit pattern, there will be increased switching stages, which will result in deterioration of the extinction ratio of the output PPM header and increased complexity [13]. In this paper, we propose a less complex PPM-HP based router no longer employing the SPC and an array of 1×2 switches. The paper is organized as follows: after the introduction, the proposed PPM-header and PPM-HP based router are presented in section 2. In addition the

…

#6(0110)

#4(0010)

…

… B A

o/p1

…

D

o/p2

o/p3

#7(0111)

#9(1001)

o/p2

C

…

#14(1110)

#13(1101)

#5(0101)

electrical low-speed data packet

optical packet

edge node

core node

Figure 1 An optical core network with 16 edge nodes

Payload

PPMH CLK

τtot

Optical Switch

(1-2α)P(t + τtot)

Pin(t)

) τCEM

Pout, M(t)

αP(t + τCEM)

PPM Header Address

Pout, 1(t) Pout, 2(t)

PPM-HEM

XPPM(t) OSC

αc(t) αP(t)

Tb

CEM

c(t)

E1(t)

τPPRT

0

1

2

3

4

5

6

7

8

9

10 11 12 13 14 15

e(t)

E2(t) PPRT

EM(t)

m1(t) &1

m2(t) &2

mM(t) &M

Figure 2 An optical packet with a PPM based header structure

calculation of multiple-hop OSNR is also presented in this section. Section 3 shows the performance analysis of OSNR and PPM-header timing-offset tolerance of this system. The simulation results and discussions are also presented in this section. Finally, section 4 will conclude the paper.

Figure 3 The architecture of the PPM header processing based router

Table I (a) Conventional routing table with 2N-entries, and (b) its corresponding PPRT with M entries

2. All-optical Router 2.1 All-optical PPM-HP router An all-optical network is composed of K edge nodes and L core nodes, see Fig. 1, with K = 16 edge nodes. Each edge node has its own specific address. Incoming lowspeed electrical packets at a source edge node with the same destination (i.e. the same target edge node) are combined and converted into a high speed optical packet. Optical packets are then routed to the destination via the core-network. When a packet arrives at PPM-HP based router (i.e. a core node), its header is processed and correlated with the entries of the local PPRT in order to switch the packet to the correct output port. Depending on the network configuration and the local PPRTs, packet will go through a number of core routers before reaching its targeted edge node. In Fig. 1, an illustration of a fourhop routing path is presented. A typical packet is composed of the clock, address header and payload bits, see Fig. 2. The clock information is used for synchronization within the router. The header address is in PPM frame format composed of 2N time slots and a short duration pulse. The position of the pulse corresponds to the target address decimal metric. For example, a target address of “0111” with a decimal value of 7 is represented in PPM as a “0000000100000000”, see Fig. 2. Figure 3 illustrate architecture of the 1×M PPM-HP router composed of a clock extraction module (CEM), a PPM header extraction module (PPM-HEM), a PPRT, AND gates, a number of fibre delay lines (FDLs), all-optical switches (OS), and an OS control module (OSC). The incoming optical packet Pin(t) is split and applied to the CEM, PPM-HEM and OS with the delays of 0, τCEM

(a)

(b)

(required time for the clock extraction) and τtot (total required time for PPM address correlation), respectively. CEM is based on two cascading SMZ switches as in [11] offering reduced residual crosstalk. The extracted clock c(t) is applied to the PPM-HEM (based on a single SMZ switch configuration) and PPRT modules with the delays of 0 and τPPRT, i.e. αc(t) and e(t), respectively, where α is the splitting factor. The recovered PPM header (2N-bit frame) at the output of the PPM-HEM is applied to a bank of AND gates. Table I illustrates both a conventional routing table (CRT) and the proposed PPRT with 2N and M entries, respectively. In the CRT each header address is assigned a particular output port, whereas in PPRT a group of header address j is converted into a PPM format, and assigned the same output. Each PPM frame is composed of j pulses of one slot duration with location determined by the decimal metrics of each address, see. Fig. 4. Note that shown in Table I(b) is the PPRT for node A. Similarly, for nodes B, C, and D, the PPRT entries would be E2 ∈ {2, 6, 7, 13, 14}, E2 ∈ {2, 7, 8, 12, 15}, and E3 ∈ {0, 4, 5, 7, 9, 13}, respectively. A PPRT is generated by applying the clock signal e(t) through a number of optical switches and delay lines as outlined in Fig. 5(b), and is given as:

PPM Header Address

0

1

2

3

4

5

6

7

8

9

Packet destination address identification is carried out by correlating the extracted PPM-header address with the PPRT entries using an array of SMZ based optical AND gates [14], see Fig. 4. Since a single bit-wise AND operation is required for each correlation, then the SOA gain recovery time of the AND-gate is no longer an issue regardless of the sizes of the packet header and the routing table. The correlated signal at the output of the kth AND gate can be expressed as:

10 11 12 13 14 15

PPM Routing Table in Node A

E1 0

1

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9

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E2

⎧1 if mk (t ) = X PPM (t ) × E k (t ) = ⎨ ⎩0 if k = 1,2,..., M d k ∈ Dk

E3

(2)

Figure 4 Correlation between PPM-header and PPRT entries

E k (t ) = ∑ e(t + d k × Ts ),

∀ d k ∈ Dk , k ≤ M

d k = pos( X PPM (t )) ∀k , d k ≠ pos( X PPM (t )) ∀k

Where XPPM(t) is the PPM header frame and pos(XPPM(t)) is the pulse position within XPPM(t).

(1)

Any timing offset between XPPM(t) and Ek will affect the intensity of mk(t), as will be investigated in Section 3.2. If more than one pulse is located at the same position in more than one PPRT entries, then the packet is classified

dk

th

where Ts is the PPM time slot, Dk is the k set containing all decimal values of the header address assigned to the kth output node (where k =1,2,…, M).

(a)

(b) Figure 5 The VPI simulation setups for (a) four-hop routing and (b) a router (node) architecture

as the multicasted or broadcasted (same position in all entries) to multiple outputs or all outputs, respectively. mk(t) is subsequently applied to the OSC module to generate a number of control pulses for controlling the switching window of the optical switch to allow complete packet switching with a minimal gain fluctuation. The router output signal is therefore described as follows: Pout ,k (t ) = Pin (t ) × mk (t ) =

⎧GOS × (1 − 2α ) × Pin (t + τ tot ) if mk (t ) = 1 ⎪ =⎨ ⎪⎩ 0 if mk (t ) = 0

Pase,i = 2n sp ,i hf 0 (G OS,i − 1)B0

i = 0,1,...H

where nsp,i and Gi are the spontaneous-emission factor and the gain, respectively, of the amplifier, where i = 0 represents the pre-amplifier and i > 0 denotes the SOA in OS modules. hf0 and B0 are the product of the Planck constant and the operating optical frequency, and the optical bandwidth of the system (i.e. filter optical bandwidth), respectively. For packets passing through a number of core nodes H, the optical signal to noise ratio (OSNR) is given as [11]:

k = 1,2,..., M (3) where GOS is the gain of the optical switch. 2.2 Multiple-hop OSNR The SOA unpolarized amplified spontaneous emission (ASE) noise is generally computed by [15]:

H −1 ⎛ ⎞ ⎜⎜ G H ∏ (Gh Lh )⎟⎟ Pin h =0 ⎠ OSNRH = H −1 ⎝ H ⎛ ⎞ ∑ ⎜⎜ Pase,h ∏ (Gk Lk −1 )⎟⎟ + Pase, H h =0 ⎝ k = h +1 ⎠

(5)

where Lh is the total loss incurred between any two core nodes.

‘0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 ’ C LK

(4)

P PM h eader

P aylo ad

(a)

(b)

(c)

(d)

(e)

(f)

(g)

(h)

(i)

Figure 6 Time waveforms; (a) input packet packets at node A, (b) extracted clock at node A, (c) extracted clock at node B, (d) extracted clock at node C, (e) extracted clock at node D, (f) switched packets at node A – output1, (g) switched packets at node B – output2, (h) switched packets at node C – output2, and (i) switched packets at node D – output3

35

3. Results and Discussions

33 31

The time waveforms of sixteen input packets and their switched versions at the outputs of four nodes (A, B, C and D) are illustrated in Fig. 6. Figure 6(a) shows the input packets with the inset illustrating the zoomed-in packet PPM header with an address decimal metric of #7. The extracted clock pulses observed at nodes A, B, C and D are presented in Figs. 6(b)-(e), respectively, showing small intensity variations. At each hop, input packets are switched to their corresponding output ports depending on node’s PPRT. Packets with target address of #7 are subsequently switched to the outputs 1, 2, 2 and 3 of nodes A, B, C and D, respectively, Figs. 6(f), (g), (h) and (i). The intensity overshot observed at the start of switched packets is due to the gain saturation of the SOA in OS when injected with a number of input packets,

OSNR (dB)

Theoretical

27 25 23 21 19 17 15 0

1

2

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4

The number of hops

(a) 80 70 Matched pulse power (mW)

3.2 Results and Discussions

Simulation

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Ts w =0.25Tb Ts w =0.5Tb

40

Ts w =0.75Tb Ts w =Tb

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Desired output packet power (mW)

3.1 Simulation Setup The proposed router is simulated and its performance is investigated by using the Virtual Photonics simulation package (VPITM). Table II shows the main simulation parameters adopted. The schematic diagram of the simulation setup for multi-hop routing and an individual router are shown in Fig. 5(a) and (b), respectively. In Fig. 5(a), sixteen optical packets are transmitted at 160 Gb/s with 1 ns packet guard time, where each packet contains one clock bit, sixteen bits PPM-header and 53 bytes payload (equal to the size of an ATM cell) [16]. Optical pulses within a packet with an average power of 1 mW are amplified before transmission to compensate for the link losses (fibre attenuation and coupling loss). Each fibre span (link) comprises of 30 km of single-mode fibre (SMF) and 5 km of dispersion-compensating fibre (DCF). The VPI equivalent of Fig. 3 is depicted in Fig. 5(b).

10

8

6

4

2

Table II Simulation Parameters Parameter and description

Value

Data packet bit rate – 1/Tb

160 Gb/s

Packet payload length Wavelength of data packet Data & control pulse widths – FWHM

53 bytes (424 bits) 1554 nm 2 ps

PPM slot duration Ts ( =Tb )

6.25 ps

Average transmitted power Pin

1 mW

Average power of Ck(t) Optical bandwidth Bo

75 mW 300 GHz

Gh (h = 1,2,…H)

20 dB

Total loss of a hop 1/Lh (h = 1,2,…H)

-7 dB

Pre-amplifier gain G0

7 dB

First span loss 1/L0

-7 dB

Pre-amplifier nsp SOA length SOA nsp Inject current to SOA Splitting factor α

1.4 500 μm 2 150 mA 0.25

0 -0.7 -0.6 -0.5 -0.4 -0.3 -0.2 -0.1

0

0.1 0.2 0.3 0.4 0.5 0.6

Timing offset (Tb)

(c) Figure 7 (a) OSNR, and the average power vs. the timing offset of XPPM(t) observed at the; (b) output of AND gate, (c) output OS.

where the proceeding bits will experience a lower amplification gain. This can be minimized by decreasing the power of input packet. Figure 7(a) depicts the theoretical and simulation OSNR against the number of hops. The small difference between the results is due to the simulated packets having unequal power, see Fig. 6. The drop of 3 dB in the OSNR, after each hop, is due to the accumulated ASE noise. The affects of XPPM(t) timing-offset on the correlated outputs mk(t) and the average OS output power are given in Figs. 7(b) and (c), respectively. For all values of Tsw the maximum power is observed at timing offset of zero, i.e. when the target signal is at the centre of SW. For Tsw =

The affect of the timing offset could be evaluated by investigating the on / off contrast ratio ron /off, which is defined as 10log10 (desired output packet power undesired output packet power). From Fig. 8, the peak value of ron /off is ~20 dB over a wide range of timing offset (0.25Tb, 0.5 Tb and 0.75Tb). Tsw of 0.5 Tb offers the widest offset range of ~0.8Tb. For Tsw > < 0.5 Tb the power level sharply drops form it maximum value due to switching of incomplete desired and undesired signals, respectively.

25 20 15 On/off contrast ratio (dB)

0.25 Tb, the correlated output power is considerably lower over a shorter range of timing offset. This is because of a narrow SW only occupying part of the target signal. For Tsw ≥0.75 Tb the targeted pulse is located within a wider SW, therefore maximum powers are observed over a much wider range of timing offset. However, a wider SW will result in switching the non-target signal.

10 5

[1] [2] [3]

[4]

[5]

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Tsw=0.75Tb Tsw=Tb

-10 -15 -20 -25

-0.7 -0.6 -0.5 -0.4 -0.3 -0.2 -0.1

0

0.1 0.2 0.3 0.4 0.5 0.6

Timing offset (Tb)

Figure 8 The on / off contrast ratio against the timing offset of PPM header [6] [7]

References

Tsw=0.5Tb

-5

4. Conclusions In this paper, the node architecture, operation principle and performance of the all-optical router using PPM formatted header address and routing table were presented. It was shown that the correlated packet header address power and switched signal on-off contrast ratio largely depends on the switching window width and the timing offset of the PPM header address. The proposed router offers fast processing time and reduced system complexity and is capable of operating in the unicast, multicast and broadcast transmission modes.

Tsw=0.25Tb

0

[8]

[9] [10] [11]

[12]

[13]

[14]

[15] [16]

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