IJRIT International Journal of Research in Information Technology, Volume 2, Issue 4, April 2014, Pg: 229- 232

International Journal of Research in Information Technology (IJRIT) www.ijrit.com

ISSN 2001-5569

An Optimised Structure for CIC Decimation Filter Sachin B R Student, R V College of Engineering,ECE,Bangalore,Karnataka,India [email protected]

Abstract Decimation filter is a type of filter used to reduce the sampling frequency. A Cascaded Integrator Comb (CIC) structure is used to implement this filter which has equal number of integrator and comb stages. In this paper, an optimised implementation of this filter is discussed which reduces the number of comb stages for a given order. The filter is modeled using VHDL, simulated in Modelsim and implemented on FPGA.

Keywords: Decimation, CIC filter, ModelSim,FPGA.

1. Introduction In many applications, for example in a communications system, the required signal may be only KHz wide but it may be centered at very high frequencies. Sampling such a signal at the Nyquist criteria, i.e. sampling at twice the highest input frequency, leads to a higher data rate of the signal. Processing a high data rate signal is a difficult task. Reducing the data rate of such signals would ease the processing significantly. In a communications system, two systems might be working at different rates which require a rate change process. This is achieved by the use of a decimator or an interpolator. In cases where decimation or interpolation rates are very high, implementation using finite impulse response filters (FIR) filters might be costly due to the requirement of large number of filter taps. CIC filters, which are an optimized class of FIR filters, introduced by Hogenauer [1], provide a very efficient means of implementing these filter functions without the requirement of multipliers. This paper discusses the architecture of CIC filters and the implementation aspects of decimation filter.

2. Existing method The CIC filter transfer function in the Z-plane is given by :

H ( z ) = H IN ( z ) H CN ( z ) =

(1 − z − RM ) N (1 − z −1 ) N


where R is differential delay and is usually 1 or 2.In this paper it is chosen to be 1,N is the filter order and M is decimation factor. The denominator is implemented using integrator stages and numerator is implemented using differentiator stages as shown in fig 1 and 2 respectively.

Sachin B R, IJRIT


IJRIT International Journal of Research in Information Technology, Volume 2, Issue 4, April 2014, Pg: 229- 232

Fig 1: Integrator

Fig 2: Differentiator

The CIC filter is a cascade of digital integrators followed by a cascade of combs (digital differentiators) in equal number as shown in fig 3. Between the integrators and the combs there is a digital switch or decimator, used to lower the sampling frequency of the combs signal with respect to the sampling frequency of the integrators. The integrator stages operate at a clock frequency of fs, while differentiator stages operate at fs/M . N integrators Z-1

Z-1 fs

N combs


Z-1 -1 fs


Z-1 -1


Fig 3: CIC filter The delay block (Z-1) is implemented as a register whose size is given by the formula:

Wi = N log2 ( RM ) + Bin


where Bin is the number of input bits Wi is the register size of ith stage The number of output is also the same as Wi.

3. Proposed method In the proposed method, for an order N, the structure consists of N integrators and N-1 differentiators. The digital switch in between acts like a differentiator thus reducing the need of one more differentiator.. The functioning of the switch is such that at every clock of differentiator, the register in Nth stage of integration is stored with the register value of (N-1)th stage and at every clock of integrator, the normal functioning of an integrator is implemented i.e. adding its contents with (N-1) register and storing the sum in the same register. This functionality removes the need of a differentiator stage. Thereby reduces hardware utilisation and power dissipation.

4. Results A decimation filter with decimation factor of 4 and 3rd order is implemented. The fig 4 shows the various clocks and the functionality of the switch. The input is a sine wave of 16 bits. As we can see in fig 4, the differentiator and output (d_dec) changes at clk_differentiator and integrator as well as input is changing at clk_integrator. Hence a decimation of 4 is obtained.

Sachin B R, IJRIT


IJRIT International Journal of Research in Information Technology, Volume 2, Issue 4, April 2014, Pg: 229- 232

Fig 4: Switch functionality The fig 5 shows the full view of fig 4 .As we can see, the input is a sine wave and output is also a sine wave but changing at the rate of 4 times lesser than the input.

Fig: Input, output waveforms The tabular column depicted below shows the device utilization summary of the device xc3s500e -4 fg320. Table 1: Device utilization summary Number of slice flip flops


Number of 4 input LUT


Number of occupied slices


Number of slices containing related logic


Number of slices containing unrelated logic


Total number of 4 input LUT


Number used as logic


Number used as feed-thru


Number of bonded IOBs


Number of BUFGMUXs


5. Conclusion In this paper the CIC decimator structure is optimized in terms of hardware required for its implementation. This reduces the area occupied and power dissipation significantly compared to the existing method. The Sachin B R, IJRIT


IJRIT International Journal of Research in Information Technology, Volume 2, Issue 4, April 2014, Pg: 229- 232

results are verified in Modelsim. The design is implemented in Xilinx Spartan 3E FPGA and verified in hardware.

6. References [1] Hogenauer, E., "An economical class of digital filters for decimation and interpolation," Acoustics, Speech and Signal Processing, IEEE Transactions on , vol.29,no.2,pp.155,162,Apr 1981,doi: 10.1109/TASSP.1981.1163535 [2]Koppula, R.M.R.; Balagopal, S.; Saxena, V., "Efficient design and synthesis of decimation filters for wideband delta-sigma ADCs," SOC Conference (SOCC), 2011 IEEE International , vol., no., pp.380,385, 26-28 Sept. 2011 [3]Shiqian Zhang; Jing Qi; Jie Bao, "The improvement of design for CIC compensation filter," Electronics, Communications and Control (ICECC), 2011 International Conference on , vol., no., pp.1712,1715, 9-11 Sept. 2011 [4]Awasthi, V.; Raj, K., "Power performance analysis of compensated Cascaded Integrator Comb (CIC) filter in optimum computing," Power and Energy in NERIST (ICPEN), 2012 1st International Conference on , vol., no., pp.1,6, 28-29 Dec. 2012 [5]Sharma, S.; Kulkarni, S.; Vanitha, M.; Lakshminarsimhan, P., "Hardware Realization of Modified CIC Filter for Satellite Communication," Computational Intelligence and Communication Networks (CICN), 2010 International Conference on , vol., no., pp.41,44, 26-28 Nov. 2010 [6] Anna Engelbert, Carl Hallqvist,”Computable efficient recursive filters”, pp.14-23, Chalmers University of Technology, Sweden,2008.

Sachin B R, IJRIT


An Optimised Structure Optimised Structure Optimised ... - IJRIT

Student, R V College of Engineering,ECE,Bangalore,Karnataka,India sachinbrraj@gmail. ... Fig 2: Differentiator. The CIC filter is a cascade of digital integrators followed by a cascade of combs (digital differentiators) in ... digital switch in between acts like a differentiator thus reducing the need of one more differentiator.. The.

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