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APPLICATION NOTE

The Quick-Pulse Programming™ Algorithm

TERRY KENDALL PROGRAMMABLE MEMORY OPERATION INTEl,. CORPORATION

Intel developed the Quick-Pulse Programming™ algorithm to dramatically reduce the programming throughput time in production environments. The algorithm supports plastic and PLCC (plastic Leaded Chip Carrier) EPROMs because these devices are ideally suited for production applications. By using the QuickPulse Programming algorithm, a substantial decrease in programming time can be realized over older programming algorithms. For example, a 256k EPROM can be programmed in under four seconds, a 40 fold time improvement over the inteligent Programming™ algorithm.

BENEFITS FOR THE PRODUCTION ENVIRONMENT The Quick-Pulse Programming algorithm has been introduced as the primary programming technique for OTpTM (One Time Programmable) EPROMs. OTP Plastic DIP EPROMs are ideal for production because they can be used in auto-insertion and auto-programming machines. Ceramic DIP (CERDIP) versions of newly introduced devices including the 27C256 and Megabit EPROMs (27010, 27011, and 27210) can also use Quick-Pulse Programming. Because of their erasability and reprogrammability, CERDIP EPROMs are used for prototyping and system development. When manufacturing begins, OTP EPROMs can be programmed as needed on the production floor using the Quick-Pulse Programming algorithm. If an error in firmware is discovered or a density increase is required after manufacturing has commenced, the production line need not come to a halt. Changes can be implemented instantly with OTP EPROMs. Scrapping an entire stock of masked ROMs or waiting weeks for revised ROMs is no longer necessary.

For surface-mount and space constrained applications, PLCC EPROMs are ideal. The footprint of a PLCC requires only 1/3 the surface area of a conventional DIP EPROM. PLCes provide additional usable board space because both sides of the printed circuit board can be used for device surface mounting. To keep pace with automated handling equipment, which is used extensively with PLCCs, production line programming equipment must have fast throughput times. Again, the Quick-Pulse Programming algorithm comes to the rescue. Coupled with auto-handlers, Quick-Pulse Programming equipment can place code in PLCC EPROMs on the production floor. The primary benefit of plastic EPROMs and the QuickPulse Programming algorithm is throughput time (TPT). The Quick-Pulse Programming algorithm provides a significant increase in the number of units that can be programmed in a given time. Below is an example that compares a typical PROM programmer (using the inteligent Programming algorithm) with a state-ofthe-art Quick-Pulse Programmer. Although the inte!igent Programmer in the example above is typical of high quality programmers on the market today, it can achieve a TPT of only 3% that of an optimized Quick-Pulse Programmer. To put this in production terms, a supply of EPROMs that previously required a month to program using conventional programming equipment can now be programmed in only half a day using Quick-Pulse Programming equipment. The Quick-Pulse Programming algorithm is supported by many single socket programmers. Coupled with automatic handlers, these programmers can be used for automated programming. High performance gang programmers that approach theoretical Quick-Pulse Programming times are also available.

Quick-Pulse

Programmer

Typical Intellgent Programmer

Auto Handler time/part Programming time/part (256k) Total time/part

0.5 sec/part 4.0 sec/part 4.5 sec/part

0.5 sec/part 158 sec/part 158.5 sec/part

Total Total

800 U/hour 139 kUlmonth

22 3.9

units/hour units/month

U/hour kU/month

CJ!p ADDRESS

= FIRST

QUICK-PULSE PROGRAMMING CHARACTERISTICS The Quick-Pulse Programming algorithm uses a higher VPP voltage than the inteligent Programming algorithm to provide greater programming energy. This leads to faster programming. Overprogramming pulses are eliminated by using a higher reference level to check cell charge margin. At the beginning of the programming sequence, Vcc is raised from 5.0V to 6.25V

LOCATION

and Vpp from 5V to 12.75V. A 100 microsecond programming pulse is applied and immediately followed by a byte verification. Up to twenty-five program/verify cycles are provided per byte before a programming failure is recognized. When all bytes are programmed, Vcc and Vpp are lowered to their 5.0V read mode voltages. All bytes are then compared with the original data to confirm proper programming. A flowchart of the Quick-Pulse Programming algorithm is shown in Figure 1.

inter Theoretical

EPROM

Programming

Quick-Pulse P2764A N27C64 N87C64 P27128A1N27128A P27256

27C256/N27C256 P27512 P27513

27010/P27010 27011/P27011/N27011 27210/P27210/N27210

THEORETICAL TIMES

Intellgent

sec sec sec sec sec sec sec sec sec sec sec

0.875 0.875 0.894 1.75 3.50 3.50 7.04 7.04 14.00 14.00 6.99

32.86 32.86 32.87 65.71 131.29 131.42 262.89 262.89 525.69 525.69 262.84

The Quick-Pulse Programming algorithm decreasees the program pulse to only 10% that of the inte!igent Programming algorithm and eliminates the overprogram pulse. Idle time inherent in older programming algorithms has been drastically reduced by the shorter program pulse of the Quick-Pulse Programming algorithm. Theoretical programming times are most easily achieved if fast microprocessors and efficient programming code are used.

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MINIMUM

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Data obtained during Quick-Pulse characterization of the 27C256 shows that over 87% of these devices program within 3.38 seconds and 99.7% within 5.8 seconds; the minimum program pulse time required for a 27C256 is 3.28 seconds. Figure 2 is a graph of the percent of 27C256 EPROM cells programmed versus the number of 100 IJos pulses required. The Quick-Pulse Programming algorithm takes advantage of the fact that most EPROM cells program during the ftrst 100 IJospulse.

A comparison of minimum Quick-Pulse Programming and inteligent Programming times is shown in Table 1. With program-verify and read-verify times added to the programming time, the Quick-Pulse Programming algorithm achieves a 97% decrease in total programming

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sec sec sec sec sec sec sec sec sec sec sec

intellgent Identlfler™

time. Decrease of the program pulse width impacts most on the program/verify cycle time. Decreasing the total pulse time from a minimum of 4 ms (tPW + tOPW for the inteligent Programming algorithm) to 0.1 ms (Quick-Pulse Programming algorithm) results in dramatic program time reduction.

PROGRAMMING

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The EPROM storage cell consists of a single MOS transistor with a floating gate (made of a layer of polysilicon surrounded by oxide layers) placed between the select gate and the substrate's diffusion layer. Figure 3 shows a simplified cross section of an EPROM cell. Data, representing a logic "0", is stored in the cell by placing electrons on the floating gate. The polysiliconoxide interface creates a 3.1 eV potential barrier that traps these electrons on the floating gate. The absence of electrons on the floating gate represents an unprogrammed state; a logic "I". Electrons are removed from the floating gate by exposure to ultra-violet (U.V.) light of wavelength 2537A. Photons contained in the high frequency U.V.

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electrons in a high energy state which allows them to overcome the 3.1 eV energy barriers of the interpoly oxide and gate oxide. With this energy the electrons are able to reach the Poly-2 layer (select gate) or substrate where they are removed from the cell. Just as removing electrons (erasing) requires overcoming the energy barriers imposed by the gate oxide, programming requires energy to move electrons in the opposite-direction. Placing a high voltage, Vpp, on the select gate and on the drain of the transistor allows programming (see figure 4). This potential causes electrons to be accelerated as they move from the source to the drain. Some of these electrons reach a high enough energy state to be drawn onto the floating gate.

Programming

vG=vpp

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SELECT GATE

eeel

v

v

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More efficient programming of an EPROM cell is achieved by increasing the programming voltage, Vpp. As the programming voltage increases, the energy supplied to electrons as they accelerate through the channel increases. This energy allows "hot electrons" to overcome the potential barrier of the gate oxide. Since increasing the Vpp voltage makes for more efficient programming, the time required to place charge on the floating gate decreases. The Quick-Pulse Programming algorithm takes advantage of this. Data stored in an EPROM cell is represented by the threshold voltage required to turn on the MOS transistor. In the Read Mode, information is requested from a cell by placing a voltage approximately equal to Vcc on the select gate. If the transistor turns on, a logic "1" is interpreted; if the transistor remains off, a logic "0" is detected. Programming an EPROM cell alters the threshold voltage required to turn on the transistor. The larger the number of electrons on the floating gate, the more effective is the blocking of the positive select gate voltage. Figure 5 shows the I-V relationships of programmed and unprogrammed EPROM cells. To provide extra margin for Vcc fluctuations, EPROMs rated to operate at 5V ± 10% must have programming margins that are at least 5.5V. The QuickPulse Programming algorithm monitors the cell charge margin by using a closed loop technique that is much more stringent than other algorithms. Applying 6.25V to Vcc allows the algorithm to detect marginally programmed cells.

Reliable programming of EPROMs requires more than just an efficient algorithm. Good design practices should be followed when designing a PROM programmer to ensure that timing parameters, voltage parameters, and sequencing of control signals are properly implemented. The power supply that drives the EPROM to its programming levels should be well regulated. Circuit board traces should be short, low-inductance lines that are decoupled at Vcc and Vpp device inputs with highfrequency capacitors; typically 0.1 /loFceramic capacitors. In addition, a 4.7 jJ.F electrolytic capacitor should be used between Vcc and GND for every eight devices. Planes for routing Vcc and GND should be used to reduce the effects of current surges and ground loops (see application notes AP-74 and AP-238, available from Intel literature). Noise is the most common nemesis of programmer design. Voltage swings caused by switching circuitry can cause significant noise on Vco GND, Vpp, address, data, and control inputs. To reduce the effect of current surges caused by these voltage swings, decoupling capacitors and isolation of the programming socket(s) should be employed whenever possible. Overshoot and undershoot should be minimized to keep voltage parameters within the limits specified in the data sheets. A high-bandwidth oscilloscope (at least 150 MHz) should be used to monitor the signals at the programming socket (with EPROM inserted).

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inter Since Vpp is the highest voltage applied to an EPROM, it is closest to the physical limits of the device. A Vpp voltage above 14.QVfor any length of time will cause permanent damage to the EPROM. Proper decoupling capacitors should be placed at all Vpp inputs to help prevent damage caused by transients. Again, a highbandwidth oscilloscope should be used to look for overshoot when adjusting Vpp. Clean switching ofVcc and Vpp voltages will help ensure proper programming. Circuits for switching these voltages are easily built. Article reprint AR-294, which can be ordered from Intel's literature department, has example circuits that can be used to cleanly switch Vcc and Vpp from 5V to their programming voltages. These switching circuits also allow VCC and Vpp to be switched off so EPROMs are not hot-socketed when they are inserted and removed.

Production of electronic equipment requires programmable memory devices that can be used in auto-test and auto-insertion machines. Electronic systems also require program memory that can be changed easily when code crashes or program errors occur. Plastic and PLCC EPROMs provide solutions to both of these needs. They can be used in automated test and manufacturing equipment, and code changes can be implemented immediately. To reduce the programming times of these devices to accommodate production-line speeds, Intel has developed the Quick-Pulse Programming algorithm. Intel's line of plastic EPROMs can now be tested, quickly programmed, and mounted on circuit boards by totally automated production equipment.