APPLICATION NOTE
AP-345
October 1990
Implementing 10Base-T Networks .with Intel's Twisted Pair Ethernet* Components and Supercomponents
WILLIAM WAGER TECHNICAL MARKETING ENGINEER
'Ethernet is a registered trademark of Xerox Corporation.
Order Number: 292080-001 1-570
Implementing 108ase-T Networks with Intel's Twisted Pair Ethernet Components and Supercomponents
CONTENTS
CONTENTS
PAGE
PAGE
3.3 Using the 82523TB Twisted Pair Ethernet MAU to Convert Existing Ethernet Nodes to 1OBASE-T ..... 1-579 3.4 Designing a MAU Using the 82506TB Twisted Pair MAU Chip .. 1-579
PROLOGUE ........................... 1-572 1.0 INTRODUCTION ................... 1-572 2.0 SYSTEM DESCRiPTION ........... 1-574
3.5 Designing a Multiple Port Repeater Based on the 82505TA MPR ...... 1-579
2.1 Network Description ............. 1-574 2.1.1 Medium Attachment Unit .... 1-574 2.1.2 Multiple Port Repeaters ..... 1-575 2.1.3 Data Terminal Equipment ... 1-576
3.5.1 82505TA to 82504TA Interface and Clock Generation .................... 1-579
2.1.4 Link Segments ............. 1-576
3.5.2 Twisted Pair Port Design .... 1-581
2.2 Integrating with Existing 802.3 Networks ......................... 1-576
3.5.3 AUI Port .................... 1-581 3.5.4 Port Disable Control ........ 1-581 3.5.5 LED Control ................ 1-581
2.3 Software Compatibility ........... 1-577
3.0 NETWORK SYSTEM COMPONENT DESIGN ............................. 1-577 3.1 Designing a DTE Node Based on the 82521TB Serial Supercomponent ................. 1-577 3.2 Designing a DTE Node Based on the 82506TB Twisted Pair MAU Chip .............................. 1-577 3.2.1 Host to Ethernet LAN Controller Interface ............ 1-579 3.2.2 Ethernet LAN Controller to 82C501AD Interface ........... 1-579 3.2.3 The 82C501AD to 82506TB Interface ....................... 1-579 3.2.4 The 82506TB to Analog FrontEnd Interface (AFE) ............ 1-579
4.0 ANALOG FRONT END ............. 1-584
4.1 Preconditioning Voltage Summer .......................... 1-584 4.2 High-Voltage Protection ......... 1-584 4.3 EMI Filter ........................ 1-584 4.4 Line Coupling Devices ........... 1-584 4.5 Layout Considerations ........... 1-586 5.0 SUMMARY ......................... 1-587
APPENDIX A. EQUATIONS FOR EPLD VERSION OF 10BASE-T STATE MACHINES .......................... 1-588
1-571
AP-345
the medium access control (MAC) and physical signaling sublayers. This means that a twisted pair Ethernet LAN based on these products will be software compatible with 802.3 standard networks, and can be included in mixed networks by connection through a standard attachment unit interface (AUI) port of a repeater.
PROLOGUE At the time of this publication, the IEEE 802.3's JOBASE-T task force is completing its work writing the Twisted Pair Ethernet standard, and the IEEE 802.3 working group has approved the standard. The draft is finished, all that remains is for the IEEE Technical Committee on Computer Communications to approve the draft and to forward it to the IEEE Standards Board, which is expected in September 1990. The work now falls to the designers of JOBASE-T products to implement the standard correctly. The objective of this application note is to aid system designers to meet this goal.
A twisted pair Ethernet LAN using these products consists of several elements: data terminal equipment (DTE), medium attachment units (MAU), multiple port repeaters (MPR), and a cable plant. More complex networks, which connect to existing 802.3 networks (e.g., JOBASE5 or JOBASE2), can be constructed by using the 802.3-standard AUI port of the MPR. A typical network using all of these elements is shown in Figure 1.
1.0 INTRODUCTION This application note is presented as an aid to designing a twisted pair Ethernet (TPE) LAN using Intel's TPE products and Intel's family of Ethernet LAN controllers (82586, 82590, and the 82596 family). It is aimed at system designers working on TPE designs who have working knowledge of the IEEE 802.3 standards and some analog design expertise. It can be used in conjunction with application note AP-274, Implementing Ethernet/ Cheapernet with the Intel 82586, by Kiyoshi Nishide. It supersedes AP-324 Implementing Twisted Pair Ethernet with the Intel 82504TA, 82505TA, and 82521TA. Intel has introduced the 82521TB Serial Supercomponent (SSC), the 82523TB Medium Attachment Unit (MAU), the 82505TA Multiport Repeater Controller (MPR), and the 82506TB Twisted Pair MAU Chip (TPMC). They simplify the design of Twisted Pair Ethernet LANs based on the JOBASE-T standard. The JOBASE-T network is compatible with other ANSI/ IEEE 802.3 networks (e.g., JOBASE5 and JOBASE2) at
Four types of DTE and MAU combinations are shown. Two are embedded MAUs (contained within the DTE) and two are external MAUs (connected to the DTE node through a standard AUI cable). The embedded MAU designs .use either the 8252lTB SSC or the 82506TB TP MAU chip and its associated. circuitry. One external MAU is the 82523TB, the other is based on the 82506TB. The repeaters are designed around the 82505TA and also contain one 82504TA. Each repeater contains 11 twisted pair ports, with embedded MAUs, and 1 AUI port. The cable plant consists of standard telephone wire: either 4- or 25-pair, unshielded, twisted pair (26-22 gauge). Each segment uses two twisted pairs, transmit (TD) and receive (RD), and can coexist with other services (such as standard telephone) in the same cable bundle. Each segment has a maximum length of 100 m.
1-572
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AUI (50 m)
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'OTE: Data Terminal Equipment 82521T8 MAU: Medium Attachment Unit FOIRL: Fiber Optic Interrepeater Link TSI: Transceiver Serial Interface AFE: Analog Front-End SSC: Serial Supercomponent MSC: MAU Supercomponent
.
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292080-1
lmet
AP·345
bit, resulting in greater induced jitter. Figure 2 shows the idealized output waveform for the preconditioned signal at the transmitter. Preconditioning the signal limits the jitter added by the MAU and a loo-m twisted pair cable to 3.5 ns (8.0 ns when the MAU is directly attached to a 100-0 load).
2.0 SYSTEM DESCRIPTION 2.1 Network Description Table I compares the IOBASE-T network features with the older standards IOBASE5 and IOBASE2.
The common mode to differential impedance balance of the tran~mitter must exceed 29 - (17 X log f/lO) db, where f IS the frequency in megahertz. The magnitude of the total common output voltage will be less than 50 mVpeak. A~ditionally, ~he application of a 15-Vpeak> 10.I-Mhz SIne wave Will not change the differential voltage by morethan 100 mV or add more than 1.0 ns edge jitter for all data sequences.
2.1.1 MEDIUM ATTACHMENT UNIT
The MAU, or transceiver, provides the circuits required to interface to the twisted pair wire. It performs the following functions: line driving with preconditioning, line receiving, collision detection, linkbeat transmission, link integrity processing, jabber protection, and signal_quality_error test. MAU Line Drivers. The transmitter is designed to drive a 96-0 ± 20% load (76 to 115 0) and must meet all the specifications when connected to a 100-0 resistive load. It is dc isolated from the twisted pair by a transformer, and has a matched source impedance of96 o ± 20%. It will achieve a drive level of 2.2- to 2.8-V peak differential when driving a 100-0 load. When the driver is sending a IO-MHz data pattern all harmonics must be 27 db below the fundamental. The signal is Manchester encoded. The return loss of the transmitter shall be 15 db below the incident signal in the 5- to 10Mhz range whenever the source impedance of the measuring device is between 85 and III O. These specifications applies whenever power is applied to the MAU. A preconditioning algorithm is incorporated into the tran~~it circuitry. This algorithm improves overall sys~em Jitter performance by reducing the amount of jitter Induced by the twisted pair. The line drivers will drive full amplitude during "thin" (50 ns) pulses and the first half of "fat" (100 ns) pulses. They will reduce their drive level to approximately 33% during the second half of "fat" Manchester pulses. This prevents the tw~sted pair from overcharging during the fat pulses. Without this preconditioning, the overcharge would cause a delay in the zero crossing following the "fat"
MAU Line Receivers. The MAU line receivers are also dc isolated by a transformer. They must have a matched differential impedance such that the return loss is at least 15 db below the incident signal in the range from 5 to 10 MHz whenever the source impedance of the measuring device is between 85 and III O. It must operate properly in the presence of any valid Manchester signal with a magnitude of 0.585 to 3.l-V differential and up to ± 13.5 ns of edge jitter. It detects the End of Packet (IDL signal) within 2.3 bit times. 'I.'he sque~ch circuit rejects as noise any of the following s~gnals: Signals less than 300 mVpeak in magnitude, all slgn.als less than 2 Mhz and 6.2 Vp_p' and any sinusoid of SIngle cycle duration starting at either zero crossing and between 2 and IS Mhz and less than 6.2 Vp _p ' It can tolerate a 25- Vp_p' 500-kHz square wave and add no more than 2.5 ns of edge jitter to the signal. C:olIision Detect. The MAU detects collisions by the simultaneous occurrence of activity on transmit and re- . c.eive pair. Collisions are detected by transmitting statIons and repeaters. When a transmitting station detects a collision it begins the normal 802.3 collision sequence of jam, random back off, and retransmit. When a repeater detects a collision it also begins a jam on all ports and it enforces the minimum frame length of 96 bits.
Table 1 Comparison of Network Features FEATURE
10BASE·T
10BASE5
10BASE2
Access Method Data Rate Controller
CSMAlCD 10 Mb/s 82586/82596
CSMAlCD 10 Mb/s 82586/82596
82590/82592
82590/82592
Existing 100 m Star Unshielded TP 960 RJ-45
Existing 500m Bus Yellow Coax 500 N or Piercing
CSMAlCD 10 Mb/s 82586/82596 82590/82592 Existing 185 m Bus Thin Coax 500 BNC
Software Segment Length Topology Wire Impedance Connector
1
1-574
Ap·345
Yellow Cable Tx Waveform
o
o
o
TPE Tx Waveform
292080-2
Figure 2. Preconditioned Waveform
Loopback. During transmission without collisi~n, the loopback function of the 10BASE-T MAU will also route the transmitted data back to the DTE on the receive circuit. This function mimics the natural data loopback which occurs in coax MAUs. Link Integrity. The link integrity function is a process by which the IOBASE-T MAU can det~rmine if its r~ ceiver is properly connected to a compattble MAU. If1t is not it disables its transmitter, receiver, and loopback functions. This prevents a one-way link failure from indefinitely disrupting the network, since the carrier sense function is dependent on the receiver. When a bad link disables a MAU's carrier sense function, it removes itself from the network. The link integrity function is accomplished by two independent and asynchronous activities--one for the transmitter and one for the receiver. The transmitter will fill long periods of idle with link test pulses Oink beats). A link beat is transmitted after every 8 to 24 ms of silence. This defines a maximum period of silence the remote receiver Will experience regardless of network traffic. The receiver monitors its circuit for data packet and link beat reception from the remote MAU transmitter. If an excessively long period of silence occurs, the MAU will disable its receiver, transmitter, and loopback functions. Link beats are still transmitted in this mode. Once data or link beat reception resumes, the MAU reenables all its functions.
2.1.2 MULTIPLE PORT REPEATER The repeater is the central point in the star configured network. It is usually located in a telephone closet or other central wiring point. The link segments (repeater to node or repeater to repeater connections) are then made by using available twisted pairs in the existing telephone cable plant or a dedicated cable plant. The repeater must conform to the ANSI/IEEE 802.3c-1988 standard for repeaters. It can have any number of dedicated IOBASE-T, 10BASE2, FOIRL, or 10BASE5 ports, and it can have. any number of attachment unit interface (AUI) ports. The AUI ports are DTE type (DB-IS female receptacle) and can be connected to any valid 802.3 MAU. All dedicated 10BASE-T ports must support the same functions as the 10BASE-T MAU and normal repeater port functions. The repeater supports autopartitioning and jabber protection. These two features prevent faulty. nodes from taking down the entire network. The autopartition algorithm monitors ports for consecutive collisions such as would happen if a coax segment (IOBASES or IOBASE2) were left unterminated or if the Tx and Rx twisted pairs were shorted together on a 10BASE-T segment. Once identified, that port is removed from the. network until the fault condition is removed; this allows the remainder of the network to operate normally.
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I
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AP-345
the remote MAU. That is, pin 1 (TD+) on a MAU with an embedded crossover is connected to the Transmit Data (+) of the remote MAU and to its own Receive Data (+). The crossover function is defined by the following connections between MAU A and MAU B shown in Table 3. TABLE 3. MAU A AND MAU B CONNECTIONS
The jabber function of the repeater monitors the length of incoming data. If it detects an abnormally long frame it breaks it into legal lengths by inserting minimum interframe spaces on its transmitted signal. This prevents any jabber condition from being repeated onto other segments. Repetition of the jabber condition would allow its own, and other MAUs, to enter, a fail state due to faults at a remote location, thus preventing normal operation of the network after the fault condition is removed. With the repeater's jabber protection, network operation resumes after the fault is removed.
MAUB
Signal
Signal
Pin
1
TD+(A) TD-(A) RD+(A) RD-(A)
RD+(B) RD-(B) TD+(B) TD-(B)
3 6 1 2
When an embedded crossover function is used in a DTE-to-repeater connection the crossover is usually embedded in the repeater MAU. In general, repeater MAUs have an embedded crossover and DTE MAUs do not. With proper use of the crossover function, repeaters can be cascaded through twisted pair ports and two DTEs can be connected in a point-to-point network. Repeaters can be cascaded two ways. First, one or more twisted pair ports on a repeater can be designed to have a switched (optional) crossover function. This allows a DTE connection on that port when the crossover is active; or a repeater connection, when the crossover is disabled. Secondly, two twisted pair ports with embedded crossovers can be connected by using a third external crossover.
2.2 Integrating with Existing 802.3 Networks.
2.1.4 LINK SEGMENTS
A lOBASE-T link segment connects two twisted pair MAUs; it comprises two medium dependent interface connectors (RJ-45 and 8-pin, standard telephone plugs), two pairs of twisted pair wire (not to exceed 100 m), and a crossover. The connector's pin assignments are shown in Table 2. TABLE 2. MDI CONNECTOR PIN ASSIGNMENTS Pin
Signal
1 2 3
Transmit Data + (TD+) Transmit Data - (TD -) Receive Data + (RD + ) Not Used Not Used Receive Data - (RD-) Not Used Not Used
4 5 6 7 8
MAUA
Pin
2 3 6
2.1.3 DATA TERMINAL EQUIPMENT
DTEs include the user nodes, file servers, bridges, and other entities that can originate and accept data packets on the network. DTEs contain the medium access control (MAC) and physical layer signaling (PLS) sublay- . ers. A DTE can also contain an embedded MAU. DTEs that do not have an embedded MAU have im AUI connector. DTEs with embedded MAUs have the medium dependent interface connector for that particular MAU (RJ-45 for lOBASE-T and BNC for lOBASE2). The MAC functions are handled. by the LAN controller (intel's 82586, 82590, 82592; or the 82596 family). ThePLSfunctions are handled by the serial interface component (82C501AD) or a combination PLS/MAU device (82504TA and 82521TB). This architecture represents a continuity of design for migration from Ethernet/Cheapernet designs to Twisted Pair Ethernet. Only the MAU part of the design needs to be updated. This is 100% software independent.
Pin
The crossover function connects the TD outputs of one MAU to the RD inputs of the other. This function can be external or embedded within a MAU. If the function is embedded the signal names on the connector refer to
Because lOBASE-T networks are fully compatible with existing 802.3 networks at the medium access control and physical layer signaling sublayers, lOBASE-T networks can be integrated with existing 802.3 networks to form one large network. The IEEE standard for repeaters allows connecting different wire types in lO-Mb/s baseband networks. This is because the repeater definition stops at the AUI connection (DTE sex). The wire type is determined by the MAU attached to the AUI connector, and can vary from port to port. Optionally, a repeater can have embedded MAUs on any of its ports. The only requirement for an embedded MAU is that functionality at the medium dependent interface point (e.g., coax tap or. twisted pair connector) be maintained as if the MAU were external. The 82505TA Multiport Repeater Controller provides embedded MAUs on 11 of its 12 ports, and an AUI connection on the remaining port. This allows creating local twisted pair subnetworks connected to an Ethernet backbone. Care must be taken not to violate the following system topology rules of 802.3 networks.
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Ap·345
The layout of the 82521TB and the RJ-45 connector s~lOuld keep the TD +, TD -, RD +, and RD - signal hnes as short as possible. The width of these signals should be at least twice the spacing between the signal trace layer and the ground plane. The power supply traces (Vee, VEE, and ground) should be as thick as possible, and bypass capacitors should be placed between each power supply and ground. An alternating strategy of 0.1- and O.OOl-/-LF decoupling capacitors should be used throughout the host circuit board. We also recommend laying out the 82521TB on a ground plane and connecting logic ground to chassis ground.
• Only one active signal path is allowed between any two stations on the network. • No more than four repeaters are allowed in the signal path between any two stations on the network. • There is an overall limit of 1024 stations on a network (repeaters do not count as stations).
2.3 Software Compatibility Because the IOBASE-T definition is restricted to the MAU, software is not affected. Twisted pair networks use the same LAN controller chips (82586, 82590, 82592, and the 82596 family) as current Ethernet and Cheapernet networks and are fully software compatible.
3.2 Designing a DTE Node Based on the 82506TB Twisted Pair MAU Chip
3.0 NETWORK SYSTEM COMPONENT DESIGN The design of various IOBASE-T network system components is presented in this section.. First, DTEs with embedded MAUs, then external MAUs, and lastly repeater designs.
3.1 Designing a DTE Node Based on the 82521TB Serial Supercomponent. A design for an 82521 TB based DTE node with an embedded MAU is shown in Figure 3. It includes all of the functions described in Section 2.1.1, thereby relieving the d~signer of those responsibilities. It is simple to use and It does not require mastering pole-zero diagrams. It is a direct interface from the Ethernet controller to the RJ-45 connector. Implementation of the Clear to Send (CTS) signal is optional.
Figure 4 shows a DTE node with an embedded MAU based on the 82506TB. It shows the Ethernet LAN controller, the 82C50lAD, an AUI transformer, the 82506TB, the analog front-end, and the connector. As i~ previous Ethernet designs, the LAN controller proVides the MAC services such as transmission deferral collision backoff and retransmission, CRC generatio~ and checking, and address checking. It also provides the host interface. The 82C50 lAD provides the serial interface function of Manchester encoding and decoding and clock recovery. The 82506TB provides the MAU functions, which include carrier sense, collision de~e?t link int~grity, jabber protection, twisted pair line dnvmg, and hne receiving. The analog front-end handles the preconditioning summation, filtering, balancing, and isolation requirements of 10BASE-T.
1-577
inter
AP-345
Power Supplies VCC ·+5V
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292080-3
Figure 3. 82521TB sse Interface
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292080-4
Figure 4. DTE Based on 82506TB
1-578
inter
AP-345
3.2.1 HOST TO ETHERNET LAN CONTROLLER INTERFACE
3.4 Designing a MAU Using the 82506TB Twisted Pair MAU Chip
The 82586 Ethernet LAN Controller interface is included in the Intel application note, AP-274.
Figure 6 shows a stand-alone MAU design using the 82506TB. It contains the same AUI transformer, 82506TB, analog front-end, and connector as the embedded design. The serial interface functions and MAC services are contained in a separate DTE. The standalone MAU functions include carrier sense, collision detection, link integrity, jabber protection, twisted pair line driving, and line receiving. The analog front-end handles the preconditioning summation, filtering, balancing, and isolation requirements of lOBASE-T.
3.2.2 THE ETHERNET LAN CONTROLLER TO 82C501AD INTERFACE The 82C50lAD to Ethernet controller interface consists of the direct connection of TxC, TxD, RxC, RxD, RTS (TEN), CRS, and CDT signals to the controller. A 20-MHz ± 0.01 % crystal, or crystal oscillator, is recommended for clocking the 82C501AD. Many crystals that meet the requirements of the 82C501AD are available commercially and are listed in the 82C501AD data sheet.
3.5 Designing a Multiple Port Repeater Based on the 82505T A MPR
3.2.3 THE 82C501AD TO 82506TB INTERFACE The 82C501AD to 82506TB interface is a standard AUI. It includes an isolation transformer to provide dc common mode isolation. 3.2.4 THE 82506TB TO ANALOG FRONT-END INTERFACE (AFE) The four transmit outputs of the 82506TB (HDAT, LDAT, HDAT, and LDAT) and two receive inputs (RD and RD) are connected to the analog front- end described in Section 4. The analog front- end handles preconditioning voltage summation, EMI filtering, and isolation.
3.3 Using the 82523TB Twisted Pair Ethernet MAU to Convert Existing Ethernet Nodes to 1OBASE-T
3.5.1 82505TA TO 82504TA INTERFACE AND CLOCK GENERATION
Any Ethernet node that supports the AUI (DB-15 connector) can be converted to a 10BASE-T node by using the 82523TB MAU. A standard AUI cable is used to connect the DB-15 connectors on the node and the 82523TB. The 10BASE-T cable then plugs into the RJ45 receptacle and the node is connected. The interface is shown in Figure 5.
AUI Coble
82523T8 Twisted Pair MAU
Twisted Pair
Figure 7 shows an MPR based on the 82505TA (with one 82504T A). It contains 11 twisted pair ports with embedded MAUs and 1 AUI port. The 82505TA controls the operation of the repeater in accordance with ANSI/IEEE 802.3c-1988 repeater unit specifications, which include signal retiming, automatic preamble generation, autopartitioning, and jam signal generation. The 82504TA does Manchester decoding and clock recovery while an incoming signal is active. Two addressable latches (74LS259s) are used to control the 16 LED indicators. A 4-to-16 decoder (74LSI54) is used to disable the transmitter of the receiving port during transmission without contention. The twisted pair port functions contain the line drivers, the line receivers, the filter, and the isolation required for a twisted pair embedded MAU. In addition, one AUI interface is present to provide access to existing (IEEE 802.3) lO-Mb/s baseband segments.
The 82505TA to 82504TA interface, shown in Figure 4, is straightforward. It consists of six signals directly connected between the devices. The signals are TRxD, TPS, MCV, CRS, RxC, and RxD. The 82504TA performs the Manchester decoding and clock recovery for the repeater. A single clock oscillator is recommended for clocking the 82505TA and 82504T A. The requirements are identical to those shown for the DTE design using the 82504TA. • Frequency Tolerance. ,0:0.01 % • Rise and Fall Times. ,0: 5 ns • Duty cycle. 60/40% or better
292080-5
• Output. TTL compatible Figure 5. 82523TB Interface
1-579
intJ
AP-345
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292080-6
Figure 6. MAU Based on 82506TB 82505TA
82504TA
~TERF,ACE
AUIRXD TRXD
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I I
r
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AUICRS
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74F154 (4 TO 16 DECODER)
292080-7
Figure 7. Repeater Design Based on 82505TA
1·580
AP-345
3.5.2 TWISTED PAIR PORT DESIGN
3.5.3 AUI PORT
The twisted pair port circuit, shown in Figures 8 and 9, provides the lOBASE-T functions for each twisted pair port. It uses the same AFE (see Section 4) as the 82506TB designs.
The AUI port circuitry is shown in Figure 10. It comprises interface circuits, the DO line drivers, two quad D-flip-flops (74F175s), and terminated line receivers for the DI (squelch and data) and CI (squelch only) circuits.
82S0STA to AFE Transmit Interface. This interface converts the four transmit signals (TRMT, TRMT, PDC, and TPEN) from the 82505TA, and the port enable (PEx) signal from the port disable control, to the four transmit signals of the analog front-end (TDH, TDL, TDH, and TDL). The design shown here uses an octal line driver (74ACT244) with the drivers paired. The circuit operates as follows. The TRMT and TRMT signal are XOR'd with the PDC signal to generate the proper logic signals for preconditioning. These signals are then gated by TXE (Transmit enable). a function of the TPEN signal and the PEx (Port Enable) signal. The signals are blocked whenever the repeater is idle, the Port Enable for this port is false, or the lOBASE-T state machines have disabled transmission. The gated signals then pass through the link beat generator. Link beats are broadcast during long periods of idle. The signals now pass to the 74ACT244 line drivers, through the AFE, and onto the twisted pair. Line Receivers. The incoming receive signal passes through the AFE into a gated line receiver controlled by the squelch circuitry. The line receiver converts the received differential signal to TTL levels and feeds it to the MPR. The receiver can be designed with a zero crossing detector (e.g., NE521) and is gated with the TCSx signal. State Machines. The state machines are required by the lOBASE-T draft standard; they handle link integrity and jabber protection. The implementation shown uses an Intel SCI80 EPLD. The equations are in iPLSII format and are in the appendix.
The CI squelch line receiver feeds the D-O and clear inputs for one of the quad D-flip-flop circuits. When a signal greater than the squelch offset is seen, the flipflops are cleared and AUICDT is asserted. This continues as long as CI is active. Squelch receiver output is held high during the start of idle and the flip-flops set in sequence. After four clocks, 150 to 200 ns, the last flip-flop is set and AUICDT deasserts. It remains deasserted during the entire idle period. The DI line receivers work in much the same way, except that activity on CI, or an active transmission, will inhibit AUICRS. The data channel on DI is processed without a voltage offset and is gated by AUICRS. This way, the least amount of jitter is added on the AUIRxD line and the data channel is not sensitive to idle noise. The DO line drivers are controlled by TPEN and PEl 1; the drivers should activate when both are asserted. A voltage divider is provided after the drivers to achieve the proper driver levels. 3.5.4 PORT DISABLE CONTROL Port disable control is handled by a 74LS154 4-to-16 decoder. During transmission without contention the address of the originating port is given to the decoder and the control line asserted. This disables the transmitter to that port. When a transmit based collision occurs the control line to the decoder is deasserted and jam is broadcast on all ports. 3.5.5 LED CONTROL
Squelch Circuit. The squelch circuit distinguishes noise from valid link beats and incoming data on the receive pair by detecting signals above a preset voltage level. When there is no signal on the receive pair the squelch circuit deasserts the CARR and LINK signals. Link is asserted when a signal above the threshold arrives. CARR is asserted if the required number of bits are seen. This causes TCSx to assert and the line receiver to be enabled.
Two 8-bit, addressable latches (74LS2S9s) handle this function. The controller cycles through the addresses for the LEDs each lOS ms and will turn each one on or off. The three least significant address bits (L2-La) for the LED control are fed to each 8-bit latch. The most significant address bit (L3) controls the enable line to the two packages. The LEDCTRL signal determines the state of the LED when it is strobed by LEDSTRB.
1-581
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74F86
74FOO
74FOO
74ACT244
TRIiotT
POC
TRIijT
'"U« .... '"'"
TO.
ANALOG FRONT END
I-
;!:
TO-
TCSx
.... u I'" -,z
",Z
IfJ
RO-
0 IfJ
N CIO
'"O
IfJI-
RD.
O
U
RESET TPEN
PEx
TPEN
PEx
LINK
LINK
TXC
TXC
5C180
Rx
IN
CO~
c:
SQUELCH
~
l'XC
292080-8
Figure 8. Repeater 10BASE-T Interface Port
IN
74HC4538
74HC4538
292080-9
Figure 9. Squelch CircuiUor 10BASE-T Port
1-582
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AP-345
NE521 CI+ CI-
...
.s
.
01+ 01-
0
.
... ~ .E
U)
"f!
""
I-
.>I.
0 0
~
~
15
. E . :5
0 U
AUICRS
~
::; «
.... "... a.
'" 1::
'"
8
0
20-MHz CLOCK
a.
:oJ
:; AUIRXD
::::E
loon TRMT
00+
loon 00-
TRt.lT
PE11 TPEN
292080-10
Figure 10. AUI Port
1-583
AP-345
transmit and two receive) as shown in the analog frontend schematic of Figure II. The diodes connect to Vcc and VEE (or ground). These should be placed at the interface between the active devices and the low pass filters so the active circuits are protected and the filter attenuates the transients.
4.0 ANALOG FRONT-END A discrete version of the analog front-end is shown in Figure II. This preliminary design filter has been extensively tested, and 'interoperability results were positive. The design will meet most of the IOBASE-T requirements with the following marginalities. 10BASE-T PARAMETER
RX Return Loss TX Return Loss Squelch at 10 MHz
SPEC 19 db 19db 585mV
4.3 EMI Filter
MEASURED
The main function of the low pass filter is to remove the high-frequency components of the transmitted signal without affecting the in-band (5 to 10 MHzffrequencies. The high frequency components can create electromagnetic -interference (EMI) above the levels permitted by FCC regulations. The design should provide minimum in-band loss, ripple, and distortion while providing maximum attenuation of frequencies above 30 MHz with appropriate roll-off in the transition band.
17.5 dB 17.5 dB 730mV
A fully characterized analog front-end design will be ready in October of 1990, and will be available through Intel sales offices. The analog front-end consists of two main sections: transmit and receive. The transmit section contains the preconditioning voltage summing circuit, high voltage protection, the EMI filter, and the line coupling devices. The receive section c()nsists of the line coupling devices, the EMI filter, and high-voltage protection.
We recommend a filter with the following characteristics. 5-pole elliptical • Filter type 5to 10 MHz • Pass band 27 db • Attenuation 2 30 MHz I db • In-band insertion loss <0.5 db (5 to 10 Mhz) • In-band ripple
A filter pack implementation is shown in Figure 12. Many designs are using this approach but this design has not yet been tested by Intel. A final design version will also be ready in October of 1990, and will be available through Intel sales offices.
4.1 Preconditioning Voltage Summer The twisted pair output drivers are configured into a single matched impedance differential driver with the preconditioning voltage summing circuit. This circuit is designed to give a preconditioned differential signal. During "thin" pulses, and the first half of "fat" pulses, the differential driver provides 100% drive level power. During the second half of "fat" pulses it provides only 33% drive level as required by the preconditioning algorithm.
The impedance of the filter must be matched to both the transmitter impedance and the line impedance. Also; balance and grounding should be tightly controlled for proper operation. Due to these considerations we recommend a differential filter built symmetrically on each line of the differential pairs with the impedance matched at each end.
This circuit provides a constant source impedance whenever power is applied; this controls matching the driver impedance to the twisted pair cable impedance. This will limit reflections that would result in excessive noise.
4.2 High-Voltage Protection Protection should be provided to prevent the active devices being damaged by high-voltage transients from the twisted pair line. We recommend placing a pair of diodes on each of the four differential signals (two
4.4 Line Coupling Devices The line coupling devices include the transformers and common mode choke. The transformers provide ac coupling between the line and the circuitry while providing dc isolation. The recommended minimum isolation is 2250 VDC. The windings should be identical to provide proper balance between the two ends of the transformers. To provide appropriate impedance matching in the frequency range of interest, the transformers should have appropriate primary and secondary inductance (200 J-LH typical) and minimal interwinding capacitance «20 pF).
1-584
_. c(
162 0.39
0.56
HDAT
¥Iv56.2 221 ~
LDAT
~
162
n¥,TJI
HDAT ."
cs·C
56.2
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221
....
:-'" l>
&, CD
U1
150
47..1.
33~
18~
24~
10
w..
T1
1)
L~~•
0.01J'~
•- - -
LDAT
~
DI 0 Ul
...
." 0 ~
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II RD
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TD+
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~ RD-:
I
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RD
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..1v
r---- ..1. "--127r---- ..1. 24~ 18~
..1. "--1 110
11~
0.56
R in Ohms (1/4 W +1%) (NPO +5%) C in pF (+5%) Lin uH SANYO SB05·05CP or equiv. D All component values should be valid over the frequency range from 1 to 100 MHz . T1, T2, and T3 are commercially available from Sprague, Valor, Pulse Engineering and others.
292080-11
inter
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56.2fl HOAT
221fl
IN
LOAT
OUT FILTER"
221n
r-----' I
C
I!--!-
I I IN
LOAT
TD+
1
~ _____ ~ 0.047 JLF
FILTER"
1:1 2 kV ISOLATIONt
56.2fl HOAT TRANSMIT
u:; RD+
OUT
IN
RD
FILTER"
93.1fl IN
RO
+----......----1
FILTER"
~ _____ ~ 0.047 JLF
1:1 2 kV ISOLATIONt
RECEIVE
292080-12
'Possible filters are the Pulse Engineering Inc. (PE32101), TDK Corp. (0921 ES), CTS Corp.-Knight Div. (9561928-01), Coilcraft (K9686-B), or equivalents. fRequired transformers are the AT&T (2759A), Pulse Engineering (PE65263), Coilcraft (LAXIOT-200), or equivalents.
Figure 12. Filter Pack Front End
The common mode choke rejects common mode radio frequency and electromagnetic interference picked up from the unshielded telephone lines. It should provide 1000-Vde isolation between the windings. The common mode choke has four windings, each connected with proper polarity, in series with the receive and transmit twisted pairs. The balance of the choke is very important for providing proper noise cancellation while passing through the differential signal unaffected. We recommend a common mode to differential balance of 30 db (measured according to the lOBASE-T draft specifications) at all frequencies up to 20 MHz.
• Clock traces, and other high-frequency traces, should be have a width of at least twice the separation between the trace and the nearest ground plane. • Connect logic and chassis ground together. • Separate and decouple all of the analog and digital power supply lines.
4.5 Layout Considerations
• Use high-loss magnetic beads on power supply distribution lines. • Group each of the receive and transmit circuits, but keep them separate from each other. Separate their grounds. • Layout all differential circuits symmetrically so parasitic effects are also symmetrical. • Layout the circuitry from the line connector to the active circuitry (especially the EMI filter) on a ground plane to prevent undesirable EMI effects.
The power and ground wiring should conform to good high- frequency practice and standards to minimize switching transients and parasitic interaction between various circuits. To achieve this, the following guidelines are presented. • Place bypass capacitors (0.1 and 0.001 /LF should be interspersed) on each IC between Vee and ground. They should be located close to the Vee pins. • Make power supply and ground traces as thick as possible. This will reduce high-frequency cross coupling caused by the inductance of thin traces. 1-586
• Close signal paths to ground as close as possible to their sources to avoid ground loops and noise cross coupling. • Connect all unused IC inputs (except as directed by the manufacturer) to ground or Vee to avoid noise injection or parasitic oscillations of unused circuits.
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AP-345
5.0 SUMMARY This application note presented several designs meeting the IEEE 802.3 10BASE-T draft standard lOBASE-T. They use standard telephone twisted pair wiring and a star configuration for cost savings and flexibility. They use the same IEEE 802.3 standard for CSMA/CD medium access control and, where applicable, the physical layer signaling. This network type is fully software compatible with, and can connect to present Ethernet or Cheapernet networks. The hardware connection is made through an 802.3 defined AUI port and by complying with the repeater standard ANSI/IEEE 802.3c1988.
Intel has introduced four products for designing network components (DTEs and repeaters). DTE design can be done with either the 82521TA Serial Supercomponent or the 82506TB TP Transceiver Chip. The supercomponent contains all the circuitry required between the Ethernet controller and the RJ-45 connector. DTEs that support the AUI can be instantly connected to lOBASE-T networks using the 82523TB MAU supercomponent. Multiple port repeaters can be designed using the 82505TA with an 82504TA. It allows for 11 twisted pair ports and 1 A UI port.
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Ap·345
APPENDIX A The following set of equations for programming the 5C 180 for the 1OBASE-T port design of a multiple-port repeater were generated from a proven lOBASE-T design. However, they were not verified in their present state. They are intended to serve as an example to aid in the development of a complete design. They are written in iSTATE format, a state machine compiler to be used in conjunction with IPLSII.
Thorn BOWDs/Bill Wager Intel Feb. 20, 1990 Repeater lBO Rev 0 SCIBO SCIBO for Multiple Port RepeaterOPTIONS: TURBO=ON PART:
Counters, State machines, etc.
SCIBO
INPUTS: OUTPUTS:
TXC', LID, WDTD, TPEN', PEx, TEST, CARR, LINK, RESET TCSx, LKBTt, TXE, WDT, SLOCLK, LI JT14 RESET, JTS8_RESET, LT_RESET~ SCQOl, SCQ02, SCQ03, SCQ04, SCQOS, SCQ06, SCQ07, SCQ08, SCQ09, SCQlO, SCQll, SCQ12, SCQ13, DLINK, JTQl, JTQ2, JTQ3, JTQ4, JTQS, JTQ6, JTQ7, JTQB, LTQl, LTQ2, LTQ3, LTQ4, LTQ5, LCQl, LCQ2, JFQl, LIFQl, LIFQ2
NETWORK: TXCn INP (TXC') INP(LID) LID = INP (WDTD) WDTD INP(TPENt) TPENn INP(TEST) TEST CARRIER INP (CARR) INP (LINK) SLINK INP (RESET) RESET INP (PEx) PEx TCSx LKBTt LKBTI TXE
CONF(TCSx,VCC) RONF(LBEATn,TXCn,GND,GND,VCC) NORF(ILBEAT,TXCn,GND,GND) CONF(TXE,VCC) 292080-13
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AP-345
% Timer reset feedback macrocells % JT14_RESET NOCF(JT14_RESETd) JT58_RESET = NOCF(JT58_RESETd) LT RESET NORF(LT_RESETd,TXCn,GND,GND) % SLOCLK macrocells % SCQOl NOTF(SCT01,TXCn,RESET,GND) SCQ02 NOTF(SCT02,TXCn,RESET,GND) SCQ03 = NOTF(SCT03,TXCn,RESET,GND) SCQ04 NOTF(SCT04,TXCn,RESET,GND) SCQ05 ~ NOTF(SCT05,TXCn,RESET,GND) SCQ06 NOTF(SCT06,TXCn,RESET,GND) SCQ07 NOTF(SCT07,TXCn,RESET,GND) SCQ08 NOTF(SCT08,TXCn,RESET,GND) SCQ09 NOTF(SCT09,TXCn,RESET,GND) SCQ10 NOTF(SCT10,TXCn,RESET,GND) SCQll = NOTF(SCTll,TXCn,RESET,GND) SCQ12 NOTF(SCT12,TXCn,RESET,GND) SCQ13 = NOTF(SCT13,TXCn,RESET,GND) SLOCLK,SCQ14 = TOTF(SCT14,TXCn,RESET,GND,VCC) SLOCK CLKB(SCQ14) DLINK - NORF(SLINK,TXCn,RESET,GND) % Jabber timer macrocells % JTQl = NOTF(JTT1,SLOCK,JT14_RESET,GND) JTQ2 = NOTF(JTT2,SLOCK,JT14_RESET,GND) JTQ3 - NOTF(JTT3,SLOCK,JT14_RESET,GND) JTQ4 a NOTF(JTT4,SLOCK,JT58_RESET,GND) JTQ5 NOTF(JTT5,SLOCK,JT58_RESET,GND) JTQ6 NOTF(JTT6,SLOCK,JT58_RESET,GND) JTQ7 - NOTF(JTT7,SLOCK,JT58_RESET,GND) JTQ8 NOTF(JTT8,SLOCK,JT58_RESET,GND)
% Link test timer macrocells % LTQl - NOTF(LTT1,SLOCK,LT_RESET,GND) ::OTF {LTT2, SLeCK, LT_RESET,GNDj LTQ3 = NOTF(LTT3,SLOCK,LT_RESET,GND) LTQ4 = NOTF(LTT4,SLOCK,LT_RESET,GND) LTQ5 NOTF(LTT5,SLOCK,LT_RESET,GND)
% Link count macrocells % LCQl NOTF(LCT1,TXCn,RESET,GND) LCQ2 = NOTF(LCT2,TXCn,RESET,GND) 292080-14
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EQUATIONS: % Input controlled variables % output_active - ! (TPENn + !PEx); output_idle - TPENn + !PEx; input_active - CARRIER; input_idle = !CARRIER; link_test_rcvd = SLINK*!DLINK; % Output equations % TCSx = input_active * !disable_receiver; ILBEAT - linkbeat_timer_done; LBEATn - !(ILBEAT * !LKBTI); TXE = !disable_driver- * output_active; disable_driver ~ disable_driver_3 + disable_driver 4; % Miscellaneous equations % link_count_is_3 = LCQ2 * LCQl; LCRESET LINK_TEST_FAIL_RESET * !link_test_rcvd; LCCOUNT = LINK_TEST_FAIL_RESET * link_test_rcvd + LINK TEST FAIL * link test_min_timer_done; LCTl = LCCOUNT + LCRESET * LCQl; LCT2 = LCCOUNT * LCQl + LCRESET * LCQ2;
link~test_rcvd
*
% ------------------------------------------------------- % % SLOCLK counter equations %
VCC; SCTOl SCQOl; SCT02 SCT02 * SCQ02; SCT03 SCT04 = SCT03 * SCQ03; SCT04 * SCQ04; SCT05 SCT05 * SCQ05; SCT06 SCT07 = SCT06 * SCQ06; SCT08 = SCT07 * SCQ07; SCT08 * SCQ08; SCT09 c,..,...nn .. SCTC9 <6- ......... SeTl!} \lv." SCTlO * SCQlO; SCTll TEST + !TEST * SCTll * SCQll; SCTl2 SCTl3 ~ SCTl2 * SCQl2; SCTl4 SCTl3 * SCQl3; % JABBER timer equations % transmit timer done = JTQ5 * NON JABBER OUTPUT; unjab_t~r_do~e - JTQ8 * JTQ7 *-UNJAB_WAIT; unjab_timer_not_done = !unjab_timer_done; linkbeat_timer_done = JTQ3 * !NON_JABBER_OUTPUT JTl4_RESETd = RESET + NO_OUTPUT * output_active + NON JABBER OUTPUT * output idle; JT58_RESETd = JTl4_RESETd + JAB * output_idle;
*
!LID;
292080-15
1-590
AP-345
VCC; JTTl JTT2 JTTl JTT2 JTT3 JTT3 JTT4 JTT4 JTT5 JTT5 JTT6 JTT6 JTT7 JTT7 JTTB JTCOUNT = !
* * * * * * *
JTQ1; JTQ2; JTQ3; JTQ4 * JTCOUNT; JTQ5; JTQG; JTQ7; (JTQ5 * JTQ6 * JTQ7 * JTQB);
% LINK timer equations %
link_loss_timer_done -LTQ5 *LTQ4 *LTQ3 *LTQ2 *LTQl * IDLE_TEST; link_test_min_timer_done = (LTQ3 + LTQ4 + LTQ5) * «IDLE_TEST) + (LINK_TEST_FAIL»; link_test_min_timer_not_done = !link_test_min_timer_done; link_test_max_timer_done = LTQ5 * LINK_TEST_FAIL; LT RESETd IDLE_TEST * (input_active + (link_test_rcvd * link_test_min_timer_done» + LINK TEST FAIL RESET + LINK_TEST_FAIL * link_test_min_timer_done * link- test- rcvd + LINK_TEST_FAIL_EXTEND;
-
LTTl LTCOUNT; LTCOUNT * LTT2 LTT3 LTCOUNT * LTT4 LTCOUNT * LTT5 LTCOUNT * LTCOUNT = !(LTQl
LTQ1; LTQl * LTQl * LTQl * * LTQ2
-
LTQ2; LTQ2 * LTQ3; LTQ2 * LTQ3 * LTQ4; * LTQ3 * LTQ4 * LTQ5)i 292080-16
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% ------------------------------------------------------- %
MACHINE: JABBER_FUNCTION TXCn CLOCK: RESET CLEAR: STATES: NO_OUTPUT NON_JABBER_OUTPUT JAB UNJAB_WAIT
NON_JABBER_OUTPUT:
WDT .JFQl 0 0 1 1
% JFQ2 is WDT also %
]
0
]
1 1
] ] ]
0
% start_transmit_timer % IF (output_active * transmit_timer done THE:N JAB IF output_idle THEN NO_OUTPUT
JAB: IF output_idle IF output_active * WDTD ASSERT: disable_driver_3 UNJAB WAIT:
*
!WDTD)
THEN UNJAB_WAIT THEN NO_OUTPUT % ASSERT WDT here %
% start_un j ab_timer % IF output_active * unjab_timer~not_done * !WDTD THE:N JAB IF unjab_timer_done + WDTD THEN NO_OUTPUT ASSERT: disable_driver_3 % ASSERT WDT here .% 292080-17
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AP-345
% ------------------------------------------------------- % MACHINE: LINK_INTEGRITY~FUNCTION CLOCK: TXCn CLEAR: RESET
STATES: IDLE TEST LINK TEST_FAlL_RESET LINK_TEST_FAIL LINK_TEST_FAIL_EXTEND ALIA ALIB ALIC ALID
LI 0 1 1 0 0 0 1 1
LIFOl 0 1 0 0 1 1 0 1
LIF02 0 0 0 1 1 0 1 1
] ] ] ] ] ] ] ] ]
start_link_loss_timer % start_link_test_min_timer % IF link_loss_timer_done.* !LID THEN LINK_TEST_FAIL_RESET %
%
LINK_TEST_FAIL_RESET:
LINK_TEST_FAIL:
IF link_test_rcvd * !LID * input_idle THEN LINK_TEST_FAIL IF input_active + LID THEN LINK TEST FAIL_EXTEND ASSERT: disable_receiver disable_driver_4
% start_link_test min timer % % start_link_test_max_timer % IF input_active + link_count_is_3 + LID THEN LINK_TEST_FAIL_EXTEND IF (link_test_max_timer_done + (link_test_min_timer_not_done * link_test_rcvd» * !LID * input_idle THEN LINK TEST FAIL RESET disable_receiver
LINK_TEST_FAIL_EXTEND:
ALIA: ALIB: ALIC: ALID:
IF input_idle * output_idle THEN IDLE_TEST ASSERT: disable_driver_4 disable_receiver
IDLE_TEST IDLE_TEST IDLE_TEST IDLE_TEST
. END$ 292080-18
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