Using Intel's ASIC Core Cell to Expand the Capabilities of an 80C51-Based System

MATT TOWNSEND CPO TECHNICAL MARKETING

MANAGER

inter Intel's new ASIC family of microcontroller core cells extends the capability of the MCS~-SI product, and allows the ASIC designer more flexibility than the popular microcontroller product. This note will discuss many of the new design possibilities inherent to the 80CSI cell-based controller. This family of cells is available with a variety of RAM and ROM configurations. Cell Name

ROM

UC51 00 UC5104 UC51 08 UC5116 UC5200 UC5204 UC5208 UC5216

No ROM 4KROM 8KROM 16K ROM No ROM 4KROM 8KROM 16K ROM

RAM 128 128 128 128 256 256 256 256

Bytes Bytes Bytes Bytes Bytes Bytes Bytes Bytes

RAM RAM RAM RAM RAM RAM RAM RAM

Other documentation will address Intel's ASIC design environment (see reference section). The 8OCSI-based,ASIC cell is part of a family of cellbased functions based on popular Intel standard products. Members of the 82Cxx microprocessor support peripheral family (SP82S4, SP8237, SP82S9, SP8284, SP82284, SP8288 and SP82288) are also available as library elements. The standard product ASIC cores are supported by a library of over ISOlogic.cells, representing a broad range of SSI, MSI, and I/O functions. Another class of cell library elements is designated Special Functions. These cells are predefined complex functions such as RAM, Serial I/O, AID Converter, and a Voltage Comparator. The Special Function and general logic element cells can also be used without a standard product core in the ASIC design. Any of the available 80CSI-based cores can be integrated with logic complexities up to SOOOgates.

Although the 80CSI-based core is functionally identical to the standard 80CSIBH microcontroller, its use as a cell in the ASIC library allows more flexibility in system design and partitioning. Figure I depicts the difference between the standard pinout of the MCS-Sl family and the ASIC core. In order to understand the enhancements (in an applications sense) made to the core it is useful to compare its connections to the pinout of the standard product. The MCS-Sl family embodies a very powerful architecture. While it was intended as a "single chip solution"

its addressing modes, clean bus interface, on-chip peripherals, and code efficient instruction set operations make it well suited to processor-like applications as well. For processor applications, a designer forgoes many of the "single chip" features in favor of the high performance CPU functions of this architecture. In order to fit the MCS-SI family microcontrollers into an economical forty lead DIP or forty-four lead PLCC package, Intel designed the standard product with many of the device's functions sharing pins. The microcontroller designer must compare necessary functions against the economics and performance required for a given design. If external memory or memory mapped I/O is required, then the use of the port 0 function is not available. If the memory address is beyond the 2S6 byte boundary defined by the ADO- 7 Bus then all or part of the port 2 function is not available. Likewise, using peripheral functions like the counter input pins, ~erial I/O, and interrupts eliminates port 3 functions. While the MCS-SI family is one of the most popular microcontrollers ever introduced, this shared functionality hinders its use in many applications. For example, a "fully loaded" MCS-Sl-based design would generally leave only one 8-bit port (port 1) for the application's I/O requirements. The standard cell version of the 80CSI provides the designer with 116 signals for connection to application specific logic. These signals represent the full function set of the MCS-Sl architecture and virtually eliminate any design trade-offs required to implement an application. Notice from Figure 1 that all of the I/O ports are separated from the other functions. In the design example, the I/O are separated into their respective inputs and outputs, leaving 32 inputs and 32 outputs for port connections into the application's logic. The most immediate impact of demultiplexing the I/O of the device is that much of the logic required to complete an application is eliminated. For example, when separating the address from the data on the AD-bus, an octal latch is required. For an 8OCSI-based core application, the designer uses the AO-7 bus directly, thus saving approximately 100 gates. The fact that the 8OCSI-based core has so many connections available does not mean an application will be forced into higher pin count packages. A 8OCSI-based ASIC can implement many system functions more economically than a discrete implementation. The design example illustrates a system with over 280 interconnects that can be integrated into one ASIC device. This application note will illustrate the less obvious ways in which the core can be used. The illustrations shown in this note are independent of the workstation platform used to implement the design. Intel provides the complete test vectors necessary to test the 8OCS1-based ASIC core, which have been derived from the standard product 80CSI test vector set.

inter P1.0

Vcc

Pl.l

Pl1.0ADII

PL2

PII.1ADI

P1.3

PII.2AD2

Pl.<4

PII.3AD3

PL5

PlUAD<4

PL6

Pll.5AD5

PL1 RST RXD P3.11 TXD P3.1 INTO P3.2 INTI P3.3

IP211-21 DP211-21

PII.6AD6

IPIII-11

EA

BOC51 BASED ASIC CORE

ALE PSEN P2.1A15 P2.6A1<4

TI P3.5

P2.5A13

WR P3.6

P2.<4AI2 P2.3A11

XTAL2

P2.2A111

XTALI

P2.1A9

VSS

DP311-31

PII.1AD1

Tll P3.<4

RD P3.1

IP311-31

P2.IIAB

RESET ERST CLK TICLK

240230-1 240230-2

RECONSTRUCTION PRODUCT 110

OF STANDARD

When designing the 8OC51-based ASIC core, Intel removed the pin multiplexers and I/O functions of the 8OC5l, and restructured them as companion cells. Companion cells allow the ASIC designer to reconfig-

ure the ASIC cell to function exactly like the standard product. Alternatively, the designer can choose to reconstruct a subset of the standard product I/O or select no reconstruction at all. Consult the references for more information about the use and function of Intel's companion cells.

inter Key to the 8OCSI's core-isolation test method is the ability to put the core into a condition that can verify the processor without the user's logic affecting the test. ERST is vital to controlling the ability to put the core based ASIC into test mode. It must be brought directly from the core to a package pin. Interface is via the PRESET companion cell. Because a dedicated reset pin may be restrictive in many applications, a second reset connection, RESET, has been included. Including this second reset connection allows the designer to simplify the overall ASIC design. Many applications require two sources of reset, usually a poweron-clear with a watchdog timer. Previously, the designer was faced with "ORing" an RC time constant circuit with the timer logic, resulting in an implementation which was not straightforward or cost effective. Figure 2 shows an 8OCSI-based ASIC implementation.

A system reset, in many designs, employs an active low logic level. Since the 8OCSI's reset requires an active high level, there is usually an inverter in the path to the microcontroller. It was mentioned earlier in this section that ERST must be brought directly from the core to a package pin. This is not entirely true; the inclusion of the inverter is allowed.

1/0 EXPANSION WITH THE 80C51-BASED CORE For the standard MCS-Sl product, the need for I/O expansion is often due to the need for external memory and/or port expansion. The designer's use of the onchip peripherals (eg. Serial I/O or Interrupts) often leaves only Port I intact.

BOCSl BASED ASIC CORE

WDT WATCHDOG TIMER WDT

ClK

OUT

WDT PRESET

OP""-"l P2

RESET

!L{>o_ ..! INVN (OPTIONAL)

D

inter 19 XTALl

P17 ~ P16 6 P15 5 P14 4 P13 3 P12 2 PIlI PH!

18 XTAL2

P27 P26 P25 P24

28 27 26 25 24 P23 23 P22 22

9 RST

8051 ~~~ 21 31

27 07 28 D6 29 05 30 04 31 03 32 02 33 01 34 00

P07 ~; P06 P05 P04 P03 P02 P01 P00

34 35 36 37 38 39

PSEN ;: A~

16

~ 17 RO 8255

PB7 PB6 PB5 PB4 P83 PB2 PBl PB0

Figure 3 depicts one case where the 8OC51can gain an expanded set of I/O ports. In addition to requiring additional package pins, this implementation would require more power supply capacity and passive components (bypass capacitors) than would be necessary if the I/O expansion were to be included on-chip with the microcontroller. Not only is PC board size decreased, but the overall system reliability increases with the ASIC solution. In addition, the 8255 port expander, being a highly flexible device, requires software to configure the device to the application. The simplest way to add I/O ports with the core is by way of a direct connection from the core's IP or OP signals through I/O functions selected from the cell library and connected to package pins. See Figure 4. In

25 24 23 22 21 20 19 18

this example, decoding is very simple and the component count is minimal.

80C51 BASED ASIC CORE

Figure 4. Direct Port Connections to ASIC Package Pins

.•.•.aa•••• __ aa•• a, __

•. _y •._.•_aa •.•••.•.•._

.•.•.•.•..••••.••.••.•. _ •..• aa •.••.•. _

I"

oa-..oaa

code efficient way to implement I/O with the core. Program code is composed of MOV operations rather than the MOVX needed for any Memory mapped I/O implementations. Logical operations to the port (ANL, ORL, XRL) can still be used. It is not necessary to update or maintain indirect pointers. Since quasi"bidirectional cells are not used, it is not necessary to set a "I" to the port in order to set these cells. Eliminating MOVX and port setup operations could result in significant codespace savings. The drawback to the direct approach is that program code written for the 8OC51using memory mapped I/O is not directly transportable to the core design. In most cases, however, implementing I/O expansion that allows code transportability is a simple task with a 8OC51-based ASIC. Most support peripherals are designed to be configurable for many different operating conditions. This is certainly true for a device like the 8255 as well; the port signals can be programmed as inputs, outputs, or bidirectional. In most applications the peripheral's setup is never changed after initialization. Port pins are set to either input, output or I/O. The peripheral's configuration is most often "set up" with data fields sent to a configuration or command register. This register is located at one of the peripheral's selectable addresses. For a cell-based implementation where code transportability is required, recreating an 8255-like function is straightforward. Since all setup information is written to one register and setup is not required because the port signal directions are fixed, that one register can

80C51 BASED ASIC CORE

~~

.••.•. __

•..• a.•.•..•••. _ •••.•••..•.•.•. ae_a

••...,

u •..•.•..•.•..•. u •.••..•••• _ •.••..•...• y .•••....•..•..•.•..•..•.

one 8-bit input port, and one 8-bit output port, both memory-mapped. Note that while the 8255 contains three 8-bit ports, an ASIC can be implemented with the exact amount of functionality desired. Implementing the full function set of the 8255 would result in an increased gate count (550 gates) included on the 8OC51-based ASIC. While 550 gates can easily be included on the same silicon chip, implementing the "exact functionality" version using elements from the cell library would consume only 100 gates.

In many designs, the built-in crystal oscillator of the 8OC5I is not utilized because the clock signal must be used for other system functions. However, the clock to the 8OC5I still must be generated and driven into the Xl/X2 pins. A clock generator is required somewhere in the system and is also used to clock many of the system functions surrounding the microcontroller. For 8OC51-based ASIC designs, all clocking functions, including the clock generator, can be brought on-chip. The advantages to doing so include enhanced reliability and a less costly, more noise free design. Clock generation is accomplished by the companion cell POSC (or POSC2 for frequencies between 16 MHz and 38 MHz) which can be used to drive the TICLK input connection to the core. The POSC output can be sent to user defined logic configured to generate other necessary

inter clocks in a system. Where the POSC cell fan out is high and might cause concerns about clock edge skew, a cell like BUF2 can be used. For systems where it is required that the signal be brought off-chip (formerly off-board), the on-chip generated clocks can be sent to output cells and on to package pins. Figure 6 depicts generation flexibility and clock source for a 8OC5l-based ASIC design.

In order for Automatic Test Equipment (ATE) to exercise the 8OC5l-based ASIC, the bus EADB must be brought directly to package pins. A specially designed I/O cell, PADB, must be directly connected to the EADB bus to ensure testability of the core as well as the user's logic.

Figure 6 illustrates a design which requires a high frequency clock to operate on a section of user-defined logic. For this, cell POSC2 is selected for the ASIC design and is set to 24 MHz. In order to meet clock specifications for the core, this 24 MHz master clock is divided down in order to provide the required 12 MHz. As discussed in the 8OC5l-based ASIC data sheet, the ATE must be able to drive the core's clock directly. For test modes, the ATE-generated clock is driven to the core's TICLK connection.

Requiring the EADB bus to appear as package pins does not impose any design restrictions on 8OC51-based ASICs designed to access external memory or peripherals. If your design does not call for the EADB to access external memory peripherals, the EADB may be multiplexed with user I/O. Contact your Intel Technology Center for the best implementation for your application. Intel supplies all test programs required to completely test the ASIC core cell. Designers are required to supply test vectors that exercise their unique logic only.

Note that signal P2 is shown being used for the application's clocks. It is sent to other logic in the ASIC and to a package pin as well.

6 •••Hz TO APPS

LOGIC

BUF2

BaCS1

BASED ASIC CORE TEST 2 •••• Hz TO APPS LOGIC

inter OBSERVING THE CONTENTS OF THE PROGRAM COUNTER The 8OC51-based ASIC core connections AO-AI5 always display the contents of the program counter (except in the case of MOVX instructions.) This feature allows another level of real time control by monitoring instruction events within the core. By attaching comparator circuitry to the program counter contents, signals can be generated to depict events within the program. Figure 7 shows such a circuit. The discussions in this note are not intended to be an exhaustive summary of the range of design possibilities available to the ASIC designer. Rather, it is hoped that it encourages the thought process toward even more innovative uses. The following is an example of an actual system problem and how it was resolved using a 80C51-based ASIC. The example utilizes many of the techniques discussed above.

Figure 8 shows a typical MCS-51-based design, which includes a port expander, timer/counter chip, a high speed event counter and a low-cost EPROM containing stable code. In this application, the 8031 controls a system based on numerous timed events. Many high speed clocks are involved, making for a potentially noisy environment, and a watchdog timer has been included to provide for soft recoveries if the microprocessor program flow is upset. The watchdog circuitry is shown as a high level block. The design must take an accurate sample of events designated at the EVENT input. The 16-bit count is read and processed under a timed interrupt designated by and generated from one of the 8254 Timers. The counter chain must be clocked at 24 MHz in order for unique and accurate event samples to occur. Another 8254 counter is programmed for single-shot mode to provide for a strobe window for some circuitry external to the PCB assembly. An 8-bit parallel data

80CS1 BASED ASIC CORE

UCS116 IN UPPER 8K

OF ROt.l

Figure 7. Signal which Designates when Program Execution Is In Upper 8K ROM input is required. The system must control peripherals external to this main assembly, resulting in a requirement for address decoder selection. Note that adequate bypass capacitors are required due to the clock speeds and the high number of pin connections. (There are 272 pins, not including the WDT and Oscillator Blocks.) A multilayer PCB is also required to compensate for the amount of wires needed to connect all the components. Figure 9 depicts the 8OC51-basedASIC solution for the design in Figure 8. Note that all of the circuitry in Figure 8 is included on a single ASIC chip. Rather than use memory-mapped I/O, the design has been converted to use the core's direct ports. Note that the 8255 function has been removed and instead the UC5116 port connections are used. Some minor software chan~es are required, and signals required to access off-chip program memory have been provided. This figure doc:s not show all test pin requirements; however, no additional package pins will be required. For this example, the designer could begin production runs with an EPROM. Once the application code stabilized, it could be developed and submitted to Intel for incorporation into the core. In this example, most of the high speed signals are contained within the ASIC, making the watchdog timer unnecessary. If needed, the overall cost of including it on the ASIC (= 500 gates) makes the functions relatively inexpensive to keep. Overall system pin requirements have decreased as well. This 8OC51-based ASIC can be produced using a 68-pin PLCC which may reduce the bypass capacitor requirements as well as the need for a multilayer PCB.

l'

PC7 PCS 11 PC! 12 PC4 13

PC3 17 PC2 IS PC1

15

pool'

Discrete Component

Count

Power Supply Current

1

3

1

Medium

High

Minimum PCB Layers System Reliability

80C51-ASIC

-25

-3A

-30

mA

Order Description Number 231816 - Introduction to Cell-Based Design 83002 - Cell-Based Design-Daisy Environment 83‫סס‬oo - Cell-Based Design-Mentor Environment 210918 - Embedded Controller Handbook 270535 -

CLK

IPO IPI

T1CLK

IP2

ERST

Embedded Control Applications

PERIPHERAL DATA INPUT

PARAL

OP3.X

RST rAoB UC5116

OP~

EXTERNAL SEL I

.0.15

EXTERNAL

EAL .0.0 PSENL

OP3/X

0

Al WRL

.0.0

ROL

.0.1

CLK2 GATE2

AoB

OUT2 SP8254

INTI

ClK1 GATE 1

WRL

OUll

SEL2