Using the 82750PD in an ATI/ISA Implementation
AL WEIDNER TECHNICAL MARKETING
ENGINEER
October 1993
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I
Order Number: 272366-001
3.0 COMPONENT
DESCRiPTION
3.1 Intel82750PD
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3.2 ATI68800DX
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3.3 ATI68890A 4.0 SCHEMATIC
ROAD MAP
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6.0 JUMPER DEFINITIONS
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7.0 CONNECTOR
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4.2 Sheet 1-ISA
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Bus Interface
4.11 Sheets 10 and 11-Resistors, Capacitors, and Header Pins 5.0 PAL EQUATIONS
4.1 Schematic Description 4.3 Sheet 2-Graphics BIOS ROMs
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Processor and
DEFINITIONS
8.0 SCHEMATICS
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9.0 BILL OF MATERIALS
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1.0 INTRODUCTION
1.2 Overview
The 82750PD Board is an ISA bus-based demonstration vehicle that, in addition to high performance graphics acceleration, includes real-time Indeof video capture/compression and accelerated video decompression/playback. This configuration and the associated software drivers fully supports Microsoft's Video for Windows" and Intel's Indeo Video 'Technology. The board's major components include:
This architecture allows each of the main components to be accessed by the host via the ISA bus. A common set of TTL butTers provides a multiplexed interface to the ISA bus. The components, in turn, interface to the shared local memory via the Shared Frame ButTer In.terconnect (SFBI). The local memory is a combination of VRAM and DRAM. The VRAM portion makes up the normal graphics frame butTer from which all graphics and video information is displayed, while the DRAM is used for video data butTering, working storage and microcode associated with the 82750PD video processor's compression and decompression algorithms. This design may be considered a "single frame butTer" in that both the graphics and video data are displayed through a single RGB format contained in graphic VRAM.
Intel 82750PD Video Processor ATI 68800DX Graphics Controller ATI 68890A Video Capture Controller 4 MB VRAM (max) 4 MB DRAM (max) This material is intended purely as a reference, not as a production ready design. The design includes component options (PLL vs oscillators, individual component reset jumpers/ etc.), that are useful for evaluation but would not normally be implemented in a production subsystem. The intent is that this be the basis for a fully productized design. Future designs which implement ditTerent host buses, contain enhanced functionality and are geared more toward production readiness will be provided as they become available.
1.1 Block Diagram
This board supports three distinct yet related functions: graphics processing/acceleration handled by the 68800DX, video data capture handled by the 68890A and real-time Indeo video data compression/decompression perfofIIl;edby the 82750PD. In the case of graphics operations, the normal data flow is from the host, through the 68800DX, to the VRAM frame butTer for display. For video playback, the, compressed frame is moved into the DRAM memory by the host, where it is decompressed by the 82750PD, then converted and scaled into the VRAM display butTer by the 68800DX.
Below is the basic block diagram of the board.
VRAM
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DAC 1----
RGB OUT
DRAM
VIDEO IN---i
ISA BUS 272366-1 NOTE: 1. SynchroLink
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is a trademark
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Inc.
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In video capture, the uncompressed video image is stored in ORAM by the 68890A, reformatted by the 688000X for display, while also being compressed in real-time by the 82750PO. The compressed video data is then read by the host for storage. This architecture provides a way to deal with video data so only low bandwidth, compressed data needtravel on the ISA bus. The movement of the raw, uncompressed video data is limited to the high speed SFBI. The following two diagrams provide data flow for playback and capture.
2.0 COMMON INTERFACES Integral in this architecture are three interconnects that are common to the main components: the Universal Host Bus Interface, the Shared Frame Buffer Interconnect and the SynchroLink' bus.
municate on system bus. This interface reduces the number of signals required to attach to the ISA bus from 56 to 44 by multiplexing SA[J5:0] with SO[15:0]. This multiplexed bus normally "passes" the address portion of the ISA bus so each device can "watch" for accesses to its unique address spaces. Using four common control signals, the device being accessed will "switch" the bus from address to data while controlling the "direction" of the data based on the type of ISA cycle (read or write). Although this specific implementation is ISA bus based, the Universal Host Bus Interface has been designed so it may be configured to support ISA, EISA, Micro Channel, PCI or VL-Bus.
2.2 Shared Frame Buffer Interconnect (SFBI) The SFBI provides a way for the major components to access the shared memory. Software provides the memory management mechanism to insure one device does not corrupt the other device's memory areas. The scheme
2.1 Universal Host Bus Interface (UHBI)
aJlows large amounts of data to be shared between devices by merely passing pointers.
The Universal Host Bus Interface is the common connection used by each of the main components to comData Flow-Playback On-Screen Memory
Off-$creen Memory CORAM) Per Stream
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The SFBI is a high-speed (200 Mb/sec) 32/64-bit wide bus that supports a combination of DRAM and VRAM. The specification includes the definition of a three-signal arbitration interface. The board uses a 22VlO PLD to provide that arbitration function. Once having been granted the SFBI, a device has full control of the RAS, CAS, WE, OE, address and data buses of the memory array. In this implementation, the 68800DX is responsible for generating the transfer cycles to VRAM as well as the memory refresh cycles to the entire array.
2.3 SynchroLink* Bus The SynchroLink bus is a bit-serial bus that is designated to facilitate synchronization between devices in the subsystem. The SynchroLink supports eight devices where one device, the arbiter, sources the 8 MHz clock and is responsible for issuing "invitations" to each device on the bus. When accepting an invitation, a device can send a "service request" message, a "service complete" message or one of many "broadcast" type messages.
Note that the SFBI is intended to provide access to memory and not communication between devices. The specification defines the memory signais and mapping so that each device has the same view of the memory space. This, however, does not restrict the use of signals on the SFBI. Once granted the bus, the master may use the signals in any way that would not interfere with the other devices or their memory. The configuration EEPROM is an example (see Section 5.9).
The typical utilization of the SynchroLink on this board involves:
See the Shared Frame Buffer Interconnect Specification for complete details.
The use of the SynchroLink for other functions is likely in the future. Audio synchronization, single point
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• receiving messages from the 82750PD indicating a frame of uncompressed data is available for display • signaiing from the 68890A indicating a frame ofvideo data is available to the 82750PD to compress and/or the 68800DX to display • etc.
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IS..! ~ut'u IS a derivative of the Intel 82750PB. It is a programmable video processor that supports a wide range of compression algorithms. Here, it operates in conjunction with the ATI 68800DX graphics controller to provide acceleration of video decompression! playback and with the AT! 68890A video capture chip to provide real-time Indeo video compression. The host resident driver is responsible for uncompressed data movement and for loading the appropriate microcode routines in the shared memory from which the 82750PD executes. The 82750PD provides host access to its internal registers and to the shared memory through both EMS-like memory accesses and indirect I/O space accesses.
Some of the internal features of the 82750PD include: 25 MHz single cycle execution unit, 512 x 48 instruction RAM, 16-bit ALU, dual 16-bit internal bus architecture, and a pixel interpolator. See the Intel 82750PD Video Processor Data Sheet, Order No. 272341-001, and the 82750PD Programmer's Reference Manual, Order No. 272352-001, for complete details.
See the AT! 68890 Data Sheet for complete details.
4.0 SCHEMATIC ROAD MAP The schematics provided in Section 9.0 of this document were generated with OeCad" and are described in Section 5.0. These schematics are currently available as paper copy in this document or electronically in OrCad format.
. 4.1 Schematic Description Below is a table of the schematic sections and page references. Schematic Sheet 1
2 3 4
3.2 ATI68800DX
5 6
The AT! 68800DX is a high performance graphics controller designed specifically for high resolution graphics and multimedia applications. The 68800DX includes VGA and 8514/ A compatibility, 1280 x 1024 x 32 bit color, graphics drawing engine, H/W cursor, and linear addressing. Additionally, the 68800DX supports colorspace conversion and scaling in support of the video acceleration.
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Function ISA Bus Interface 68800DX Graphics Controller and BIOS ROM 82750PD Video Processor 68890A Capture Controller Memory Banks 1 and 2-VRAM Memory Banks 3 and 4-DRAM 68860 Display Interface, Feature Connector Video In, AID Converters and Line Buffer Chip Clock Generation, Arbiter and Configuration ROM Pull-ups and Capacitors Test Point Headers
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4.2 Sheet 1-ISA Bus Interface Four TIL buffers and associated control signals are used to form the 16-bit multiplexed host bus AD[15:0]. The address lines, SA[15:0], are buffered through two 74ALS245s that are normally enabled (DIS--...ADR# = High), while the data lines, SD[15:0], are buffered through two 74ALS245s that are normally disabled (EN-DBO# and EN-DBI # = High). Each device monitors LA[23:l7], SAI6, AD[15:0], BALE and the command strobes (IOR #, IOW #, MEMR # and MEMW #) to detect an access to its memory or I/O space. The selected device pulls DIS~DR # low, turning off the address buffers, and enables the byte-wide data bus transceivers by pulling EN_DBO# and/or EN_DB I # low. The data direction control (DIR) is set depending on whether the access is a read or write. Each device is also responsible for controlling NOWS#, 10CHRDY, MEMCSl6#, and IOCS16# for its particular accesses.
4.3 Sheet 2-Graphlcs Processor and
This page of the schematics refers to the capture controller. It also includes the series termination resistors for the RAM address and control signals and a set of jumpers that allow different VRAM/DRAM configurations.
4.6 Sheet 5-VRAM The design allows for two banks of VRAM. Each bank is implemented using four 256K x 16 parts. The address, control and parallel port of the VRAM make up its interface to the SFBI. The 68800DX is responsible for generating the transfer cycles while the serial port data accesses are controlled by the 68860 DAC and provides the pixel data path to the DAC.
4.7 Sheet 6-DRAM The remaining memory on the board is made up of two banks of DRAM. Again, 256K x 16 parts are used to provide up to 4MB of DRAM memory. The DRAM area is used mainly as microcode RAM, video data buffers, and working storage for the 82750PD video processor and the 68890A capture controller.
BIOS ROMs The 68800DX interfaces to the UHBI, the SFBI, and the SynchroLink along with a set of control signals for the DAC. It also provides the output enables for the BIOS ROMs. The ROMs are addressed by CK[4:l] generated by the 68800DX and the ISA bus address lines SA[l1:l]. The data outputs of the ROMs are tied to AD[15:0] of the UHBI, which provides the path directly to the ISA bus and to the 68800DX. The ROM must be implemented as l6-bit wide even though the subsystem supports a configuration that appears to be 8-bit to the host. In this case, the 68800DX handles the routing of the data from the high order to low order of the AD bus and onto SD[7:0].
4.4 Sheet 3-Vldeo Processor The 82750PD attaches to the UHBI, the SFBI, and the SynchroLink. It utilizes the shared memory for all its off-chip activities and microcode storage and the SynchroLink for "signaling" between components.
4.5 Sheet 4-Capture Controller The 68890A capture controller attaches to the UHBI, the SFBI, and the SynchroLink along with a set of control signals for the AID converters and the line buffer chip.
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4.8 Sheet 7-DAC, Analog Output and Feature Connector The 68860 DAC provides direct analog RGB output to 11, a standard l5-pin VGA connector. The DAC requires a separate analog voltage supply, which is provided by a TL43lCD regulator. The schematic includes a second regulator which is needed only with revision A of the DAC. JU5, JU6, and JU7 are available so that the DAC may be upgraded to a newer version without requiring other parts to be added or removed. U24, 74LS15l, allows the 68800DX to read the monitor type from the connector. The 68800DX and the DAC support a VGA passthrough port for VGA compatibility mode operation. An 8-bit data bus P[7:0] provides this path and provide the data for the VGA feature connector. JU8, JU9, and JUW allow this port to be configured as VGA compatible or as an output-only port.
4.9 Sheet 8-Video Input and A-D Section Analog video data from composite or s- VHS sources is converted to digital through two Phillips video analog input chips. U33 (TDA8708) is used for composite video from inputs J4 or J5. Both U33 and U34 (TDA8709) are used when the S-VHS input JU3 is used. The data
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from these devices is read by the 68890A via DADC[7:0]. A Sony CXK1209Q digital delay line is used by the 68890A as a "line buffer" to save previously captured video. DDAC[7:0] provides the path from the 68890A to the CXK1209 while it is read through the same path as the AID converters.
JU5,6,7JU5 1- 2 open
JU6 1- 2 open
JU8,9,10-
4.10 Sheet 9-Clock Generation, SFBI Arbiter and Miscellaneous Two different PLLs and four discrete oscillators have been included to promote ease of testing and evaluations. The oscillators are used for fixed mode testing, while the PLLs provide the programmability required for multiple operating modes. U26 (22VIO) is programmed as the SFBI arbiter. In order to allow the SFBI to operate at 50 MHz, U68 (74F174) is used to sample the state of the SFBI request signals from the 68800DX, the 82750PD, and the 68890A. A second PAL, U49, is used to combine the interrupt requests from each device and drive the ISA bus IRQ. The equations for these devices appear in Section 6. A serial EEPROM (D37) is used by the 68800DX to store setup and configuration information. This is an example of a non-memory use of the SFBI. SFBI data bits MD[34:32] are used along with a chip select to transfer information.
JU8 1- 2 2- 3
Feature Connector Configuration JU7 1- 2 open
68860 Rev. 1 68860 Rev. 1 +
Feature Connector Configuration
JU9 1- 2 2- 3
JU11,12,13 -
JU10 1 - 2 VGA Compatibility Mode 2 - 3 Output Only Mode Memory Configuration
JU11 JU12 JU13 Bank 1 plus None 1 - 2 open open Bank 2 open 1 - 2 open Bank 3 open open 1 - 2 Bank 4 1 - 2 3 - 4 open Banks 2 and 3 1 - 2 open 3 - 4 Banks 2 and 4 open 1 - 2 3 - 4 Banks 3 and 4 1 - 2 3 - 4 5 - 6 Banks 2 and 3 and 4 JU15-Test JU15 open Test only - removes MCLK 1 - 2 Normal JU16 - 68860 Reset
4.11 Sheets 10 and 11-Resistors, Capacitors, and Header Pins The last two pages of the schematic contain pull-up resistors, by-pass capacitors and a set of header pins to allow easy probing of signals.
5.0 PAL EQUATIONS TBD
JU16 1 - 2 Hold 68860 in Reset 2 - 3 Resets the 68860 with ISA bus reset JU17 - OSC Source JU17 1 - 2 OSC from PLL 2 - 3 OSC from Oscillator JU18 - 68800DX Reset
6.0 JUMPER DEFINITIONS Jumper definitions are as follows: JU1 -ISA JU1 1-2 3-4 5-6
7-8 9 -10
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JU18 1 - 2 Hold 68800DX in Reset 2 - 3 Resets the 68800DX with ISA bus reset
Interrupt Level Selection
IRQ9 IRQ3 IRQ5 IRQ10 IRQ13 1-349
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JU22 -
82750PD Reset
JU22
1- 2 2- 3 JU23 -
Connector definitions are as follows: Hold 82750PD in Reset Resets the 82750PD with ISA bus reset 68890A Reset
JU23
1- 2 2- 3 JU24 -
Hold 68890 in Reset Resets the 68890A with ISA bus reset 68860 Reset
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7.0 CONNECTOR DEFINITIONS
Hold 68860 in Reset Resets the 68860 with ISA bus reset
J 1 - VGA Monitor -
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-
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8.0 SCHEMATICS The schematics provided in the following pages were generated with OrCad and are described in Section 5.0. These schematics are currently available as paper copy in this document or electronically in OrCad format.
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AP-491
1-361
5
6
C1,C2,C3,C4,C5,C6
Capacitor, 220 pF, NU
6
7
C7, C20,C21,
Capacitor, 470 pF
7
11
C25,C26,C27,C28
ce, C10,
C11, C105, C106, C112, C113, C114, C115, C116, C117
Capacitor, 0.01 ,...F
C12,C107,C120,C121,C126,C144,C148
Capacitor, Tantalum, 22 ,...F, 16V
C16,C34,C35,C36,C37,C38,C39,C40,C41,C42, C43,C44,C45,C46,C47,C48,C49,C50,C51,C52, C53, C54, C55, C56, C57, C58, C59, C60, C61 , C62, C63,C64,C65,C66,C67,C68,C69,C70,C71,C72, C73, C74, C75, C76, C77, C79, C80, C81, C82, ces, C84,C86,C87,C88,C89,C90,C91,C92,C93,C94, C95,C96,C97,C98,C99,C100,C101,C102,C103, C119,C122,C127,C143,C146,C147,C149,U150, C152
Capacitor, 0.1 ,...F
8
7
9
78
10
6
C17,C18,C19,C22,C23,C24
Capacitor, 470 pF, NU
11
5
C29,C30,C31,C32,C33
Capacitor, Tantalum,
12
10
C108,C109,C132,C133,C135,C136,C138,C139, C141, C142
Capacitor, ,...F,NU
13
2
C125, C110
Capacitor, 0.001 ,...F
14
1
C111
Capacitor, 22 ,...F, 16V
15
3
C123, C128, C153
Capacitor, 30 pF
16
2
C124, C129
Capacitor, 20 pF
17
2
C130,C145
Capacitor, 1 ,...F
18
1
C151
Capacitor, 0.22 ,...F
19
3
01,02,03
Diode BAT54S
20
1
21
4
04 EC__ O,EC __C,EC __ B,EC--A
Edge Card Fingers
22
1
JU1
Header2X5
23
9
JU5, JU6, JU7, JU11, J15, JU19, JU20, JU26, JU27
Header 2X1 Header3X1
JU16,JU17,JU18,JU22,JU23,JU24
10,...F
1N751
24
9
JU8,JU9,JU10,
25
1
JU12
26
1
JU13
Header3X2
27
1
J1
Connector
28
1
J2
Header 13X2
Header2X2 OB15
29
1
J3
4 Connector,
30
2
J5,J4
RCA Jack, PC Mount, RT-Angle
31
6
J6,J7,J8,J9,J10,J11
Header 26X2
32
1
MMY2
TTL
1-362
osc,
S-VHS, Female
14 DIP, 35.46895 MHz, NU
I
infel~ 9.0 Item
AP-491
BILL OF MATERIALS
(Continued)
Quantity
Part
Reference
1
MMY3
TIL OSC, 14 DIP, 28.63636 MHz, NU
34
1
MMY4
TIL OSC, 14 DIP, 40 MHz, NU
35
2
REG2, REG1
TL431CD
36
1
REG3
LM7805,
37
6
RP5, RP6, RP10, RP11 , RP13, RP18
SIP Resistor, 15Kx9, Parallel
38
2'
RP14, RP15
SIP Resistor, 1Kx9, Parallel
39
7
RX1,RX2,R16,R17,R18,R19,R103
Resistor, 15K, %W, 10%
40
39
R1, R2, R3, R4, R5, R7, R8, R9, R10, R11, R12, R13,R14,R15,R27,R28,R30,R31,R32,R33, R43,R44,R45,R54,R55,R56,R57,R58,R59, R60,R61,R62,R63,R64,R65,R66,R93,R94, R95
RESISTOR, 33, %W,10%
41
13
R20, R21 ,R22, R23, R24, R25, R51, R52, R53, R74,R75,R76,R77
Resistor, 75, %W, 10%
42
1
R26
Resistor, 360, %W, 10%
43
1
R34
Resistor, 1370, %W, 5%
44
1
R35
Resistor, 160, %W, 10%
45
2
R46,R36
Resistor, 240, %W, 10%
46
1
R37
Resistor, 660, %W, 10%
47
1
R38
Resistor, 470, %W, 10%
48
5
R39,R40,R100,R101,R102
Resistor, 2K, %W, 10%
49
5
R47,R48,R49,R50,R70
Resistor, 100, %W, 10%
50
4
R67,R80,R81,R82
Resistor, 4.7K, %W, 10%
51
4
R68, R69, R71, R72
Resistor, 750, %W, 10%
52
1
R73
Resistor, 330, %W, 10%
53
2
R78, R79
Resistor, 10K, %W, 10%
54
6
TP1,TP2,TP3,TP4,TP5,TP6
Test Point
33
+ 5V REG,
T0220
55
8
U1,U2,U3,U4,U5,U6,U7,U8
256X16 VRAM -70 (SOJ)
56
8
U9,U10,U11,U12,U13,U14,U15,U16
256X16 DRAM -70 (ZIP)
57
1
U17
68800DXI
58
1
U18
68890A
59
1
U19
82750PDI
60
1
U22
CXK1202Q
61
1
U23
68860_DAC
62
1
U24
74LS151
63
1
U25
AT118811-1
64
2
U27, U26
27256-250
65
1
U28
22V10-10 DIP
66
4
U29, U30, U31, U32
74ALS245
67
1
U33
TDA8708
68
1
U34
TDA8709
69
2
U35,U36
74ALS374
70
1
U37
93C56 SERIAL EEPROM
71
2
U38,U40
74LS04
72
1
U39
74FOO
I
-,
\
1-363
intel~
AP-491
9.0 Item 73 74 75 76 77 78 79 80
1-364
BILL OF MATERIALS (Continued) , Quantity 1 1 1 1
Reference
1
Y1
1
Y2
Part 16R8-25 PLCC 74F174 74LS174 ICD2061 XTAL, 14.318 MHz TTL OSC, 8-Pin DIP, 35.46895 MHz
1 1
Y3 Y4
TTL OSC, 8-Pin DIP, 28.63636 MHz TTL OSC, 8-Pin DIP, 40 MHz
U49 U58 U59 U60
I
