APPENDIX for LABORATORY 3 SHEET

APPENDIX A The JTAGICE mk II AVR debugger The AVR JTAGICE mklI from Atmel is a development tool for On-chip Debugging of all AVR 8-bit RISC microcontrollers with IEEE 1149.1 compliant JTAG interface or debugWIRE Interface. DebugWIRE enables on chip debug of AVR microcontrollers in small pin count packages, using only a single wire for the debug interface. The JTAGICE mkII and the AVR Studio user inter-face give the user complete control of the internal resources of the microcontroller thus making hardware debugging easier. The JTAGICE mkII performs Real Time emulation of the microcontroller while it is running in a target system.

Figure A.1: JTAGICE mklI Device and its JTAG connector, USB port and USB cable

1

APPENDIX for LABORATORY 3 SHEET A.1.

The ATmega32A Target board

JP2

JTAG Connector Connector Move jumpers from JP2 to JP1 if JP1 not jumpered

Push Buttons Panel

LED Panel

JP1 Interrupt pins

Pushbutton panel

LED panel Figure A.2: ATmega32A target board and its JTAG Connector, LED panel, pushbuttons panel locations and External Interrupt pins panel.

2

APPENDIX for LABORATORY 3 SHEET A.2.

The connections of LED and Pushbuttons panels in the ATmega32A Target Board

ATmega32A

Figure A.3: Wiring of LED and Pushbuttons panels to ATmega32A (shown by the pins labels). Note: Both input and output device are connected to PORTB

3

APPENDIX for LABORATORY 3 SHEET A.3.

Connecting AVR Studio to the JTAGICE mk II

In this Laboratory (Laboratory 3) you will be using the Atmega32A chip (on the Atmega32A target board) to run an Atmega32A program. The JTAGICE mk II will be the interface between AVR Studio IDE and the Atmega32A target board. To connect PC running AVR studio to the JTAGICE mk II, the following is the procedures. 1. Connect the USB cable from the Windows system USB port to the Atmega32A target board USBPOWER connector. If the board power is ON, switch it OFF (very important) by toggling the POWERSW button. 2. Connect the USB cable from the Windows system USB port to the JTAGICE mk II (USB connector). If the JTAGICE mk II power is ON, switch it OFF (very important).

To connect to the JTAGICE mk II to the ATmega32A Target Board, the following is the procedures. 3. Connect the 10 pin DIP connecter from JTAGICE mk II to the JTAG connector on the Atmega32A target board. 4. Switch ON JTAGICE mk II first before switching ON the Atmega32A target board.

Note: When switching OFF you must OFF the Atmega32A target first before switching OFF the JTAGICE mk II power to avoid damage to the JTAGICE mk II. A switched OFF JTAGICE mk II must never be JTAG connected switched ON Atmega32A target board. Only the JTAGICE mk II can on ON if connected to a switched OFF Atmega32 target. 5. If you are opening a new AVR studio project (as shown in Appendix A of Laboratory 1 sheet, in the Welcome to AVR Studio window, as shown below, instead of selecting AVR Simulator select JTAGICE mk II as the debug platform and Atmega32A as the device and click Finish

4

APPENDIX for LABORATORY 3 SHEET 6. If the JTAGICE mk II is connected you will see the JTAGICE mk II word (in grey) at the bottom of theAVR studio Window as shown below, when it is opened.

If you debugging (running) a program built on AVR studio IDE which is connected to JTAGICE mk II, the “JTAGICE mk II” will be in bold. ci 7. In case where you have open a previous project which uses the AVR Simulator as the Debug Platform, or the JTAGICE mk II is disconnected (USB cable removed or powered OFF), you can connect AVR studio to the JTAGICE mk II by selecting Debug|Select Device and Debug Platform and select JTAGICE mk II and Atmega32A as shown below anf Click Finish, if you have not done so.

Note:

5

APPENDIX for LABORATORY 3 SHEET 1. When you have selected JTAGICE mkII and ATmega32A, when a “Built and Run” command is executed codes will be uploaded to the ATmega32A chip on the ATmega32A target Board via the JTAGICE mkII debugger (Assuming JTAGICE mkII debugger and ATmega32A Target Board is already connected correctly). 2. AVR Studio communicates to the JTAGICE mkII debugger through the USB cable. 3. JTAGICE mkII debugger communicates to the ATmega32A target Board through the JTAG cable. To Check the Running Frequency of the ATmegea32 chip on the ATmega32 target Board 1. Make sure you are not in Debugging mode. To confirm his select “Debug|Stop Debugging” menu. 2. Make you that the JTAGICE mkII and ATmega32A Target Board are correctly connected to AVR studio (refer above steps). 3. Select “Tools|Program AVR|Auto Connect” menu and the following window will open.

4. Select the Fuse Tab and check the SUT_CKSEL which states that the Clock Source is 1MHz. This information is need for delay calculation in timers ins section A.8. 5. If the setting display on your PC is not the same, you may change appropriately and click “Program” button. 6

APPENDIX for LABORATORY 3 SHEET

7

APPENDIX for LABORATORY 3 SHEET A.4.

Interrupts.

Any reasonable microprocessor system must have several external devices connected to it and must be able to communicate with these devices. All of these devices must have some sort of AVAILABLE signal telling the microprocessor that data is available for it or that it is available for use. There are two methods for a microprocessor to communicate with external devices: Polling and interrupts. Polling is the act of periodically querying the AVAILABLE lines on all the input devices to see if data is available. The disadvantage of polling is that the polling routine must be entered periodically (very often if high speed data is coming through) and there may be too little time for the microprocessor to execute its program. You have done this in Laboratory 2 experiment. Interrupts is an alternative, more efficient method of communication. Here, when the I/O device has data for the microprocessor or requires some other service it issues an interrupt request. An interrupt request can come at any time during the execution of a program and generally comes while the microprocessor is executing an instruction. The following figure shows the microprocessor executing its main program when an interrupt request occurs.

Interrupts are basically events that require immediate attention by the microcontroller. When an interrupt event occurs the microcontroller pause its current task and attend to the interrupt by executing an Interrupt Service Routine (ISR) at the end of the ISR the microcontroller returns to the task it had pause and continue its normal operations (executed by the RTI instruction). In order for the microcontroller to respond to an interrupt event the interrupt feature of the microcontroller must be enabled along with the specific interrupt. This is done by setting the Global Interrupt Enabled bit and the Interrupt Enable bit of the specific interrupt.

8

APPENDIX for LABORATORY 3 SHEET Interrupt vector table An interrupt vector table, a concept common across various processor architectures, is a table of interrupt vectors that associates an Interrupt Service Routine (interrupt handler) with an interrupt request. Interrupt Service Routine or Interrupt Handler An Interrupt Service Routine (ISR) or Interrupt Handler is a piece of code that should be executed when an interrupt is triggered. Usually each enabled interrupt has its own ISR. In AVR assembly language each ISR MUST end with the RETI instruction which indicates the end of the ISR. Interrupt Flags and Enabled bits Each interrupt is associated with two (2) bits, an Interrupt Flag Bit and an Interrupt Enabled Bit. These bits are located in the I/O registers associated with the specific interrupt:  

The interrupt flag bit is set whenever the interrupt event occur, whether or not the interrupt is enabled. The interrupt enabled bit is used to enable or disable a specific interrupt. Basically is tells the microcontroller whether or not it should respond to the interrupt if it is triggered.

In summary basically both the Interrupt Flag and the Interrupt Enabled are required for an interrupt request to be generated as shown in the figure A.5 (1).

Figure A.5 (1): Hardware implementation on External Interrupt in ATmega32 (ATmega32A) Global Interrupt Enabled Bit Apart from the enabled bits for the specific interrupts the global interrupt enabled bit MUST be enabled for interrupts to be activated in the microcontroller. For the AVR 8-bits microcontroller this bit is located in the Status I/O Register (SREG). The Global Interrupt Enabled is bit 7, the I bit, in the SREG.

9

APPENDIX for LABORATORY 3 SHEET Interrupt Request sources provided with the AVR microcontroller The AVR 8-bits microcontroller provide both internal and external interrupt sources. The internal interrupts are associated with the microcontroller's peripherals. That is the Timer/Counter, Analog Comparator, etc. The external interrupts are triggered via external pins. The figure A.5 (2) shows the pins, on which the external interrupts can be triggered, for an AVR 8-bit microcontroller. When an Interrupt is triggered, the CPU will execute the its service routine whose starting address is defined in the Interrupt vector table. On ATmega32/ATmega32A microcontroller there are four (4) external interrupts: 1. The RESET interrupt - Triggered from pin 9 (executed like an interrupt but does not operate as an interrupt because RETI instruction cannot be used in RESET “Interrupt service routine”. 2. External Interrupt 0 (INT0) - Triggered from pin 16. 3. External Interrupt 1 (INT1) - Triggered from pin 17. 4. External Interrupt 2 (INT2) - Triggered from pin 3.

Figure A.5 (2): Location of External Interrupt pins in ATmega32/ATmega32A

10

APPENDIX for LABORATORY 3 SHEET Important Notes: As it relates to AVR microcontrollers - An interrupt vector is the program memory address of an interrupt service routine (interrupt handler). The interrupt vector for each interrupt provided by the AVR microcontrollers can be found in its datasheet. The table A.5 (3) is an extract from the section of the ATMega32 datasheet that shows the interrupt vector table that identify the interrupt vectors (address of respective ISR) for the interrupts provided with this microcontroller (ATMega32/ ATMega32A). Please note here that the memory location for interrupt vector table which should be reserved for storing pointers to interrupt handlers (ISR) are not used to store regular programs code. For ATmega32/ ATMega32A should not use address below 0x2A i.e. the vector interrupt table memory area.

11

APPENDIX for LABORATORY 3 SHEET

Very Important When writing assembly codes for ATmega32A utilizing the interrupt feature the following MUST be observed:   



 

The interrupt MUST be enabled by setting its enabled bit in the appropriate I/O register i.e. the General Interrupt Control Register (GICR). The Global Interrupt bit, the I bit, in the microcontroller's status register (SREG) MUST also be enabled by using the SEI instruction. The stack MUST be initialized (Normally at the beginning of the program). When an interrupt is being service the microcontroller needs to store critical information on the stack and so it must be initialized. The Triggering Condition (in MCUCR for INT0 and INT1 and in MCUSCR for INT2) must be specifically set to suit hardware wiring configuration of the interrupt pin. Switch ON internal pull-up resistor if external pull-up resistor is not wired for active low interrupt input. The Interrupt Service Routine (ISR) MUST end with the RETI instruction, which indicates the end of the ISR. The microcontroller needs to know when it reaches the end of the ISR so it can return to its previous task. Note A.5(1)

Steps taken in servicing an interrupt Upon the triggering of an interrupt the following sequence is followed by the microcontroller providing that the both the specific interrupt and global interrupts are enabled in the microcontroller: 1. The microcontroller completes the execution of the current instruction, clears the I bit and stores the address of the next instruction that should have been executed (the content of the PC) on the stack. 2. The interrupt vector of the triggered interrupt is then loaded in the PC and the microcontroller starts execution from that point up until it reaches a RETI instruction. 3. All registers used in the interrupt service (unless the registers are as output parameter) and SREG must be saved upon entry and restored before executing RETI instruction. 4. Upon the execution of the RETI instruction the address that was stored on the stack in step 1 is reloaded in the PC and the I bit is re-enabled. 5. The microcontroller then starts executing instructions from that point. That is the point that it left off when the interrupt was triggered. Note A.5(2)

12

APPENDIX for LABORATORY 3 SHEET

Figure A.5 (3): Interrupt vector Table reserved in Program Memory for ATmega32 (ATmega32A) A.5.

Programming ATMEga32/ATMEga32A External Interrupts.

A common task in embedded programming is checking when the state of pin has changed. You can write software to poll a pin's state. You have done this in Laboratory 2 experiment. In this Laboratory 3 experiment you will set up interrupt. An interrupt can be used to notify your program when a pin state has changed. The following example will show how to use external interrupts. 1. The ATMEga32/ATMEga32A External Interrupts Pins. Use the data sheet to find out which pins can be used as external interrupts. In page 2 of file “ATmega32A datasheet.pdf” shown in figure A.5, note the INT2, INT1 and INT3. These pin can be programmed to generate external interrupt for the ATmega32A (ATmega32).

13

APPENDIX for LABORATORY 3 SHEET

Figure A.6: Pin Configurations - Pin out of ATmega32A chip The interrupts can detect four different types of pin changes: 1. 2. 3. 4.

pin goes low any logical change in pin falling edge (pin goes from high to low) rising edge (pin goes from low to high)

14

APPENDIX for LABORATORY 3 SHEET 2. The ATMEga32/ATMEga32A External Interrupts Registers. As mentioned above, the hardware interrupt sources of ATmega32 are   

INT0 INT1 INT2

Referring to pp. 66 thru 68 of “8-bit Microcontroller with 32KBytes In-System Programmable Flash Reference Manual.pdf” these interrupts are controlled by the following registers.    

GICR GIFR MCUCR MCUCSR

3. General Interrupt Control Register (GICR):

INT1: When this bit is ‘1’ and global interrupt bit in SREG is ‘1’ (i.e. I bit) the External Interrupt 1 is enabled. The ISC11 and ISC10 of MCUCR register control the interrupt when to be activated (i.e. on rising edge or falling edge or level sensed). INT0: When this bit is ‘1’ and global interrupt bit in SREG is ‘1’ (i.e. I bit) the External Interrupt 0 is enabled. The ISC01 and ISC00 of MCUCR register control the interrupt when to be activated (i.e. on rising edge or falling edge or level sensed). INT2: When this bit is ‘1’ and global interrupt bit in SREG is ‘1’ (i.e. I bit) the External Interrupt 2 is enabled. ISC2 bit of MCUCSR register control the interrupt when to be activated (i.e. on rising edge or falling edge). 4. General Interrupt Flag Register (GIFR):

INTF1: When ‘1’ on this bit trigger INT1 Interrupt when INT1 bit of GICR and I bit of SREG is one. INTF0: When ‘1’ on this bit trigger INT0 Interrupt when INT0 bit of GICR and I bit of SREG is one. INTF2: When ‘1’ on this bit trigger INT2 Interrupt when INT2 bit of GICR and I bit of SREG is one. 15

APPENDIX for LABORATORY 3 SHEET 5. MCU Control Register (MCUCR):

ISC11:10: These bits control the INT1 interrupt trigger condition.

ISC01:00: These bits control the INT0 interrupt trigger condition.

MCU Control and Status Register (MCUCSR):

ISC2: This bit controls the INT2 interrupt trigger condition. If ISC2 is set to logical 0, the interrupt is detected on falling edge. If ISC2 is set to logical 1, the interrupt is detected on rise edge. A.6.

Internal Pull-up resistors for the ATmega32/ ATmega32A Input/Output port. All Input/Output port pins have individually selectable pull-up resistors with a supplyvoltage invariant resistance. Referring to figure A.7 which is taken from page 51 of file “8-bit Microcontroller with 32KBytes In-System Programmable Flash Reference Manual.pdf”, if PORTxn is written logic one when the pin is configured as an input pin, the pull-up resistor is activated. To switch the pull-up resistor off, PORTxn has to be written logic zero or the pin has to be configured as an output pin. The port pins are tri-stated when a reset condition becomes active, even if no clocks are running. If PORTxn is written logic one when the pin is configured as an output pin, the port pin is driven high (one). If PORTxn is written logic zero when the pin is configured as an output pin, the port pin is driven low (zero).

16

APPENDIX for LABORATORY 3 SHEET

Figure A.7: Configuring Digital I/O port. A Digital I/O pin configured as an for active low interrupt pin or an input pin, pull-up resistor are necessary so that a stable logic ‘I’/high level state when the input on open circuit condition. By default PUD=0 and is specifically programmed to change it. A.7.

Built-in Timers in ATmega32/ATmega32A chip

ATmega32/ATmega32A Timers have three timers (TIMER0, TIMER1 TIMER2): two of a resolution of 8 bits (TIMER0 and TIMER2) and one of a resolution of 16 bits (TIMER2). 8 bit timer is 8 bits wide so capable of holding value within 0-255 in the TCNTn (TCNT0 or TCNT1) register. 16 bits timer is capable of holding value within 0-65535 (better resolution) in the TCNT2 register. But this register has a property that increases/decreases automatically at a predefined rate (determined by user by setting the Prescaler). This is the timer clock. And this operation does not need CPU’s intervention.

Fig A.8(1): Basic Operation Of a Timer. Since Timer works independently of CPU it can be used to measure time accurately. Timer upon certain conditions takes some action automatically or informs CPU. One of the basic conditions is the situation when timer OVERFLOWS i.e. its counted up to its maximum value (255 for 8 BIT timers) and rolled back to 0. In this situation timer will issue an Overflow Flag (TOVn i.e. TOV0 for TIMER0), or can invoke an interrupt (TIMERn OVF i.e. TIMER1 OVF for TIMER0) but you must write an Interrupt Service Routine (ISR) to handle the event.

17

APPENDIX for LABORATORY 3 SHEET

(TOVx 1) TOVx  0

TOVx = 1

Fig A.8(2): Basic Operation Of an 8 bit Timer 1. Timer Basic Concepts From the following formula:

As an Example, To flash an LED every 10 ms its frequency is 1/10ms = 100 Hz. Assuing the CPU clock frequency is 4 MHz and the timer counts from 0 to TOP. For an 8-bit timer, it counts from 0 to 255 whereas for a 16-bit timer it counts from 0 to 65535. After that, they overflow. This value changes at every clock pulse. If timer’s value is zero to go to 1, it takes one clock pulse. To go from 1 to 2, it takes another clock pulse. To go from 2 to 3, it takes one more clock pulse. And so on. For F_CPU = 4 MHz, time period T = 1/4M = 0.00025 ms. Thus for every transition (0 to 1, 1 to 2, etc.), it takes only 0.00025 ms! Now, as stated above, a delay of 10 ms is needed. This maybe a very short delay, but for the microcontroller which has a resolution of 0.00025 ms, its quite a long delay! To get an idea of how long it takes, let’s calculate the timer count from the following formula:

18

APPENDIX for LABORATORY 3 SHEET Substitute Required Delay = 10 ms and Clock Time Period = 0.00025 ms, and Timer Count = 39999. The clock has already ticked 39999 times to give a delay of only 10 ms! Definitely an 8-bit timer cannot be used (as it has an upper limit of 255, after which it overflows). Hence, 16-bit timer can be used (which is capable of counting up to 65535) to achieve this delay. 2. The Prescaler The Prescaler allow limit of delay derived from the CPU clock be increased. Assuming F_CPU = 4 MHz and a 16-bit timer (MAX = 65535), and substituting in the above formula, the maximum delay is 16.384 ms. If we a greater delay, say 20 ms the Timer cannot handle it. A solution to this is to decrease the frequency to the timer i.e. as an example the F_CPU is divided (this is Prescaled by 8) from 4 MHz to 0.5 MHz (i.e. 500 kHz), then the clock time period increases to 1/500k = 0.002 ms. Now substituting Required Delay = 10 ms and Clock Time Period = 0.002 ms, we get Timer Count = 4999. This can easily be achieved using a 16-bit timer. At this frequency, a maximum delay of 131.072 ms can be achieved if Timer Count is allow up to 65535. This technique of frequency division is called prescaling. The actual F_CPU remains the same (at 4 MHz in this case) but clock to the timer is prescaled. Thus, by doing so, the frequency is divided. There is a provision to do so in AVR by setting some bits which we will discuss later. There is a trade-off between resolution and duration. As seen above, the overall duration of measurement has increased from a mere 16.384 ms to 131.072 ms. So has the resolution. The resolution has also increased from 0.00025 ms to 0.002 ms (technically the resolution has actually decreased). This means each tick will take 0.002 ms. The drawback is that the accuracy has decreased. Earlier, you were able to measure duration like 0.1125 ms accurately (0.1125/0.00025 = 450), but now you cannot (0.1125/0.002 = 56.25). The new timer can measure 0.112 ms and then 0.114 ms. No other value in between. 3. Choosing Prescalers Let’s take an example. We need a delay of 184 ms (a random number is chosen). We have F_CPU = 4 MHz. The AVR offers us the following prescaler values to choose from: 8, 64, 256 and 1024. A prescaler of 8 means the effective clock frequency will be F_CPU/8. Now substituting each of these values into the above formula, we get different values of timer value. The results are summarized as below:

19

APPENDIX for LABORATORY 3 SHEET

Choosing Prescaler Now out of these four prescalers, 8 cannot be used as the timer value exceeds the limit of 65535. Also, since the timer always takes up integer values, 1024 is not accurate as the timer count is a decimal digit (no decimal point) so either a count 717 or 718 (the nearest) can be chosen. Prescaler values of 64 and 256 are feasible if accurate timing is needed. But out of these two, prescaler value of 64 provides greater resolution. Prescaler value of 256 if chosen proved the timer a greater duration if needed. Thus, choose prescaler which gives the counter value within the feasible limit (255 for 8 bit timer or 65535 16 bit timer) and the counter value should always be an integer. In ATmega32, Prescaler can be used to get the following clock for the timer. 1. 2. 3. 4. 5. 6. 7.

No Clock (Timer Stop). No Prescaling (Clock = FCPU) FCPU/8 FCPU/64 FCPU/256 FCPU/1024 Timer can also be externally clocked

4. TIMER Registers.     

TCNTn TCCRn OCRn TIMSK TIFR

Timer counter register n Timer Counter Control Register Output Compare Register Timer Counter Interrupt Mask Register Timer Counter Interrupt Flag Register

The AVR Timer/Counter register are used for

20

APPENDIX for LABORATORY 3 SHEET    

Generating time delays Counting the operation Pulse Width modulation Waveform Generation

In this laboratory we will use Timers to generate accurate time delay. The maximum delay attainable = MaxCount*Timer Clock. Referring to Section A.4, the CPU frequency of the ATmega32A configured on the Target Board is 1Mhz. Based on this frequency, the following is the maximum delay attainable for the 16 bit and 8 bit timer for each prescaler. F_CPU=1MHx

Maximum delay (Sec) (MaxCount/Timer Clock)

Timer Clock (Hz) Prescaler

1 8 64 256 1024

1000000 125000 15625 3906.25 976.5625

16 bit timers

8 bit timers

(MaxCount = 65535)

(MaxCount=256)

0.065536 0.524288 4.194304 16.777216 67.108864

0.000256 0.002048 0.016384 0.065536 0.262144

Table A.5(1) 5. The following table shows a various prescaler setting and Timer Count to generate a 250 mSec delay required on both 16 bit and 32 bit TIMER. Required Delay F_CPU(F_CPU/

0.25 1

Sec MHz

Prescaler 1 8

Timer Clock (Hz) (F_CPU/ Prescaler) 1000000 125000

Timer Count (Required Delay*Timer Clock-1) 249999 31249

64

15625

3905.25

256

3906.25

975.5625

1024

976.5625

243.140625

For 16 bit timers Too big Acceptable Acceptable but not exact Acceptable but not exact Acceptable but not exact

For 8 bit timers Too big Too big Too big Too big Acceptable but not exact

Table A.5(2) 16 bit Timer and 8 bit Timer can be used for this delay. We will use 8 bit Timer with prescaler=1024 and Count = 243 In a subroutine, we start TCNT0 with (256-243) i.e. 13 and starts the counting up to the TOP, when at this state TOV0 will be generated, the time taken will be 250 mSec. We will keep check the TOV1 bit to identify the 2 sec delay. The we can Clear TOV0 bit, and restart Timer when needed. 21

APPENDIX for LABORATORY 3 SHEET 6. The following table shows a various prescaler setting and Timer Count to generate a 2 Sec delay required on both 16 bit and 32 bit TIMER. Required Delay F_CPU(F_CPU/

2 Sec 1 MHz

Prescaler 1 8 64

Timer Clock (Hz) (F_CPU/ Prescaler) 1000000 125000 15625

Timer Count (Required Delay*Timer Clock-1) 1999999 249999 31249

256

3906.25

7811.5

1024

976.5625

1952.125

For 16 bit timers Too big Too big Acceptable Acceptable but not exact Acceptable but not exact

For 8 bit timers Too big Too big Too big Too big Too big

Table A.5(3) Only 16 bit Timer can be used. We will use the Timer with prescaler =64 and Count = 31249 In a subroutine, we start TCNT1 with (65536-31249) i.e. 13 and starts the counting up to the TOP, when at this state TOV1 will be generated, the time taken will be 2 Sec. We will check the TOV1 bit to identify the 2 sec delay. Then we can Clear TOV1 bit, and restart Timer when needed.

22

APPENDIX for LABORATORY 3 SHEET 7. Timer Registers Every peripheral is connected with CPU from a set of registers used to communicate with it. The registers of ATmega32/ATmega32A TIMERs are given below. A. TCCR0 Register The Timer/Counter Control Register – TCCR0 is as follows:

TCCR0 is used to set up TIMER0 (Setting WGM01:WGM00 and COM01:COM00). This register is also used to start (when CS02:00 is set other than 000) and stop TIMER0 (when CS02:00  000). In this Laboratory we will be operating the TIMER0 in Normal Mode, so WGM01:WGM00 and COM01:COM00 will be set Cleared.

By selecting these three Clock Select Bits, CS02:00, we set the timer up by choosing proper prescaler. The possible combinations are shown below.

23

APPENDIX for LABORATORY 3 SHEET

B. TCNT0 Register The Timer/Counter Register – TCNT0 is as follows:

This is where the unsigned integer 8-bit counter of the timer resides. The value of the counter is stored here and increases/decreases automatically. Data can be both read/written from this register. Now we know where the counter value lies. But this register won’t be activated unless we activate the timer! Thus we need to set the timer up. When Operating in a Normal mode, When set to a starting value, TIMER0 will count up to 0xFF (max value for 8 bit number) and then TIMER0 will count up to 0x00 when at this time TOV0 = 0. Referring to table A.5(2), in a subroutine if TCNT is set to 13 (256 – 243) and then TOV0 is Cleared and TIMER0 is started with normal mode and prescaler = 1024, after 243 counts TOV0 will be set. If the CPU frequency is 1Mhz the Time take from the TIMER0 setup and when TOV0 is set will be 250 mSec as calculated in table A.5(2). Program will check the TOV0 bit in the TIFR Register. C. TIFR Register The Timer/Counter Interrupt Flag Register- TIFR is as follows. we will be using it in our code, you should be aware of it.

24

APPENDIX for LABORATORY 3 SHEET This is also a register shared by all the timers. Even here, bits 1 and 0 are allotted for TIMER0. At present we are interested in the 0th bit TOV0 bit and 2nd bit TOV1. Bit 0 – TOV0 – Timer/Counter0 Overflow Flag. This bit is set (one) whenever TIMER0 overflows. This bit is reset (zero) whenever the Interrupt Service Routine (ISR) is executed. If there is no ISR to execute, we can clear it manually by writing one to it. Bit 2 – TOV1 – Timer/Counter1 Overflow Flag. This bit is set to ’1′ whenever the timer overflows. It is cleared (to zero) automatically as soon as the corresponding Interrupt Service Routine (ISR) is executed. Alternatively, if there is no ISR to execute, we can clear it by writing ’1′ to it. D. TCCR1B Register The Timer/Counter1 Control Register B- TCCR1B Register is as follows.

Right now, only the highlighted bits concern us. The bit 2:0 – CS12:10 are the Clock Select Bits of TIMER1. Their selection is as follows.

Clock Select Bits Description If we need a prescaler of 8, we choose the third option (010).

25

APPENDIX for LABORATORY 3 SHEET E. TCNT1 Register The Timer/Counter1 - TCNT1 Register is as follows. It is 16 bits wide since the TIMER1 is a 16-bit register. TCNT1H represents the HIGH byte whereas TCNT1L represents the LOW byte. The timer/counter value is stored in these bytes.

F. TCCR1A Register For normal TIMER1 operation this register need no programming.

26

APPENDIX for LABORATORY 3 SHEET

APPENDIX B The following program implement is targeted for the ATmega32A target board conform to the circuit in figure A.3. For input we will use interrupt (refer section A.5 and A.6) to detect changes on INT0 and INT1 push buttons (refer figure A.2). For delays we will use TIMERS (refer section A.8). The program will and can be executed on AVR Studio platform using the HAPSIM that has been set to simulate the circuit in figure A.3. To run the program on the ATmega32A chip, the program has to be up loaded to the ATmega32A program memory sor AVR studio has to be set to do so (refer section A.4). The program will enable Internal pullup resistor needed for the push buttons inputs (refer section A.7). Check if JP1 connector on the ATmega32A target board is jumpered, If not jumpered the jumpers can be taken from JP2 connector (not used in this laboratory).

/* This program can be loaded on to AVR Studio simulating ATMega32A chip connected to HAPSIM which simulates an 8 bit LED panel wired to Port B pins and 2 bit Push Buttons wired to INT0 and INT1 pins. This program can also be loaded on to ATMega32A chip with an 8 bit LED panel wired to Port B pins and 2 bit Push Buttons connected to INT0 and INT1 pin. Function: When loaded to ATmega32 Program memory, on RESET will cause LED panel to display a binary count up an a 250ms pace. Every time INT0 button is pressed, the LED will toggle to counting down display from counting up display and vise-versa.

Every time INT1 button is pressed, the LED will toggle to a 2 second counting pace from 250 mSec pace and vise-versa. */ .include .def count =r25 ;Assign r25 as label "count" .def Up=r24 ;Assign r24 as label "Up" .def Fast=r23 ;Assign r23 as label "Down" .org 0 ;Declare Vector Table jmp reset ;Reset jmp INT0ISR ;INT 0 jmp INT1ISR ;INT 1

- Refer Figure A.5 (3) vector vector vector

.org 0x2a reset: ;Set Stack at end of Data Memory - Refer Note A.5(1) ldi r16,high(RAMEND) out sph,r16 ldi r16,low(RAMEND) out spl,r16 clr Fast com Fast clr Up com UP

;"Fast" Flag set False = 0x00

ldi r16,0xff

;Set PORTB as Output

;"Up" Flag set False = 0x00

27

APPENDIX for LABORATORY 3 SHEET out ddrb,r16 ldi count,0x01 ;Start COUNT at 1 com count ;Prepare for active low LED panel - Refer figure A.3 out portb,r16 cbi sbi cbi sbi

ddrd,2 portd,2 ddrd,3 portd,3

;Set PD2 as Input for INT2 input ;Enable Internal pull-up register on PD2- Refer section A.7 ;Set PD3 as Input for INT1 input ;Enable Internal pull-up register on PD3- Refer section A.7

ldi r16,0b11000000; out GICR,r16

Enable INT0 and INT1 - Refer Section A.6(3)

ldi r16,0b00001010; Set falling edge trigger for INT0 and INT1 out mcucr,r16 ; Refer Refer Section A.6(5)

SEI

;Global Interrupt bit - refer Note A.5(1)

here:

;here is where the Operating System(simple one) operates ;It wait for an Input -Interrupt event ;(in this case from INT0 and INT1 in background) ;and process the input cpi Fast,0xff ;If FastCount ==FALSE breq FastCount call TIMER1_2sDelay ; call TIMER0_2sDelay jmp DoCounting FastCount: ;Else call TIMER0_250msDelay; call TIMER0_sDelay DoCounting: cpi Up,0xff brne CountDown inc count jmp DisplayCount CountDown: dec count DisplayCount: com count out portb,count com count jmp here

INT0ISR:

;Interrupt Service routine for vector 1 - refer Figure A.5 (3) ;Invoked from a negative edge on INT0 ;Toggle Count Mode - Upwards or Downwards in R16,SREG ;Save SREG - Refer Note A.5 (2) push R16 com

Up

;R24 (Up) is modified to used in OS loop ;so is not saved on Entry and restored on Exit

pop R16 ;Restore SREG - Refer Note A.5 (2) out SREG, R16 reti ;end of the ISR - refer Note A.5(1) INT1ISR:

;Interrupt Service routine for vector 2 - refer Figure A.5 (3) ;Invoked from a negative edge on INT1 ;Toggle Count Mode - Upwards or Downwards

28

APPENDIX for LABORATORY 3 SHEET in R16,SREG;Save SREG - Refer Note A.5 (2) push R16 com

Fast;R23 (Fast) is modified to used in OS loop ;so is not saved on Entry and restored on Exit

pop R16 ;Restore SREG out SREG, R16 reti ;end of the ISR - refer Note A.5(1) TIMER1_2sDelay: push r16

;Save r16 to Stack

;Set start of counter TCNT1 - refer section A.8(6) ldi r16,high(65536-31249) ;TCNT1H <-- high byte out tcnt1h,r16 ldi r16,low(65536-31249) ;TCNT1H <-- high byte out tcnt1l,r16 ldi r16, 0b00000011;start TIMER1, normal mode, prescaler=64 out tccr1b,r16 ;refer section A.8(7)(D) waitForTOV1: in r16,TIFR ;wait until TOV1 is set - refer section A.8(7)(C) andi r16,0b00000100 breq waitForTOV1 in r16,TIFR ;Get a copy of TIFR ori r16,0b00000100 ;set bit 2 (TOV1 bit) only before writing back to TIFR out TIFR,r16 ;Clear TOV0 bit by writing 1 to it - refer section A.8(7)(C) pop ret

r16

;Restore r16 from Stack

TIMER0_250msDelay: push r16 ;Save r16 to Stack ldi r16,256-243 ;Set start of counter TCNT0 - refer section A.8(5) out tcnt0,r16 ; ldi r16, 0b00000101;start TIMER0, normal mode, prescaler=1024 out tccr0,r16 ;and refer section A.8(7)(B) waitForTOV0: in r16,TIFR ;wait until TOV0 is set - refer section A.8(7)(C) andi r16,0b00000001 breq waitForTOV0 in r16,TIFR ;Get a copy of TIFR ori r16,0b00000001 ;set bit 0 (TOV0 bit) only before writing back to TIFR out TIFR,r16 ;Clear TOV0 bit by writing 1 to it - refer section A.8(7)(C) pop ret

r16

;Restore r16 from Stack

Program B.1.

29

APPENDIX for LABORATORY 3 SHEET APPENDIX A

An Interrupt Service Routine (ISR) or Interrupt Handler is a piece of code that should be executed when an interrupt is triggered. Usually each enabled interrupt has its own ISR. In. AVR assembly language each ISR MUST end with the RETI instruction which indicates the end of the ISR. Interrupt Flags and Enabled bits.

2MB Sizes 1 Downloads 297 Views

Recommend Documents

A Appendix - Semantic Scholar
buyer during the learning and exploit phase of the LEAP algorithm, respectively. We have. S2. T. X t=T↵+1 γt1 = γT↵. T T↵. 1. X t=0 γt = γT↵. 1 γ. (1. γT T↵ ) . (7). Indeed, this an upper bound on the total surplus any buyer can hope

A Appendix - Semantic Scholar
The kernelized LEAP algorithm is given below. Algorithm 2 Kernelized LEAP algorithm. • Let K(·, ·) be a PDS function s.t. 8x : |K(x, x)| 1, 0 ↵ 1, T↵ = d↵Te,.

Appendix A
Sep 15, 2006 - things. Teacher says where she wants to go, what she wants to do. Teacher models; has students get in pairs for communication activity. Last 15 minutes: quiz. HW: Workbook pages 4 -5 complete (don't tear out,. I'll stamp), Journal: fix

Online Appendix
Aug 13, 2013 - Online Appendix Figures 3a-4e present further evidence from the survey .... Control variables include age, gender, occupation, education, and ...

Online Appendix
Aug 13, 2013 - Online Appendix Figures 3a-4e present further evidence from the survey responses on the .... Notes: Data from a survey of 70 individuals in 9 villages. ...... You will stay in the assigned room for 20 minutes listening to a.

Online Appendix
Length of business registration in days. 2. Land access sub-score ..... Trends. Province trends. Cluster. Commune. Commune. Commune. Commune. Province.

APPENDIX 12
Certain LFAs, nominated as Dedicated User Areas (DUA), are allocated for special use (such as concentrated helicopter training) and are managed under local ...

Online Appendix
Power Capital Variables adds up all ranking positions by terms (excluding the above top 4 positions). 2 ever held by native officials connected to a commune (in.

Web Appendix
We again assume U(x)=x throughout, following Doyle. As in our paper and in. Bleichrodt, Rohde, and Wakker (2009; BRW henceforth), we write ln for the natural logarithm instead of Doyle's log. As in the main text, (T:F) denotes receiving $F>0 at time

Appendix-3 IREM Examination.PDF
4l/201s sent to Railway Board on ... to clear Paper-ll, and if the revised instructions are impiernented the said staff will have to ... Candidates who have passed ... 030-22283, 22626, Fax : 01 1-23744019,Rty.22382, Tetegram : RATLMAZDOR.

Appendix-3 IREM Examination.PDF
2. Loading… Page 1 of 2. Page 2 of 2. Appendix-3 IREM Examination.PDF. Appendix-3 IREM Examination.PDF. Open. Extract. Open with. Sign In. Main menu.

ONLINE APPENDIX for
Dec 6, 2017 - that acquired other stores, whereas. “Other” denotes chains in mark ets with mergers that did not participate in the merger. All sp ecifications include a con stan t and store and time. (quarter) fixed effects. Columns. 5 to. 8 also

Online Appendix for - Harvard University
Notice first that solving program (5), we obtain the following optimal choice of investment by the ... 1−α . Plugging this express into the marginal contribution function r (m) = ρ α ...... Year started .... (2002), we obtained a master-list of

Online Appendix for - Harvard University
As pointed out in the main text, we can express program (7) as a standard calculus of variation problem where the firm chooses the real-value function v that ...

Internet Appendix for - Lu Zhang
∗Fisher College of Business, The Ohio State University, 820 Fisher Hall, 2100 Neil ... †Lindner College of Business, University of Cincinnati, 405 Lindner Hall, ...

Web Appendix
We again assume U(x)=x throughout, following Doyle. As in our paper and in. Bleichrodt, Rohde, and Wakker (2009; BRW henceforth), we write ln for the natural.

Online Appendix
When γ = 1, Equation 3 becomes α(p – c) = 1 + exp(δ – αp). The left-hand ... We averaged daily five-year maturity credit default swap (CDS) spreads on GM debt.

Online Appendix for
where µi ≡ ¯αi − ¯ci. Solving the FOCs gives ei = qi,. (A.1) qi = µi − ρ n. ∑ j=1 bijqj + φ n. ∑ j=1 aijqj,. (A.2) or, in vector-matrix form, e = q, q = µ − ρBq + φAq. Therefore, there exists a unique Nash equilibrium with the e

Supplemental Appendix for
compose only a small part of dyadic trade – particularly if the commodity holds strategic value. 4 Use of rare events logit models are justified because MID ...

WEB APPENDIX FOR
For this level of θ and above, the ruler centralizes the entire territory. .... are log area, major river, agricultural constraints, distance to coast, elevation, malaria, ...

Appendix 3 IREM Examination.PDF
International Transport Workers' Federation (lTF). No.IV7OlPt.II. The Financial Commissioner (Railways),. Rail Bhavan,. New Delhi. Dear Sir,. Sub: Appendix 3IREM Examination of 2015 - results - reg. ' Ref: NFIR'sletterNo.IVT}lPtIdated10/0512016. In c

Supplemental Appendix for
We code these variables using data from Pevehouse, Nordstrom, & Warnke (2004). .... Australia. Japan. Israel. Iceland. Denmark. Norway. Sweden. Finland. Italy .... following criteria: (1) direct election of the executive (or indirect selection via ..

Appendix 3 Page 1 of 3 MEMORANDUM OF ... -
Dec 31, 2012 - ELDOT Organizing Meetings. 10,000. Lunch & Dinner. 44,000. Travel-Festival Director. 28,000. Food & Lodging. Festival Director. 7,000. 7,000.