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With Its Paged Structure, A 512K EPROM Relaxes System Storage Constraints

BY KURT ROBINSON PRODUCT MARKETING ENGINEER INTEL CORPORATION

INTEL CORPORATION, 1985. Reprinted with permission from Electronic Design.

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DESIGN ENTRY With its paged structure, a 512k EPROM relaxes system storage constraints The limits imposed by the addressing range of today's 8-bit microprocessors are removed by a pageaddressed EPROM that acts like four 128-kbit chips.

nventive system designers know that advanced software features could prolong the usefulness of their 8-bit microprocessorbased systems. Though the idea is an attractive one, adding those changes to program memory would often strain the 64-kbyte addressing range of the microprocessor. Today's 512-kbit EPROMs have the higher capacity but would consume the entire address space of the 8-bit machines. A new twist-a 512-kbit EPROM organized as four 16-kbyte pages-quadruples the program storage available to an 8-bit system. Indeed, 16-bit systems can benefit from using it. As important, the entire chip looks to the system like a 128-kbit EPROM, which it can easily replace. Upgrading a system in this way entails little or no software modification, while building a new one with the device reduces circuit complexity and permits the use of less costly and more mature system components. The byte-wide 27513 is a paged version of the 27512 512-kbit EPROM. Only 14 of its 16 ad-

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Kurt Robinson, Intel Corp. Kurt Robinson has served for five years with Intel's nonvolatile memory division, which recently moved to Folsom. Calif. Starting as an EPROM product en· gineer, he later joined the programmable memory marketing group as an applications engineer. Subsequently he advanced to senior product marketing engineer. His BSEE is from Cornell and his MBA from the University of Santa Clara.

dress bits are needed to access it s full 64 kbytes, since it reserves on-chip latches for the two highest-order bits. Its 16-kbyte page size satisfies a variety of system requirements. A smaller page would entail too frequent page changes. A larger one would leave too little room for addressing RAM-which in a reprepresentative 8085-based system requires 48 kbytes of the microprocessor's 64-kbyte address space (Fig. 1). In fact, the microprocessor treats the EPROM as if it were a fourth bank of 16-kbyte RAM and selects it by writing to a 2-to-4 decoder. The main difference

The primary operational difference between the paged 512-kbit device and linearly addressed EPROMs, including the 27512, lies in page selection. First the microprocessor sends the EPROM 2-bit page data over the lowest-order data bi ts, Doand D,. Next it enables the memory by setting the Chip Enable (CE) line low via the 2-to-4 decoder. Then it brings the Write Enable line (WE) low also, thus clocking the page data into the chip's 2-bit address latch. Thereafter the newly selected 16-kbyte page can be accessed during conventional EPROM read cycles. The address inputs during page selection are in a "don't care" state. During power-up, the EPROM automatically resets itself to page 0 as if the data 00 were being written into D, and Do. A circuit for clearing the page latch remains active until Vcc exceeds

DESIGN ENTRY 512·kbit EPROM

4 V.Above that level, system control signals remain sufficiently stable to avoid inadvertent page selection. The 4-V level is also low enough to prevent a low-going power-supply glitch from accidentally clearing the page latch. The worst-case voltage for Vcc is 4.5 V. The 4 V that clears the page also sets a 500-mV noise margin against supply undershoot, without presenting any danger of resetting the current page to O. Programming the 27513 utilizes a proprietary algorithm supplied with all 12.5-V HMOS EPROMs, including the 27512.This algorithm creates 1-ms programming pulses until the byte has been verified, after which it gives a programming overpulse margin of three times the number of initial pulses. A page-select write operation is included at the start of the program and at every subsequent page boundary thereafter. (Fig. 2). The chip's programming voltage, Vp~ multiplexed with the OJ!1putEnable line (OE), and the combined line (OE/Vpp) is brought to 12.5V for programming and to a TTL low level for verificatiQ!has in a normal read. If the chip is disabled (CE goes to a TTL high) while OE/Vpp

is at 12.5V, programming stops. After each page has been programmed, it undergoes a page-selection write operation, with the write parameters tested in a manner similar to that for static RAMs. Because the chip's page latch is a write-only register, the programmed data is not read back. Instead the memory must be checked for a successful page change. Unique data must appear in at least one physical address on each page; checking that address on each page and finding the unique data confirms that the page programming was successful. Though testing of the write cycle entails reading from specific addresses, an actual write operation is independent of the address inputs. Simple to substitute

The EPROM chip has a socket footprint almost identical to that of a 128kEPROM, meaning that it can easily be substituted for the smaller device in an existing system. However, some changes in board design are required. For example, the 512k EPROM assigns pin 27 to the Write Enable control signal, as in the JEDEC standard for byte-wide RAMs. In contrast, a

1. An 808S-based system equippe!l with 48 kbytes of RAM has room only for a 16-kbyte block of EPROM. But the 27S13 EPROM packs four such blocks into the space previously occupied by a 128-kbit part. The EPROM resides In memory space from ‫סס‬oo,. to 3FFF,.; tha RAM occupies addresses 4000,. to FFFF , •.

DESIGN ENTRY 512-kbit EPROM 128k EPROM's pin 27 is set for the program function and is tied to 5 V or Vcc. The origin of the Write Enable signal of the 27513 varies, since the chip encounters situations in which code and data must share the same memory map but are selected independently through dedicated selection lines or decoded status signals from the processor. Upgrading a circuit to the 512k EPROM from one designed for a 128k EPROM is dramatically simplified if the socket has been laid out according to the so-called universal site for byte-wide memories. That arrangement brings address and control lines close to the socket, so that different configurations can be selected through jumpers. Designers can access Vcc (for tying the program pin of 64k and 128k EPROMs to 5 V) and WE (for byte-wide RAMs) through the universal pin 27. Thus if the socket follows this standard arrangement, the 27513 can be substituted for lower-capacity devices by changing justonejumper. Superior

16-bit control,

too

The paged EPROM can solve the limited addressing range of both 8-bit and 16-bit microprocessor-based systems. That holds true especially for firmware-intensive jobs that tax the 16-bit chip's seemingly adequate addressing range of a megabyte or more assigned to EPROM. For example, a system tackling frequent transactions can actually eat up most of its total memory address space, which can reach about 16 Mbytes. It may use high-order address lines for specialized I/O and still have enough room for a megabyte each of RAM and EPROM. The code changes required to modify the extremely complex functions of transaction processing might cause even the megabyte of EPROM to overflow. With the 27513, code can be chopped to more manageable levels or rearranged into different memory configurations. The 512k chip is not suited to all 16-bit systems. Indeed, executing code in the consecutive pages of the segmented chip poses a real challenge to the software programmer of, say, the 80186, which has internal segmented addresses. A high-performance processor like that also prefetches several instructions, making it difficult to know which page in the paged 512k chip

2. A proprietary programming algorithm performs a page-selection write operation at the end of each page in the 27513. The algorithm generates 1-ms pulses until 8 bits have been verified; an overpulse that lasts three times longer than the number of initial pulses gives an extra program margin.

would be sourcing the executable code when page boundaries are being crossed. But segmented addressing and prefetched instructions do not completely eliminate the possibility of using the 27513 with a processor like the 80186. For instance, when the processor must access several large banks of fixed data or application code-but not simultaneously-a group of th€se 512k chips can be set to the same page by an appropriate hardware switch or by operating-system commands. Software concerns

When the paged EPROM is storing fixed data or discrete application programs (those that do not run concurrently), it is treated like another 128k chip. Designers need not worry about specialized software for crossing page boundaries; the code is executed either from another memory (for fixed data) or from the same page of each chip (as in nonoverlapping software). On the other hand, when program code is executed from consecutive pages of the EPROM, the software considerations become more critical. In this case, the software for crossing page boundaries must maximize system performance, afford the greatest flexibility, and simplify the programming task itself. Satisfying anyone of those objectives to a great degree forms a trade-off in the others. That is, if performance jumps, transitions must be kept to a minimum. Optimum performance can be reached only at the expense of less flexible code. A flexible program illustrates the trade-offs that must be made. It usually comprises a small number of statements that contain several conditional calls and jumps. Program flow can be changed easily, and the modular nature of the subroutines makes the modification of specific operations simple. This approach is consistent with common programming techniques. An exception is the few extra instructions required to cross page boundaries. The flexible structure's call sequence is initiated by using the new page number and a lookup table, called offset, for the subroutine address (Fig. 3a). The command Call is issued and the new page selected. However, the current page number remains unchanged. Next, the subroutine Call Address is obtained from the new-page lookup table, as indexed by the

offset table. After a jump to Call Address in the new page, a return is made by jumping to the instruction RETR. The current page number is read, and the chip is reset to the previous page. Finally the program goes back to Return Address in the original page. If the program branches to a new section of the program and there is no need to return to the previous page, a jump sequence begins. First, the offset table and the new page number are loaded, and the program moves to instruction JUMPR. The new page is now selected and its number stored in the current page location. The jump address is found in the new page lookup table, based on the offset table. A jump is then made to Jump Address in the new page. Subroutine lookup tables are essential to this most advanced method of page selection, one that involves storing the lookup tables in the EPROM chip itself and reserving a small section of RAM for page-selection code. Although the technique demands more code for the page transitions, the overall amount is reduced by eliminating redundant instructions for common subroutines. The look-up tables contain the page number and the offset address from which a given routine is called. Within the page containing the actual subroutine code, another lookup table, indexed by the offset value, holds the physical address of the routine. Thus the page number and offset information contained in the other pages remain constant, but the physical address of the actual subroutine can be relocated within its page, even if the code changes. The in-. structions for handling the page transitions are preloaded into a reserved section of RAM when the system is initialized. Interrupts anywhere

Interrupt routines can be executed from any page of the EPROM if the current page information is retained. After the interrupt has been serviced, the EPROM is reset to the page and address that were current when the interrupt occurred. Here again, the instructions for handling the page transitions and for calling the interrupt subroutine are preloaded into reserved RAM. As with the flexible programming structure, designers are typically trying to make their

DESIGN ENTRY 512-kbit EPROM program code more efficient by squeezing the greatest number of operations into each instruction. Those are critical concerns for systems that place program code in standard 128-kbit EPROMs, but they become much more relaxed when seen in terms of the 27513's fourfold increase in capacity. Some designers might choose straight-line programming where jumps and calls are avoided. The 27513 excels in that situation, i.e. where flexibility and compactness of code are sacrificed for an overall increase in execution speed (Fig. 3b). A true straight-line program contains no calls or jumps; the code for any repeated function is replicated each time.

Though a program that uses no branching may appear impractical, another approach that places all subroutines in the same page as the call and jump commands that refer to them is not impractical. With that technique, frequent operations are stored on every page-but only once. In either case, page transitions occur only at the end of a page or when the program is jumping back to the beginning. Small instruction sets at the start and end of each page actually shift the pages. If the page transitions occur frequently but at relatively few points in the program, another scheme-one of moderate complexity-duplicates the set of instructions at the straight-line

3. The program atrueture of the 27513 can take three forma. A flexible program requirea more code for page trenaitiona and eliminatea redundant inatruetiona for frequently called aubroutinea (a). The atraight-Iine approach afforda the faateat performance (b). A modification of that atrueture maintaina the apeed but adda branching code to deal with jumpa between page boundariea (c).

program's page boundaries. In that manner, page transitions occur through dedicated portals of code (Fig. 3c). Enlarging fixed storage

Though the 512k chip will undoubtedly be called to duty for code-expanding missions in popular 8-bit processors, its hardware interface proves equally suitable for applications requiring more storage of fixed data. Suppose that the chip is substituting for several 128-kbit EPROMs in an 8051-based dot-matrix printer. The chip itself provides enough extra storage space that designers can add three new character sets (for example, scientific marks, mathematical symbols, custom shapes). The Write Enable signal derives from the processor's Write/Read line, as with standard data memory. Likewise, the software interface is not complicated, since the chip is not actually storing code. Pages are selected either by an external hardware switch or by a command from the host computer. The 27513 is not limited to 8-bitjobs-it makes a valuable addition to a 16-bit system, since it can store firmware for several independent application programs. In fact, it could quadruple the number of programs in, say, an 8088-based system, wi thout increasing the total

amount of physical address space allocated to EPROM. And because the programs are not used simultaneously, the system interface is simple. Each program is selected in much the same manner as for the 8051 character-set storage application. Even a complex chore, such as storing firmware-intensive 8031 applications, need not be a formidable task with the chip (Fig. 4). The 8031 has a special PSEN(Program Store Enable) signal to enable the output of external program memory. Because data cannot be written to the standard program memory, the designer must make sure that the 27513 is su bj ected to the necessary page-selection write operation. If the external data memory of the 8031 is not fully used, the EPROM chip's page latch can be addressed as if it were a lower-order bank of external RAM. Th~r, and WR signals can be ORed to generate WE; alternatively, a specific RAM address can be decoded to generate WE. That would reduce the amount of RAM address space allocated to the 27513 but at the expense of additional decodingcircuitry.o

4. Although some processors do not make a perlect match lor the 27513, provision can be made lor the EPROM's requirements. Here the memory's page latch is addressed as il the chip were a low-order bank 01 external RAM. ORing the processor's A15 and WR signals generates the 27513's WE signal; line A,s determines whether the RAM or EPROMs are selected. Chip-enable signals lor the 27513s are decoded Irom lines A,. and A,s.