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AR-414

Marri. Of CMOSArid PLCCSparking Rapid Change In Mounting Memories

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he surge in circuit complexity over the past year or two has pushed the standard DIP size beyond workable climensions, and rendered it obsolete where high lead count is required. Meanwhile, the semiconductor indU8try's shift to CMOS procesaing for memories, as weJI as other ICs, is helping usher in the era of surface-mountable packages. Chief among these packages for memories is the plasticleaded chip carrier (PLCC). The technology for surface mountables and CMOS procesaing emerged from shaky beginnings. Although surface-mount packaging has been available for nearly two decades, its potential has just begun to be realized. Several technical problema hampered its early acceptance: the need for automated factory equipment; prohibitively high packaging costs; and the lack of nece88arY construction tools. As of 1984, only 6 percent of all components used in the United States were surface-mount types. Industry analysts predict, however, that with the increase in packaging options, the availability of development tools and the rising demand for surface-mountable devices, more than 25 pe~nt of components will be surface mounted by 1988. And an estimated 128 million of the 600 million PLCCs manufactured in 1988 are expected to be memories. CMOS has had to fight a similar battle. Prohibitively high cost, inherently low performance (metal gates) and lack of a complete lineup of products necesaary to provide low-power system solutions were the chief reasons for CMOS' slow start. But, these problema have now been overcome and the number of products combining CMOS technology and surface-mount packages is accelerating rapidly. PLCC Inroeda The decision to move from insertion (through-hole) to surface-mount technology is not an easy one. The available options are somewhat confusing: eAre space constraints a problem? els more functionality required? eWillsurface mounting make a more competitive product? eWill manufacturing-cost savings be realized? EI«tnMic EIfIin«rV18 TiMws -

els the proper assembly equipment already available? eDo components meet JEDEC standards? eWill socketing be required? The drive for smaller, more functional and more competitive products is forcing many engineers to sc81e down existing designs; to strive for VLSI solutions; and to use PLCC packages and other surfacemount packaging options, which can reduce board size dramatically. Decisions as to which surface-mount option to use are usually baaed on boardsize restrictions. In general, PLCCs minimize the area footprint on a board for lead counts ranging from 28 to 124. One example of the space-saving ability of a PLCC package is Intel's new 32-lead PLCC package which it is developing for its 64k and 266k CHMOS EPROMS. The PLCC measures 0.• 5 x 0.55 inch, whereas the 28-pin DIP that would nOl"llUlllybe used here measures 1.4 x 9.6 inch. The reduction in area footprint is 70 percent. The contact area for clUpleads can be closer for a PLCC device because the mounting holes mandatory for insertion devices are eliminated. Surface mounting also allows components to be placed and soldered on both sides of a pc board where through-hole mounting is not employed. Depending on the complexity and type of components required in the board layout, a 35- te 60percent reduction in board size is possible. To minimize tota1 chip requirements, manufacturers of products such as EPROMs are incorporating an addresalatch on the addresa and data pins to allow direct interface with a microcontroller or microprocessor. This eliminates the need for an external latch, as well as reducing board size. Surface-mount elements can also re-

duce component weight as much as 75 percent. Lightweight PLCC packages tend to be ideal for high-vibration industrial and automotive applications, as well as for portable applications. Surface mounting requires a substantial investment in capital equipment. New techniques for soldering components to boards (Le., vapor phase or wave soldering) must be considered and automated machinery such as pick-and-place assemblers must be employed-new pick-and-place machinery employing vacuum pickup has been developed to handle the wide array of different sized packages available for surface mounting. Today, many different machines are available. Their processing capacity ranges anywhere from 500 to 500,000 devices per hour. (Surface-mounting technology is even used in small-volume, custom facilities, such as for making portable medical equipment, where the devices are manually soldered to boards.) The benefits offactory-automated assembly are numerous. Lesa f'loor space is required. Since raw materials are contained in smaller packages, storage space is diminished. Lighter-weight components reduce shipping and handling expenses. Space-saving benefits can be achieved in the layout of the assembly equipment itself. Some manufacturers have been able to reduce the required factory floor space by as much as 25 percent. Other cost savings include a reduced labor force, the ability to maintain a no-shutdown assembly, improved reliability and reduction of inspection and rework. These benefits must outweigh, of course, the costs of automating the factory, as well as the cost of restructuring and retraining.

••..... This CMOS EPROM combines both n-chsnnelend type epltaxlel sUbstrete to reduce greeUy current en NMOS counterpert.

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Copyrigh~ 1985 by CMP Publications, Inc., 600 Community Drive, Manhasset, N.Y. 11030. Reprinted wnh permission from Electronic Engineering Times.

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inter When choosing between packaging alternatives, consideration should al· ways be given to industry·wide stan' dardization to avoid unneceBBary de· sign mismatching and insure upgradeability. For example, the 32· lead PLCC package was chosen for high· density EPROMs because as much as 512 kbits of addre88 space is easily contained within this package size. Furthennore, PLCC devices with as many as 124 J·type lellds have been registered with JEDEC, the standard· setting body for the industry. A J-type lead extends out of the four sides of a PLCC package and is tucked under the body into small pockets. 1t was chosen as the industry·standard lead type as opposed to gull wing for several reasons. A minimum-area footprint is best achieved with a J·lelldgull wings extend horizontally out from the body of the package, increasing the required area footprint of the compo' nent. Because of their extended leads, gull·wing devices are also at greater risk to damage during assembly or transporting. J-type leads are also more aptly suit· ed for socketing, which may be particu· larly important for memory components subject to periodic updates. The J-Iead PLCC does, however, have its drawbacks, the most noticeable being the difficulty encountered in inspecting solder joints. The next step for design engineers who have decided to use PLCC compo' nents is to investigate the available proce88-technology alternatives. CMOS And PLCC Packaging Applications ideal for both CMOS parts and PLCC packages lie in lowpower portable products in space-con' strained environments. Examples can easily be found in the automotive, tele· communication and portable·instru· ment markets. Alan Hanson is product marketing enginaer, Intel Corp., Folsom, Calif.

CMOS' greatest strength lies in its low·power properties. For example, In· tel's 27C64 CHMOS EPROM, which combines both n-channel and p-channel transistors onto a p-type epitaxial substrate, maintains a maximum operating current of 10 mA, standby current of 100 mA and otTers 200-ns total access time. Its NMOS counterpart would require six times more active current, 200 times greater standby current and would otTerno improvement to total acce88 time.

Both the 28-p1nDIP and 32·leed PLCC can hold anywhere from 32k to 512k EPRO•••. But, the carrier la roughly a third a_lIer. PLCC packages are essential in portable applications because of their space-saving and lightweight features. Minimizing component packaging size, however, achieves little if used in con· junction with bulky power supplies, batteries and cooling devices. Because of its low·power reql,1irements, CMOS helps minimize the need for large power supplies and cooling devices, as well as enhancing PLCC-device reliability. Because of their reduced pack8&esize and plastic construction, PLeCs are poor ileat conductors compared with the larger DIP packages. So heat-related break· downs are more likely-heat di88ipation is generally a function of package material, length and construction of leads, package surface area and, of course, the

power consumed by the devices. ln improving the overall integrity and reliability of surface-mountable components, methods must be employed to deal with thennal-manage· ment problems. The chief way to ac· complish this for PLCCs is to reduce the resistance to heat flow from the active junction to the atmosphere. Thermal resistance ranges from about 40C· per watt for a 68·lead PLeC package to more than lOOC·per watt for the 20·lead device. Copper alloy leads, modified substrate materials, and special heat sinks are being used at the package and board levels to maximize heat conduction. ln VLSI applications where increased device functionality is required, thennal management becomes an acute problem. As functionality increases, power demands likewise increase. The resulting higher operating temperatures may result in severe degradation to device operation and perfonnance. CMOS otTers a solution to thennal· management problems. For example, the 27C64, with a maximum operating current of 10 mA, generates 50 mW of heat-a sixth the amount of its NMOS counterpart. Depending on the particular design and application, special heat-sink designs and/or cooling fans can be reduced or even eliminated with CMOS parts. CMOS is particularly valuable in ex· tended-temperature environments, such as automotive engine.control applications where operating tempera' tures range from - 40·C to 80·C and as high as 125·C. In these applications, CMOS may be the only way to provide reliable device operation. CMOS also brings to a PLCC package wider Vex tolerances and HMOS compatability. Support tools such as testing, soldering and programming equipment have also become available for CMOS-based surface-mount designs. EET