HIGH VOLTAGE MOSFET CAD MODEL IN ADMS Kerwin O. Khu1,2, Fujiang Lin2, Le-Wei Li1

1

Singapore-MIT Alliance, National University of Singapore (http://www.sma.nus.edu.sg) 2 Institute of Microelectronics, Singapore (http://www.ime.a-star.edu.sg) 11 Science Park Road, Singapore Science Park II, Singapore 117685 [email protected] , [email protected] , [email protected] Abstract

An analytical model of a high voltage MOSFET device is presented in this paper. The model is simple and efficient, requiring only a few easily extracted parameters, which makes it suitable for CAD applications. The model is implemented with the new tool, Automatic Device Model Synthesizer (ADMS), for ease of integrating into existing simulators. Keywords: high voltage MOSFET, analytical model, ADMS Introduction High voltage MOSFET’s (HVMOS) are used in driving liquid crystal displays (LCD’s). With increasing popularity of LCD’s in personal computers and in consumer electronics, there is a corresponding need for a better HVMOS model for use in computer-aided circuit design. Currently, industry standard models such as BSIM3 provide a poor fit when modeling HVMOS devices. In addition, the parameter extraction procedure required for BSIM3 is very complex. Developing a new model from scratch or making modifications to such a model is often difficult and timeconsuming [1]. Another approach is to change the physical meanings of the parameters of a standard model and reinterpret them in a non-standard way [2]. In this paper, we will develop a custom CAD model using an analytical approach. That is, we will build a model empirically from measured characteristics, with the objective of keeping the equations simple while minimizing the number of parameters.

that the source and bulk nodes are shorted. The equations and our modifications are briefly described below. A. Ids-Vgs relationship We start with a variation of the well-known square-law characteristic of the inversion region:

[

]

I dso (V gs ) = A{ln 1 + exp( B (V gs − Vth ) }

2

(1)

Our measured characteristics show however that the Ids-Vgs relationship is highly linear in our sample transistors. Thus, we generalize (1) to this form:

[

]

I dso (V gs ) = A{ln 1 + exp( B (V gs − Vth ) }

Q

(2)

With parameter Q restricted to values between 1 and 2, inclusive, and with the threshold voltage Vth related linearly to Vds,

Vth = Vtho − σ (Vds − Vdso )

(3)

Where Vtho is the threshold voltage measured at Vds = Vdso. If we define parameters Ith and Sth such that:

I th = I ds

V gs =Vtho

and S th =

∂I ds ∂V gs

(4) V gs =Vtho

Then we can express A and B as:

The main problem of custom models, however, is that they are difficult to integrate into commercial simulators. Our approach addresses this problem by implementing our model using the up-and-coming Automatic Device Model Synthesizer (ADMS) tool [3]. ADMS is based on the open high-level language Verilog-A, from which it generates C code for specific simulators.

Thus, (2) can be defined with three easily extracted physical parameters Vth, Ith, and Sth.

Model Equations

On the other hand, the saturation region of the Ids-Vds curve can be approximated with the hyperbolic tangent function:

The model equations are based on a previously developed empirical model for LDMOS devices [4]. This model assumes

A = I th /(ln 2) Q and B = 2 S th (ln 2) / Q ⋅ I th

(5)

B. Ids-Vds relationship

I max (Vds ) = I sat (1 + λVds ) tanh(αVds )

(6)

The saturation current term Isat can be treated as a physical parameter by extrapolating the maximum Ids for Vds = Vdso; however, we find that we generally get better results by treating it weakly as a fitting parameter. C. Smoothing Function

ADMS tool. // VerilogA for mylib, hvmos1, veriloga `include "constants.h" `include "discipline.h" `define T_nominal 27

A smoothing function for combining the terms in (2) and (6) is the following [4]: −1 −1 I ds (V gs , Vds ) = ( I dso + I max ) −1

(7)

We add a parameter n to (7) for better fitting: −n − n −1 / n , I ds (V gs , Vds ) = ( I dso ) + I max

(8)

n n I ds (V gs , Vds ) = I dso I max /( I dso + I max )1 / n

(9)

or

The form of (9) is preferred since it provides continuity when the drain voltage Vds = 0.

module hvmos1(g, s, d); inout g, s, d; electrical g, s, d; parameter real ith=4.806u, sth=47.67u, vth=1.583; parameter real isat=3.54m, n=3.392, vdso=10; parameter real alpha=0.1359, lambda=0, sigma=3.047m, q=1.31; parameter real T=27, vT1=0, vT2=0, iT=0, pT=0; real vgs, vds, vgd; //voltages //temporary vars real idso, imax, delta_T, vth1, isat1, ids1, tmp; analog begin vgs = V(g,s); vds = V(d,s); vgd = V(g,d);

This term adjusts the current downwards when Vds is high.

// DC I-V part delta_T = T - `T_nominal; vth1 = (vth-sigma*(vds-vdso))+vT1*delta_T+vT2*pow(delta_T,2); isat1 = isat + iT*delta_T; inot = (ith/pow(ln(2),q))* pow(ln(1+exp(2*sth*ln(2)*(vgs-vth1)/(q*ith))),q); tmp = alpha*vds; imax = isat1*(1+lambda*vds)* (exp(tmp)-exp(-tmp))/(exp(tmp)+exp(-tmp)); //tanh ids1 = (inot*imax)/pow(pow(inot,n)+pow(imax,n),1/n); I(d,s) <+ ids1/(1+pT*vds*ids1); end

E. Temperature Effects

endmodule

D. Self-heating We provide a simplified treatment of the self-heating effect by adding a fitting parameter pT as the self-heating coefficient:

I ds ( pT ) = I ds1 /(1 + pT Vds I ds1 )

(10)

The temperature dependence can be modeled by the following modifications to the threshold voltage and saturation current equations:

Vth (T ) = Vth (Tnom ) + VT 1 (T − Tnom ) + VT 2 (T − Tnom ) (11) 2

I sat (T ) = I sat (Tnom ) + I T (T − Tnom )

(12)

Where Tnom is the temperature at which measurements were taken. Model Description Most commercial simulators have a mechanism for adding new, user-defined models into the simulation environment. Typically, these models take the form of C files. However, each simulator has its own distinct interface, such as the CMI interface of the Cadence Spectre simulator. Thus, it would require a lot of work to support a new model in different simulators. We will get around this problem by using the

Fig. 1. Verilog-A description of HVMOS model

In this approach, the model equations are encoded in the Verilog-A language, which is the analog-only subset of the open Verilog-AMS language [5]. This is the standard language used by ADMS [3]. Verilog-A is a high-level language, which means that model equations can easily be coded in a compact form, as shown in the sample description in Fig. 1. ADMS reads in the Verilog-A description of the model, which then generates the C model for the target simulator. The generated C code is then compiled with the simulator interface, the end result of which is a model which can be treated as a built-in model of the target simulator. Results and Discussion Here we show typical results obtained from modeling 0.35-µm technology 12 V HVMOS devices. The particular device is a W = 10 µm NMOS transistor.

Table 1. Simulated Parameter Values (gate width 10 µm) Vtho, V Ith, A Sth, A/V Isat, A Vdso, V α, 1/V λ, 1/V n Q σ pT

(a)

1.707 2.08 x 10-5 5.006 x 10-5 3.732 x 10-3 10 1.206 x 10-1 0 4.193 1.258 1.77 x 10-2 1.832

Fig. 2 shows the measured vs. the modeled Ids-Vgs curve and Gm-Vgs curve for Vds = 10 V. Fig. 3 shows the measured vs. the modeled Ids-Vgs curves for Vgs = 0 to 16 V. Table 1 lists the parameter values used for the simulation. Optimization of the parameters was done by means of the commercial package Agilent IC-CAP. Our model’s Ids-Vgs and Gm characteristics shows a reasonable match to the actual data. The Ids-Vds curve shows that our model is a good match in the saturation region, but is not as good in the triode region. Note also that at low Vgs and high Vds, we start to see the breakdown effect of the transistor. Some modification of the model equations needs to be done to extend the accuracy of the model. Currently, the C code generated by ADMS for the Cadence Spectre simulator has been verified. The C code for the Agilent ADS simulator will also be verified. Scalability

(b) Fig. 2. Measured vs. simulated data for (a) Ids-Vgs and (b) Gm-Vgs curves of a NMOS device (gate width 10 µm)

To show how the model scales, we compare the results obtained a device with different dimensions, e.g. a device with half the gate width (5 µm). If the dimension varies only by a few factors, then the drain current is roughly proportional to the gate area. Thus, we expect that for the same parameters, drain current of the 5 µm gate width device would be half of the 10 µm width device. Or, equivalently, halving the currentrelated parameters should give the correct simulation. Table 2. Simulated Parameter Values (gate width 5 µm) Ith, A Sth, A/V Isat, A

1.04 x 10-5 2.503 x 10-5 1.866 x 10-3

Fig. 4 and Fig. 5 show the measured vs. simulated data for a 5 µm width transistor by halving Ith, Sth, and Isat parameters of the 10 µm width model, while maintaining the values of the other parameters.

Fig. 3. Measured vs. simulated data for Ids-Vds curves (gate width 10 µm)

Clearly, the fit is not as good, but optimization of the parameters should correct it. The model parameters are roughly scalable and should provide a good starting point for

optimization. Note though that small-dimension effects are not necessarily accounted for by the model.

Future Work A. Model Improvements As noted in the previous section, the accuracy of the model can still be improved. One area of improvement is to take into account the substrate current induced body effect (SCBE), which is the effect responsible for avalanche breakdowns in MOSFET’s. As suggested in [6], this effect can be modeled as a substrate current Isub which is added to the drain current Ids. To model the snapback effect, [7] suggests that we can set the breakdown parameter as a linear function of Vgs. Another area of improvement is the triode region of the Ids-Vds curves. The measured data shows that the “knee” voltages of the Ids-Vds curves are more strongly a function of gate voltage Vgs than the model currently indicates. Scalability could also be improved by using a more sophisticated model than the simple proportional to area rule.

(a)

B. Small-signal modeling In addition to the DC characteristics modeled, the CV characteristics can also be measured and modeled using the same approach for use in RF circuits. Conclusion An efficient, simple, scalable HVMOS large-signal model has been developed. The technique used here can be generalized to rapidly develop models for other devices which do not have standard models. The ADMS tool can be used to easily integrate such new models into popular simulators. Acknowledgements (b) Fig. 4. Measured vs. simulated data (unoptimized) for (a) Ids-Vgs and (b) Gm-Vgs curves (gate width 5 µm)

The authors would like to thank Chartered Semiconductor Manufacturing, Singapore, for providing the sample wafer from which this model was extracted. The authors offer sincere appreciation to Laurent Lemaitre of Motorola for his support in using ADMS. The authors would also like to thank Cadence Design Systems for sharing their CMI code. References [1] [2] [3] [4] [5] [6] [7]

Fig. 5. Measured vs. simulated data (unoptimized) for Ids-Vds curves (gate width 5 µm)

K. Kundert, "Automatic Model Compilation: An Idea Whose Time Has Come," http://designers-guide.com/Opinion/modcomp.pdf, May 2002. T. Myono, et al, “High-Voltage MOS Device Modeling with BSIM3v3 SPICE Model,” IEICE Trans. Electronics, Vol. E82-C, No. 4, 1999. L. Lemaitre, C. McAndrew, S. Hamm, "ADMS - Automatic Device Model Synthesizer," IEEE Custom Integrated Circuits Conference, 2002. A. V. Grebennikov and F. Lin, "An Efficient CAD-Oriented Large-Signal MOSFET Model," IEEE Trans. Microwave Theory and Techniques, Vol. 48, No. 10, October 2000. Verilog-AMS Language Reference Manual, Open Verilog International, 1999. BSIM3v3.2.2 Manual, University of California, Berkeley, 2001. F. Lin, B. Chen, T. Zhou, B. L. Ooi, and P. S. Kooi, “Characterization and modeling of avalanche multiplication in HBTs,” Microelectronics Journal 33, pp. 39-43, 2002.