Automatic circuit layout for emerging nanoscale architectures C. Teodorov, C. Dezan and L. Lagadec Lab-STICC CNRS UMR 3192, Universit´e de Bretagne Occidentale {ciprian.teodorov, catherine.dezan, loic.lagadec}@univ-brest.fr Context • Nanofabrics

One of the most exciting developments in science and engineering over the past few years has been the progress toward architectures, materials, and devices for nanoscale and molecular-electronics-based computing systems. These progresses met the need of the microelectronic industry for ever increasing performances • Metamodeling and small feature sizes. NASIC[5] is one example of such architecture. They are based on a variety of nanodevices but still require some supporting CMOS • Physical layout circuitry. The manufacturing process of these fabrics proposes a combination of lithographic processes and bottom-up self assembly, thus imposing some • CAD constraints on the architecture layout and reliability. The regularity of assembly and the huge number of faults are mainly the principal effects of the bottomup self assembly. Based upon our experience with the FPGA CAD framework Madeo[2], we introduced N ANO M ADEO[1]: a generic, evolutive CAD framework for automatic circuit layout. The principal characteristics of this framework are its capacity to explore the complex solution space circuits/architectures/algorithms/metrics, enabling three principal prospection possibilities using different metrics. Here, we are presenting N A B OO a prototype implementation of the physical design steps in N ANO M ADEO.

Metamodeling Approach for Durable Nano-Oriented CAD Tools Structured Circuit Model

Architectural Model Parametric virtual representation of the nanofabrics, encapsulates the topological and physical constraints of the target architecture. Principal characteristics: 1. Nano/CMOS device representation: FET, nanowire, microwire, etc.; 2. Basic architectural primitives: crossbar, nanotile, etc.; 3. Hierarchical composition of 1 and 2;

Polymorphic model capturing the structural characteristics of a circuit. Principal characteristics:

Logic

1. Encapsulate behavioral code, memory elements, etc.;

Logic

Logic

2. Hierarchical circuit representations based on composites and aliasing;

→ Integrates new hybrid architectures through model evolution; → Enables reconfigurable and non-reconfigurable fabric modeling;

→ Powerful tools (circuit simulation and visual editing) inherited from Madeo.

→ Offers the architectural support for the physical layout tools.

Yal

Fabric Specifications Architectural Model

Port

Net SCCompositeNode

Embedded Port

SCSimpleLogic

Example of a simple Structured Circuit Model instance

EDIF

Blif

Structured Circuit Model

...

Fabric Builder

Pin

...

Partitioning

Transformation Engine

Floorplanning Placement Fabric Viewer

Architectural Instance

Structured Circuit Instance

Routing

Circuit Simulator

Physical Layout Tools

Methodology 1. Extensive use of design patterns. 2. Platypus[4], Express based metamodeling environment. 3. Generation of multi-target models and APIs. → Exchangeable models; → API-based instance creation (for existing and prospective nanofabrics);

Generic, modular, pluggable set of tools built around the circuit and architectural models. The open framework model enables the possibility of highly specialized tools to coexist with the general purpose one. Express and equivalent UML definition of the Architectural Model

Simple circuit floorplan in N A B OO

Conclusions and Future work Results

Conclusions and Future work

• N A B OO, preliminary working prototype placing circuits on NASIC fabric. • TCG-S[3] floorplanning algorithm implementation integrated in N A B OO. • Nanofabric constraints integrated via customized cost functions.

The evolution of the computing architectures forces also the evolution of CAD tools. In the context of nanofabrics the tools must be able to cope with a huge number of relatively regular structures, they should integrate support for: 1. fault tolerance, 2. nano/CMOS application partitioning. The preliminary N A B OO implementation proved the viability of a MDA-based generic framework targeting application physical design automation on nanofabrics. N A B OO, in the future: • Rich set of generic tools for physical design;

Area and runtime comparisons between the reference TCG-S and our implementation for area optimization.

MCNC Circuit apte xerox hp ami33 ami49

Reference TCG-S N A B OO implementation Area (mm2) Time (sec) Area (mm2) Time (sec) 46.92 1 46.92 1 19.796 5 20.386 1 8.947 7 9.574 5 1.185 84 1.678 110 36.398 369 58.44 401

• Integration of defect maps and other defect tolerance techniques; WISP-0 Decoder mapped on a NASIC nanotile

References [1] C. Dezan, L. Lagadec, M. Leuchtenburg, T. Wang, P. Narayanan, and C.A. Moritz. Building CAD Prototyping Tool for Emerging Nanoscale Fabrics. European Nano Systems, 2007. [2] L. Lagadec. Abstraction, modlisation et outils de CAO pour les architectures reconfigurable. PhD thesis, Universit´e de Rennes 1, 2000. [3] J.-M. Lin and Y.-W. Chang. TCG-S: Orthogonal Coupling of P*-admissible Representations for General Floorplans. 39th Design Automation Conference (DAC’02), 00:842, 2002. [4] A. Plantec and V. Ribaud. PLATYPUS : A STEP-based Integration Framework. In 14th Interdisciplinary Information Management Talks (IDIMT-2006), September 2006. [5] T. Wang, M. Ben-Naser, Y. Guo, and C. A. Moritz. Wire-Streaming Processors on 2-d Nanowire Fabrics. NSTI Nanotech’05., 2005.

• Extended architectural support for nanofabrics (architectural modeling and tool support);

Contacts: Lab-STICC - Architectures et Syst`emes (D´ept. d’Informatique) 20 Avenue Victor Le Gorgeu BP808 Brest 29285, FRANCE http://as.univ-brest.fr Tel: +33 2 98 01 62 15