IBM SRDC

Channel Strain Engineering For High Performance CMOS Technology Hasan M Nayfeh 45nm Technology Team IBM SRDC 2008 IEEE RTP Conference Workshop Strain-Enhanced Mobility and Advanced Channel Materials Tuesday September 30, 2008 Las Vegas, Nevada

Hasan M. Nayfeh, IBM SRDC

© 2006 IBM Corporation

IBM SRDC

Outline

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45-nm Technology Background (Performance requirements and challenges of strain engineering with ground-rule scaling from 65nm to 45nm technology)




Hole transport physics in nanoscale pFETs under high strain (GPa regime) (Mobility vs. strain and correlation to injection velocity, role of strain in increasing the thermal velocity).




Conclusions

H. M. Nayfeh, IBM SRDC

© 2008 IBM Corporation

IBM SRDC

Background: 45nm High Performance Logic SOI Technology through Strain Engineering at IBM SRDC

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H. M. Nayfeh, IBM SRDC

© 2008 IBM Corporation

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Review of Strain Engineering at IBM SRDC NFET Tension

PFET Compression

90nm Industry first DSL IEDM 2004

Tension

Compression

65nm DSL + eSiGe + SMT with SMT 4

eSiGe H. M. Nayfeh, IBM SRDC

IEDM 2005 © 2008 IBM Corporation

IBM SRDC

Review of Strain Engineering at IBM SRDC NFET Tension

PFET Compression

90nm Industry first DSL IEDM 2004

Tension

Compression

65nm DSL + eSiGe + SMT with SMT 5

eSiGe H. M. Nayfeh, IBM SRDC

IEDM 2005 © 2008 IBM Corporation

IBM SRDC

Performance Degradation with Pitch Scaling (65 - > 45 nm technology ground rules) 65nm

Migration from 65 to 45nm GR results in decreased channel strain •~10% pFET degrade. •~5% nFET degrade. Experimental Data

45nm

45 nm 65 nm

Scaling to smaller gate pitch reduces stressor effectiveness. To overcome this loss and maintain the 45nm performance roadmap: enhance and extend both DSL and eSiGe.

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H. M. Nayfeh, IBM SRDC

© 2008 IBM Corporation

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45-nm technology pFET device “Pushing strain to the limit” Relative to the 65nm gen-II deviceSilicon Nitride Strain liner (CSL)

(1) Close Proximity of the eSiGe stressor to the channel Proximity reduced resulting in 40% stress increase. This stress increase results in 15% Id,sat increase. (2) Deeper eSiGe Cavity: Tsoi substrate increased. The channel stress increase is 25% resulting in 7% Id,sat increase. (3) CSL stressor The silicon nitride stressor increased increased by 15% translating into 3-4% Id,sat increase.

eSiGe •2X-fold increase in channel stress compared to 65nm pFET. Id,sat enhancement over 65nm gen-II pFETs is ~25%. (δ δId,sat/Id,sat ~ 0.25 δσ/σ δσ σ)

The hole mobility for the 45nm eSiGe device is 4X-fold increased over unstrained-Si control. This is achieved by employing 2 stressors with the methodology outlined above: (1) eSiGe and (2) CSL resulting in a composite longitudinal channel stress value determined to be ~1.6GPa. 7

H. M. Nayfeh, IBM SRDC

© 2008 IBM Corporation

IBM SRDC

DSL Film Enhancement

DSL Film

Stress Level (Normalized)

2.0 1.8

Compression Liner Film

1.6 1.4 1.2

Tension Liner Film

1.0 Initial DSL

0.8 0

90nm-II 65nm 65nm-II 45nm 1 2 3 4

5

Since DSL introduction, stress has been enhanced: • 1.9X for PFET film • 1.4X for NFET film

Technology Node 8

H. M. Nayfeh, IBM SRDC

© 2008 IBM Corporation

IBM SRDC

SOI Thickness - eSiGe Compatibility

Channel Stress (Normalized)

eSiGe Depth PFET

1.60 1.50 1.40 1.30

eSiGe Depth

1.20

BOX

1.10

Typical SOI

Sub

1.00 0.90 0

50

100

150

SiGe Depth (nm)

9

SOI

H. M. Nayfeh, IBM SRDC

Typical SOI thickness captures essentially all of the eSiGe stress in the channel © 2008 IBM Corporation

IBM SRDC

eSiGe Enhancement Through Close Proximity

eSiGe Proximity Stress Level (Normalized)

1.5 1.4 eSiGe

1.3 1.2

Close

Far

1.1 1.0

Far

0.9 0

10

20

30

eSiGe to Channel Proximity (nm) 10

H. M. Nayfeh, IBM SRDC

Close

Reducing eSiGe proximity increases channel stress 1.4X © 2008 IBM Corporation

IBM SRDC

µXRD Analysis of SiGe Layer

Intensity (Normalized)

1.0E+04

Si 1.0E+03

SiGe sample measured after processing

1.0E+02

(004) and (224) scans show that eSiGe is fully strained

1.0E+01 1.0E+00

SiGe

1.0E-01 1.0E-02

Reciprocal Units

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H. M. Nayfeh, IBM SRDC

© 2008 IBM Corporation

IBM SRDC

45-nm Technology FET Response

1.E-04

PFET

NFET

Ioff (nA/um)

1.E-05 1.E-06 1.E-07

AC Value

Idsat at Ioff = 200nA/um • NFET 1310 uA/um (AC) • PFET 882 uA/um (AC) S. Narasimha, K. Onishi, H. M. Nayfeh, et al. “High Performance 45-nm SOI Technology with Enhanced Strain, Porous Low-k BEOL, and Immersion Lithography”, 2006 IEEE Electron Devices Meeting (IEDM)

1.E-08

Vdd 1.0V 1.E-09 500

700

900

1100

1300

1500

Idsat (uA/um) 12

H. M. Nayfeh, IBM SRDC

© 2008 IBM Corporation

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Hole transport under high levels of strain

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H. M. Nayfeh, IBM SRDC

© 2008 IBM Corporation

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Transport Study: two devices with large stress difference eSiGe device => (1 GPa stress)

non-eSiGe device => (500 MPa stress)

CSL

CSL

eSiGe

Strict requirements for transport study(1) Matched Rext and overlap capacitance (challenging due to different dopant diffusion coefficients for SiGe) (2) Matched Vt,sat and tinv (3) Longer gate lengths in order to have Rext << Rchannel 14

H. M. Nayfeh, IBM SRDC

© 2008 IBM Corporation

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Diode Leakage Characterization 1 0.1 0.01 0.001 0.0001 1E-05 1E-06 1E-07 1E-08 1E-09 1E-10 1E-11 1E-12 1E-13 1E-14

Current [A]

non-eSiGe eSiGe

-1

-0.5

0

0.5

1

SiGe extends into the depletion region

Voltage [V]

Incorporation of eSiGe stressor results in 100X increase in forward leakage and 10X increase in reverse leakage. This behavior is consistent with increased intrinsic carrier concentration (ni) due to 100mV reduced bandgap for Si0.8Ge0.2 versus Si. Due to this diode leakage behavior, the SOI body voltage of a SiGe pFET device is lower than a non-eSiGe control. 15

H. M. Nayfeh, IBM SRDC

© 2008 IBM Corporation

IBM SRDC

Electrostatics: DIBL and threshold voltage 1.E-02

DIBL (non-eSiGe)

1.E-03

DIBL (eSiGe)

250 DIBL [mV/V]

Ioff (non-eSiGe)

200

1.E-04

Ioff (eSiGe)

1.E-05

150

1.E-06

100

1.E-07

50

1.E-08

0

1.E-09 30

35

40

45

50

55

Off-Current [A/um]

300

60

Effective Channel Length [nm]

Due to less floating body effects, the DIBL for the eSiGe devices is less than the Si controls by ~50 mV/V and is attributed to the diode leakage behavior. In order to match the Ioff vs Leff curve of the SiGe devices to Si, a 15% reduced channel halo dose was utilized. The Vt,sat versus Leff shows are closely matched for the eSiGe and non-eSiGe control. 16

H. M. Nayfeh, IBM SRDC

© 2008 IBM Corporation

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Low-lateral electric field mobility enhancement extraction

dRon tinv = dLeff ε ox (Vgs − Vt ) µ

(dRon

Vds=50mV Vgs-Vt=0.8 V W=3 µm

) µ1 dLeff 1 tinv1 = µ 2 (dRon ) 2 tinv 2 dLeff

Channel stress shown to vary by less than 3% for the length regime studied (35-55nm). Rext for the eSiGe and non eSiGe device is well matched at 150 Ω∗µm Mobility enhancement measured to be 1.75X-fold and varies weakly with varying effective channel length. 15% increased halo dose has little impact on the vertical electric field for this high vertical electric field used in the measurements. 17

H. M. Nayfeh, IBM SRDC

© 2008 IBM Corporation

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Channel Stress simulations- eSiGe and compressive liner stressors Cut taken near the

Sxx (dynes/cm2)

0.0E+00 -4.0E+09

gate insulator interface

7.5nm proximity 12.5nm proximity PC

-8.0E+09 -1.2E+10 -1.6E+10 0.10

0.11

0.12

0.13

0.14

position (um)

• Stress distribution is non-uniform, increasing toward source and drain •Devices with wide range of stress fabricated and simulated from relaxed to 1.6 GPa

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H. M. Nayfeh, IBM SRDC

© 2008 IBM Corporation

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Mobility Enhancement versus channel strain (100) Si wafers

µ µo = 1+ ∏ σ xx xx µ

=> relaxed-Si

o

∏ xx ⇒ Effective piezo-coefficient

σ xx

⇒ Longitudinal stress {110} direction

Mobility enhancement approaching 4X-fold over relaxed-Si control (σxx=1.6 GPa) 3 distinct stress regimes

(1) σ xx < 1GPa

∏ xx=> Consistent with low strain Smith coefficients (0.71 GPa-1)

(2) 1GPa <σ xx < 1.5GPa

∏ xx=> Increased PZ coefficient towards (2 GPa-1).

(3) σ xx > 1.5 GPa

∏ xx => 6 band k*p calculations predict saturation

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H. M. Nayfeh, IBM SRDC

© 2008 IBM Corporation

IBM SRDC

Physical Mechanisms for enhanced hole mobility at high strain Six-band k*p calculations (valence band)

Confinement at high vertical electric field

Thompson et al. IEEE T-ED Vol. 53. No. 5

Relaxed-Si

Valence Band

Strained-Si (σ σxx =1 GPa)

Top band 0.59mo (50%)

Top Band 0.12mo (80%)

Second band 0.15mo (50%)

Second Band 0.61mo (20%)

Mass reduction of 1.75X

Etop Esecond

40-50 meV

σxx 0.5-1 GPa Eopt=63 meV Comparable to splitting energy!

The measured mobility enhancement over relaxed-Si is ~2X for 1 GPa stress.  In addition to reduced mass driving the mobility enhancement mechanism, decreased interband scattering contributes also.

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H. M. Nayfeh, IBM SRDC

© 2008 IBM Corporation

IBM SRDC

Calculation of the injection velocity, Vxo φvalence

Silicon Nitride Strain liner (CSL)

vth

Vxo

SiGe

xo

eSiGe

x

( I D / W ) = Coxinv (VG − Vt )v Injection velocity

v=

v xo [1 + Coxinv RsW (1 + 2δ )v xo ]

Rs- source parasitic resistance, Rext/2 Cox(inv)=3.9εox /tinv, tinv ~ 21A

δ: DIBL 21

A. Khakifirooz, D. A. Antoniadis IEDM Tech Dig. p. 667, 2006

H. M. Nayfeh, IBM SRDC

© 2008 IBM Corporation

IBM SRDC

Saturation Drain Current versus effective channel length

pFET devices with Rext=300 Ω∗µm

∂I d , sat I d , sat ∂I d , sat I d , sat

= 0.25

∂σ xx

σ xx ∂µ = 0.33 µ

Saturation drive current versus gate length. The eSiGe pFETs show a 25% increase for Id,sat at fixed Leff due to a 100% increase in strain (2X-fold increase) at a supply voltage of Vdd= 1V. 22

H. M. Nayfeh, IBM SRDC

© 2008 IBM Corporation

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Injection Velocity versus effective channel length

Injection velocity versus Leff. The eSiGe devices show ~45-50% increase over the non-eSiGe controls at fixed Leff. 23

H. M. Nayfeh, IBM SRDC

© 2008 IBM Corporation

IBM SRDC

How close to the thermal limit?

B=

v xo => Ballistic Coefficient vth M. Lundstrom IEEE EDL Vol. 22, p. 293, 2001

If B=1, device at the thermal limit

∂v xo ∂µ = [α + (1 − B)(1 − α + β )] µ vxo

vth ~ µ α

vth

=> Thermal velocity

β : power law coefficient relating critical Natori et al. Ballistic/Quasi-Ballistic Transport in Nanoscale Transistor

length for backscattering (length necessary to drop kT/q voltage to low-field mobility. A. Khakifirooz, D. A. Antoniadis, IEDM 2006

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H. M. Nayfeh, IBM SRDC

© 2008 IBM Corporation

IBM SRDC

How close to the thermal limit?

Lots of room to improve!

Vxo~9x106 cm/sec @ Leff=35nm Vth~1.5x107 cm/sec for high strain pFET devices Therefore, the ballistic coefficient is ~0.60

•Ballistic coefficient versus Leff B ~0.60 (60% of the thermal limit). for Leff=35 nm. •The coefficient is a weak function of Leff, and α < 0.50 is required implying reduced interband scattering in addition to reduced conductive effective hole mass under high strain. 25

H. M. Nayfeh, IBM SRDC

© 2008 IBM Corporation

IBM SRDC

Future Technology Projections (PFET focus) down to the 12nm node

Injection Velocity [cm/sec]

4.00E+07 3.50E+07

Injection Velocity

This plot assumes-

3.00E+07

(1)

External resistance will remain equal to the 45nm node

2.50E+07

(2)

Inversion charge will remain equal to the 45nm node (Tinv of 19A) highK material assuming mobility transparency

2.00E+07

will help to relax the injection velocity requirements.

1.50E+07 1.00E+07 5.00E+06 0.00E+00 0

10

20

30

40

50

60

70

Technology Node [nm]

Performance Requirement: 17%/year (34%/technology node) From theoretical k*p calculations, highly strained PFETs (1%/1.6GPa) saturate with a thermal velocity of 1.5E7cm/sec. Technologies beyond the 22nm node will require injection velocity greater than the thermal limit of highly strained holes For such nodes, novel materials will be required with significantly higher Vth. Such material also need to deliver sufficient inversion layer charge (low in-plane mass, but sufficient density of states mass). Circuit and system architecture improvements (3D CMOS integration) will likely need to be introduced to alleviate these incredible injection velocity requirements 26

H. M. Nayfeh, IBM SRDC

© 2008 IBM Corporation

IBM SRDC

Conclusions

 Longitudinal compressive stress in the GPa regime is required for the 45nm SOI high-performance pFET device to meet aggressive performance goals.

 Compressive stress liner, and eSiGe stressor enhancement was employed in order to achieve a 1.6 GPa channel stress level.

 Mobility enhancement of the 45nm baseline device is shown to be 4X-fold higher

than relaxed-Si. Effective piezo-cofficients extracted for wide range of stress highlighting 3 stress regimes. Stress and drive current are shown to be correlated with a coefficient equal to ~ 0.25.

 Low-field mobility is shown to be strongly correlated to injection velocity. High

strain pFET devices with gate length down to 35nm operate at about 60% of the thermal limit.

 Challenge for future technology nodes- the mobility vs stress relationship for

channel stress levels in the 1.6GPa regime is approaching saturation. To continue this incredible rate of performance increase (17%/year), methods of increasing the low-field mobility through increased thermal velocity is required.

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H. M. Nayfeh, IBM SRDC

© 2008 IBM Corporation