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Digital System Test and Testable Design: Using HDL Models and Architectures Z. Navabi, 2011

Basic of Test and Role of HDLs • In this chapter we try to answer some of the

Chapter 1

important questions about digital system testing: • What it is that we are testing in digital system

Basic of Test and Role of HDLs

• What are the methods that we use for testing? • What are the ways of making a chip or a

test, test and why we are testing it?

manufactured device more testable?

Zain Navabi

• How HDLs can help the test process?

Slides prepared by: Majid Namaki

Digital System Test and Testable Design - Copyright Z. Navabi, 2011

Basic of Test and Role of HDLs

Basic of Test and Role of HDLs

(Outline) • Design and Test

(Outline) • Testability Hardware Evaluation • Protocol Aware ATE

• RTL Design Process • Postmanufacturing Test

• ATE Architecture and Instrumentation

• Test Concerns • • • •

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• • • • •

Test Methods Testability Methods Testing Methods Cost of Test

Digital Stimulus and Measure Instruments DC Instrumentation AC Instrumentation RF Instrumentation ATE

• Summary

• HDLs in Digital System Test • Hardware Modeling • Developing Test Methods • Virtual Testers Digital System Test and Testable Design - Copyright Z. Navabi, 2011

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Digital System Test and Testable Design - Copyright Z. Navabi, 2011

Basic of Test and Role of HDLs

Design and Test

• • • • •

• Producing a digital system:

Design and Test Test Concerns HDLs in Digital System Test ATE Architecture and Instrumentation Summary

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• Begins with a designer specifying his or her design in a high-level design language

• Ends with manufacturing and shipping parts to the customer • This process involves many simulations, synthesis, and test phases h

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RTL Design Process • • • •

Device and Its Test Data • In digital system testing, device being tested can be:

RTL Simulation RT Level Synthesis

• • • • • • •

Physical Layout Chip Manufacturing

a system a board a packaged chip a chip a die on a wafer a core on a die a section of a core

• Regardless of what it is that is being tested, it is treated as a closed box • It can only be controlled and observed from the outside

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Digital System Test and Testable Design - Copyright Z. Navabi, 2011

Device and Its Test Data

Testers

• • • • •

• A tester is a device or equipment that applies test

Device Under Test (DUT) or Circuit Under Test (CUT) Test Vector or Test Pattern Test Set Stored Response Test Generation

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vectors to a DUT, collects DUT’s responses, and makes comparisons with the expected data

• Functional • Structural

• Good Circuit Model or Golden Model

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Digital System Test and Testable Design - Copyright Z. Navabi, 2011

Test Board

A DUT Testing Itself

• Test board on a system takes

• A DUT without requiring an external chip or device,

responsibility for testing other system boards and chips mounted on the boards

can be tested by a built-in hardware that has been primarily designed for testing the rest of the hardware of the DUT.

• It communicates through a test

• Built-in Self-test (BIST)

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bus with b i h other h bboards d in i the h system for testing them

• The test board consists of storage, memory, processors, and communication busses

Digital System Test and Testable Design - Copyright Z. Navabi, 2011

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Digital System Test and Testable Design - Copyright Z. Navabi, 2011

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Automatic Test Equipment

UltraFLEX tester

• An ATE is an equipment that consists of processors, storage, and fixtures for mounting devices

• ATEs are used for • Die testing • Wafer testingg • Testing a packaged product

• An ATE runs a test program that implements the specific procedure designed for testing the DUT • Multisite Testing Capability • Concurrent Testing Courtesy of Teradyne Digital System Test and Testable Design - Copyright Z. Navabi, 2011

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Digital System Test and Testable Design - Copyright Z. Navabi, 2011

Using Test Results

Types of Tests

• The manufacturing defects can either cause catastrophic

• • • • • • • • • • •

failure or parametric failure • The test results: • Can impact the product itself, the design process, or the implementation of the design

• Can be used to identify functionalities whose failures do not necessarily make a device unusable

• May impact the design and implementation process

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External Testing Internal Testing Online Testing Offline Testing Concurrent Testing (Online) Concurrent Testing (ATE) At-Speed Testing DC Testing In-Circuit Testing Guided Probe Testing Diagnostic

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Digital System Test and Testable Design - Copyright Z. Navabi, 2011

Basic of Test and Role of HDLs

The need for Test Methods

• • • • •

• • • •

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Example

Design and Test Test Concerns HDLs in Digital System Test ATE Architecture and Instrumentation Summary

64 inputs 64 outputs 12 ns internal delay Tester running at 1 GHz clock frequency • 4 clock cycles (4 ns ) to fetch a new test vector

Test time : 264 × (12 + 4 + 4) ×10−9 s = 11,698 years!!!

Digital System Test and Testable Design - Copyright Z. Navabi, 2011

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Digital System Test and Testable Design - Copyright Z. Navabi, 2011

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Test Methods

Test Methods: Fault Model

• In digital system testing, a set of algorithms and methods

• To simplify defects that we are trying to test for, we

help reduce the number of test vectors by selecting them more wisely than just trying every combination: • • • • • • •

develop a fault model • The fault model that we use is only a model to simplify analysis of a circuit for finding better test vectors and evaluating them

Simplify faults that can occur Use a reduced number of faults Find mechanisms for evaluating test vectors Find parts of circuit that are harder to test Generate tests that target hard to test areas Evaluate test vectors and keep more efficient ones

• Based on this model we define fault coverage as the percentage of faults that have been detected. • For a given test vector, fault coverage determines its efficiency in the number of faults it can detect.

Compact test vectors

Digital System Test and Testable Design - Copyright Z. Navabi, 2011

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Digital System Test and Testable Design - Copyright Z. Navabi, 2011

Test Methods: Fault Reduction

Test Methods: Fault Simulation

• We try to reduce the number of faults that we deal

• A test vector or a test set is graded by the number of

with by:

faults it detects

• Eliminating redundant ones • Ignoring some that do not occur often

• To find this number, a fault is introduced in the circuit we are testing, and tests are applied to see what faults it detects

• The circuit in which a fault is introduced is called a faulty

• Reducing number of faults can be incorporated in our fault model, i.e., using a simple model consisting of very few fault types • In addition, reducing can be done by eliminating faults that have the same output effect; this process is referred to as fault collapsing

Digital System Test and Testable Design - Copyright Z. Navabi, 2011

model, and simulating this circuit is referred to as fault simulation • It is the most important test method, and it is computationally very complex

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Digital System Test and Testable Design - Copyright Z. Navabi, 2011

Test Methods: Testability Measurement

Test Methods: Test Generation

• Controllability is defined as the ease of controlling a line

• What we use for generating an efficient test set:

in a circuit • Observability is the ease of observing the effect of its value on a primary output • Test methods for controllabilityy and observabilityy analysis are used in the test generation process. • Testability measurement refers to calculation of these parameters.

Digital System Test and Testable Design - Copyright Z. Navabi, 2011

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• Simplified fault model, • Having tools and methods for evaluating a test vector or a test set,

• Being able to identify hard to reach areas of a circuit

• Various test generation methods and algorithms, ranging from pure random to deterministic

• Repeated use of fault simulation in test generation and its np-complete algorithms make this test method computationally complex

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Digital System Test and Testable Design - Copyright Z. Navabi, 2011

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Test Methods: Test Compaction

The need for Testability Methods

• Test compaction tries to reduce the number of test

• • • •

Example

vectors without significantly affecting the fault coverage of a test set • A more compact test set tests a CUT quicker

64 bit counter Clock rate of 1 GHz 1 clock cycle to generate new count 5 clock cycles to read its output

Test time : 264 × (1+5) ×10−9 s = 3,509 years!!! Digital System Test and Testable Design - Copyright Z. Navabi, 2011

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Digital System Test and Testable Design - Copyright Z. Navabi, 2011

Example

Testability Methods: Ad Hoc Testability

• Partitioning into smaller counters (four 16-bit counters)

• Some of what we can immediately think of in terms of

The need for Testability Methods

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making a circuit testable

• Normal mode: NbarT = 0 • Test mode: NbarT = 1

• Adding extra output pins to observe internal nodes of a CUT • Adding a jumper to make certain parts of a CUT more controllable and/or observable

• Partitioning, input/output pins • Multiplexing inputs and outputs are

Test time : 216 × (1+5) ×10−9 s = 0.4 ms

Digital System Test and Testable Design - Copyright Z. Navabi, 2011

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Digital System Test and Testable Design - Copyright Z. Navabi, 2011

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Testability Methods: Scan Insertion

Testability Methods: Boundary Scan

• A method of turning a sequential circuit into a

• To isolate a core on a chip and test it, independent of its

combinational circuit

surroundings

• Used for board level testing, chip and core level testing

• Making it accept combinational test methods

• Scan methods make the internal registers of a sequential circuit look like inputs and outputs, and form a combinational model for the circuit. • Scan methods are the most important testability methods for today’s digital design and test methodology

Digital System Test and Testable Design - Copyright Z. Navabi, 2011

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Digital System Test and Testable Design - Copyright Z. Navabi, 2011

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Testability Methods: BuiltBuilt-in Self Self--test

Testing Methods

• BIST is a testability method that involves adding a semi-

• Another aspect of testing that can also improve and

processing unit to a CUT, with the sole responsibility of testing various parts of the CUT that it shares chip area with • BISTs save test time by:

speed up the testing process is by using smarter and faster testers (ATE) • ATE industry is looking at ways of incorporating the use of HDL in their ATEs for improving test speed

• Not having to pull a component out of its mounting for testing • Interlacing testing with normal operation of a CUT

• This will result in a better understanding of test engineering

Digital System Test and Testable Design - Copyright Z. Navabi, 2011

issues by the designers; and at the same time, it makes test engineers get more involved in the design process and early testing of designs

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Digital System Test and Testable Design - Copyright Z. Navabi, 2011

Cost of Test

Cost of Test: Rule of 10

• Keeping cost to a level to make production profitable,

• Cost of detecting a fault increases by a factor of 10

and still be able to deliver right parts for the right markets • Test strategy: Incorporation of testing in the design development cycle so that a device gets the right test, at the right time, and with the right level of completeness

Digital System Test and Testable Design - Copyright Z. Navabi, 2011

when going from one level to the next higher level

• Detect faults as early as possible in the design process

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Digital System Test and Testable Design - Copyright Z. Navabi, 2011

Cost of Test Test:: Chip Testing

Basic of Test and Role of HDLs

• High-volume test is performed using ATE, along with

• • • • •

equipment to transport either a wafer or a device package to the ATE • The cost of test (COT) added to the overall cost of producing the part is generally calculated as:

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Design and Test Test Concerns HDLs in Digital System Test ATE Architecture and Instrumentation Summary

(cost of equipment + operating costs/number of devices tested)

Digital System Test and Testable Design - Copyright Z. Navabi, 2011

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HDLs in Digital System Test: Hardware Modeling

HDLs in Digital System Test: Developing Test Methods

• Analyzing a circuit for test purposes requires a

• We can use procedural constructs and capabilities of an

hardware model

HDL, and use it as a software programming language to process the CUT model and perform tasks that are related to test

• For testability purpose, describing the CUT and its testability hardware in an HDL produces a simulation model that can be analyzed for the effectiveness of the testability method

• Example: Use of an HDL for generating random test vectors, applying to the l i them h h CUT, CUT and d sorting i the h test vectors according di to their effectiveness in terms of detecting faults

Digital System Test and Testable Design - Copyright Z. Navabi, 2011

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Digital System Test and Testable Design - Copyright Z. Navabi, 2011

HDLs in Digital System Test: Virtual Testers

HDLs in Digital System Test: Testability Hardware Evaluation

• An HDL testbench that mimics a tester, with the

• Evaluating hardware that is to be added to a CUT for

additional capability of being able to manipulate the CUT for studying its testability or changing parameters for making it a more testable circuit

making it testable, by another device, or by itself • An HDL testbech can take responsibility for instantiating a CUT and its associated preliminary BIST, and simulating and adjusting BIST register lengths and configurations for a more efficient testing of the CUT

• To properly play its role as a tester, a virtual tester can be allowed ll d only l to interact i with i h the h CUT through h h its i test ports

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HDLs in Digital System Test: Protocol Aware ATE

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Basic of Test and Role of HDLs

• A recent addition to ATE industry is the use of HDLs

• • • • •

for programming a tester for testing a DUT • Instead of using predefined bit patterns to test a CUT, specialized hardware (typically FPGA-based) is embedded in the tester hardware to directly interpret HDL commands, construct data input patterns on on-the-fly the fly, and adopt to variations in CUT output timing and data content

Digital System Test and Testable Design - Copyright Z. Navabi, 2011

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Design and Test Test Concerns HDLs in Digital System Test ATE Architecture and Instrumentation Summary

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ATE Instrumentation

ATE Architecture

• • • •

• ATE from different vendors is differentiated on

Digital Stimulus and Measure Instruments DC Instrumentation AC Instrumentation RF Instrumentation

Digital System Test and Testable Design - Copyright Z. Navabi, 2011

measurement capability and device throughput. The architecture of the tester must achieve certain goals: • Minimize hardware setup time • Optimize instrument handshaking • Minimize data post processing time

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UltraFLEX ATE

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Summary

• Hybrid air/liquid cooled test head

This chapter discussed some of the very basic concepts of test: • Why test is needed? • Why we need methods for test and methods for makingg circuits testable? • The role of ATEs in test This chapter showed how hardware description languages can be used in all aspects of digital system testing

with universal slots

• 24-slot standard capacity (-SC) test head , and a 36-slot high capacity (HC) test head I Offers Off di i l speed d and d pin i count • It digital needed for multisite test applications of SoC and SiP devices operating at greater than 200 MHz

• It

has a mainframe cabinet containing the power distribution unit, heat exchanger for liquid cooling, air-cooling resources, clock reference, and an integrated manipulator

Digital System Test and Testable Design - Copyright Z. Navabi, 2011

Courtesy of Teradyne

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