APPLIED PHYSICS LETTERS 91, 133510 (2007)

Characteristic trapping lifetime and capacitance-voltage measurements of GaAs metal-oxide-semiconductor structures. Guy Brammertza), Koen Martens, Sonja Sioncke, Annelies Delabie, Matty Caymax, Marc Meuris, Marc Heyns Interuniversity Microelectronics Center (IMEC vzw), Kapeldreef 75, B-3001 Leuven, Belgium.

Abstract The authors show the implications that the free carrier trapping lifetime has on the capacitance-voltage (CV) characterization method applied to metal-oxidesemiconductor (MOS) structures. It is shown that, whereas the CV characterization method for deducing interface state densities works well for Si, the generally used frequency range 100 Hz – 1 MHz is much less adapted to GaAs MOS structures. Only interface trapping states in very small portions of the GaAs bandgap are measured with this frequency range and mainly the very important mid-gap region is not properly probed. Performing an additional measurement at 150°C on GaAs-MOS structures eliminates this problem.

Alternative channel materials such as Ge and GaAs with inherently higher carrier mobility than Si are currently being considered as possible channel materials for complementary metal-oxide-semiconductor (CMOS) transistor circuits, in order to extend the Si roadmap beyond the 22-nm node1. In order to characterize the amount of trapping states at the oxide-semiconductor interface, all researchers in the field use well known capacitance-voltage (CV) characterization methods, which in the past 30 years have proven to be a very efficient technique for characterizing Si-oxide interfaces2. Nevertheless, very fundamental limitations of the techniques are not well known in large parts of the research community anymore, which leads to some confusion when applying the methodology to GaAs-MOS structures. The problems of applying the capacitance-voltage characterization techniques to GaAs MOS structures were already discussed in detail in reference 3. In the following, we will re-discuss the basic phenomenon allowing for interface state density determination from CVmeasurements, free carrier trapping and de-trapping, and explain the consequences of the strong dependence of the trapping time on the energy depth of the traps within the semiconductor bandgap. We will then apply this knowledge to experimental data obtained from the HfO2/GaAs system and demonstrate that measurements at 150°C

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are necessary to complement the room temperature data in order to gather information about the mid-gap density of states. The characteristic time τ with which a free charge in a semiconductor gets trapped by a trapping state of energy Et can be determined from standard Fermi-Dirac statistics and is given by4: exp(∆E / kT ) τ= , (1) σvt N where ∆E is the energy difference between the majority carrier band edge energy and the trapping state energy Et, k is the Boltzmann constant, T is the semiconductor temperature, σ is the interaction cross section of the trapping state, vt is the thermal velocity of the majority charge carriers and N is the density of states in the majority carrier band. From this characteristic time τ, one can derive the characteristic response frequency f=1/2πτ of the corresponding trapping state. Figure 1 shows this characteristic trapping frequency for electrons (solid line) and holes (dashed-dotted line) in Si (a) and GaAs (b) as a function of the energy of the trapping state within the bandgap, calculated using the parameter values from table I5 (Possible deviations of the parameter values from the values in table I do not alter the conclusions, because it is mainly the exponential term, which has the largest influence on the characteristic trapping time). Zero on the horizontal axis corresponds to the valence band edge energy EV, whereas the right edge of the axis represents the conduction band edge energy EC. The horizontal dashed lines represent the frequency range generally accessible for CV-measurements, 100 Hz to 1 MHz. Only trapping states with characteristic frequencies lying within this range will contribute to the typical interface trap signature, a frequency-dependent CV component in the measurement. All trapping states with characteristic frequencies larger than 1 MHz are too fast to produce this frequency-dependent component, whereas the trapping states with characteristic frequencies lower than 100 Hz are too slow to contribute to this typical frequency dependent component. Looking at the energy range within the bandgap, where the measurable trapping states reside, one can see that in Si a large part of the bandgap can be measured with the CV characterization method. MOS structures on ptype Si can probe interface trapping states lying 0.25 eV to 0.55 eV above the valence band edge, whereas MOS structures on n-type Si can probe interface trapping states lying 0.55 eV to 0.8 eV above the valence band edge. In total a very large part of the bandgap in Si can therefore be probed for interface trapping states. Only the very fast states near to the band edges are not accessible with the usual frequency range of 100 Hz to 1 MHz. Due to the larger bandgap of GaAs, the situation is completely different for GaAs MOS structures. The trapping states near to the mid-gap have very low characteristic trapping frequencies for both electrons and holes. As a consequence, these states can not be probed with the usual frequency range, 100 Hz – 1 MHz. MOS structures on p-type GaAs measure interface trapping states lying 0.25 eV to 0.5 eV above the valence band edge and MOS structures on n-type GaAs measure the states lying 0.95 eV to 1.2 eV above the valence band edge. The mid-gap states lying 0.5 – 0.95 eV above the valence band edge are not accessible to CV-measurements in GaAs MOS. It can therefore very well be that CV measurements show very good behavior without frequency dispersion, indicating low interface states densities, whereas there is still a very large peak in the density of interface states near the mid-gap. Simple assesment of interface state density near mid-gap used routinely for Si at room temperature by simply looking for frequency dispersion in the C-V, or by applying analysis on the frequency dispersive part of the admittance such as with the 2

conductance method2, are therefore not effective at all when talking about GaAs MOS-structures. A possible method to assess these mid-gap interface states, which have characteristic frequencies of the order of 10-2 Hz, is to perform quasi-static CV measurements with integration times of the order of several minutes3. Nevertheless, already the slightest leakage currents introduce a large amount of error in these measurements and secure conclusions on the density of interface states can only be made for devices with extremely low leakage currents. An alternative method to assess the density of mid-gap states (next to photoluminescence intensity measurements3) is to thermally activate them with an increased temperature, so that the characteristic frequencies of the mid-gap states, according to Equ. (1), lie within the accessible frequency range 100 Hz – 1 MHz. Figure 2 shows the corresponding characteristic frequencies of interface trapping states in GaAs at 150°C. It can be observed that at higher temperatures the mid-gap is much better covered by the CV frequency range. In p-type GaAs, interface trapping states lying 0.4 to 0.75 eV above the valence band edge can be measured, and in n-type GaAs, states ranging from 0.75 eV to 1.1 eV can be measured. Also, because of the large bandgap of GaAs, the increased temperature does not generate a large amount of minority carriers, which could introduce parasitic features in the CV-characteristics. Only ~104 minority carriers exist per cm3 in GaAs at 150°C. In addition, at 150°C, leakage currents through the gate oxide are usually not increased considerably either. Figure 3 shows CV measurements performed on the same GaAs capacitor at two different temperatures, 25°C and 150°C, illustrating the statements made in the previous section. The capacitor structure consists of a 5 1017 cm-3 p-type doped GaAs substrate on which 10 nm of HfO2 was deposited using atomic layer deposition (ALD). On top of the oxide, 50 nm thick Pt gate metal dots were deposited through a shadow mask. Ohmic contact to the GaAs was made through the deposition of a AuZn/Au layer on the backside of the substrate and subsequent forming gas anneal at 380°C for 30 s. The diameter of the measured capacitor is 200 µm and the measured capacitances were normalized to the capacitor area in order to facilitate oxide thickness extraction from the accumulation capacitance. For both measurements the leakage currents through the gate oxide are below 0.2 nA. The room temperature measurements show a quite reasonable shape of the CV-curves with quite low frequency dispersion in accumulation. The accumulation capacitance of 1.3 µF/cm2 roughly corresponds to the value expected for 10 nm of HfO2. Applying C-V methods blindly, this might erroneously lead to the conclusion that the interface state density is reasonable around mid-gap energies, of the order of 1012 eV-1cm-2. This is clearly wrong, as is visible from Fig. 1, because at room temperature on p-type material only interface trapping states lying 0.25 – 0.5 eV above the valence band edge are measured and in this region the interface state density might be around the suggested value. The mid-gap states are not assessed with these measurements. The high temperature measurements in Fig. 3 indicate the true nature of the interface state density near mid-gap, with the appearance of large bumps in depletion at the lower frequencies, which are created by interface states near the mid-gap. To conclude we would like to propose a methodology to assess the interface state density in GaAs MOS structures with CV-measurements: On both n- and p-type substrates, MOS capacitors should be measured both at room temperature and at 150°C. If all four measurements in thermal equilibrium show low dispersion of the CV-curves with frequencies varying from 100 Hz – 1 MHz, one can safely conclude 3

that the mid-gap interface state density is low. Extraction of an exact number for the interface state density over the bandgap is not that simple. This necessitates numerical analysis using a model of all relevant phenomena present in the structures, as presented in Refs. 3 and 6.

References:

1

R. Chau, S. Datta, M. Doczy, B. Doyle, B. Jin, J. Kavalieros, A. Majumdar, M. Metz and M. Radosavljevic, IEEE Transactions on Nanotechnology 4, 153 (2005). 2 E. H. Nicollian and J. R. Brews, MOS (Metal oxide semiconductor) physics and technology (Wiley, New York, 1982). 3 M. Passlack, in Materials Fundamentals of Gate Dielectrics (Springer, The Netherlands, 2005) p. 403. 4 W. Shockley and W. T. Read, Phys. Rev. 87, 835 (1953). 5 http://www.ioffe.rssi.ru/SVA/NSM/ 6 K. Martens, B. De Jaeger, R. Bonzom, J. Van Steenbergen, M. Meuris, G. Groeseneken, H. Maes, IEEE Electron Device Letters 27, 405 (2006).

Tables Table I: Parameter values used for the plots in Figs. 1 and 2 (Ref. 5). Property Unit Si GaAs n-type p-type n-type p-type Energy gap

eV

1.12

1.12

1.42

1.42

Capture cross section Thermal velocity

cm cm/sec

10 2.3x107

10 1.6x107

10 4.4x107

10-15 1.8x107

Density of states

cm-3

3.2x1019

1.8x1019

4.7x1017

9x1018

2

-15

4

-15

-15

Figure 1: Characteristic trapping frequency for electrons (solid line) and holes (dashed-dotted line) in Si (a) and GaAs (b) as a function of the interface trap energy within the bandgap. The dashed horizontal lines indicate the frequency range available for CV-measurements, 100 Hz – 1 MHz. The dotted vertical lines indicate the trap energy regions within the bandgap that are actually measured with this frequency range.

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Figure 2: Characteristic trapping frequency for electrons (solid line) and holes (dashed-dotted line) in GaAs at 150°C as a function of the interface trap energy within the bandgap. The dashed horizontal lines indicate the frequency range available for CV-measurements, 100 Hz – 1 MHz. The dotted vertical lines indicate the trap energy regions within the bandgap that are actually measured with this frequency range.

Figure 3: CV measurements performed on a GaAs capacitor with 10 nm of HfO2 used as gate oxide. The diameter of the measured capacitor is 200 µm. The figure on the left shows room temperature measurements, whereas the figure on the right shows the results for measurements performed at 150°C. For both low and high temperature measurements the gate leakage currents of the capacitor are below 0.2 nA for all applied voltages. 6