Characterization and Parameterized Random Generation of Digital Circuits Michael Huttony, J.P. Grossmanz, Jonathan Rose yy, and Derek Corneily

Departments of Computer Sciencey, Mathematicsz and Electrical and Computer Engineeringyy University of Toronto, Ontario M5S 1A4 fmdhutton@cs, jp@eecg, jayar@eecg, [email protected]

Abstract

The development of new Field-Programmed, MaskProgrammed and Laser-Programmed Gate Array architectures is hampered by the lack of realistic test circuits that exercise both the architectures and their automatic placement and routing algorithms. In this paper, we present a method and a tool for generating parameterized and realistic random circuits. To obtain the realism, we propose a set of graph-theoretic characteristics that describe a physical netlist, and have built a tool that can measure these characteristics on existing circuits. The generation tool uses the characteristics as constraints in the random circuit generation. To validate the quality of the generated netlists, parameters that are not speci ed in the generation are compared with those of real circuits, and with those of \random" graphs.

1 Introduction

There is a need for benchmark netlists in order to compare and test the quality of new ASIC architectures and physical design algorithms. However, useful benchmarks are rare|they are usually too small to eectively test large future-generation products, and those large enough are often proprietary. Some attempts to alleviate this problem have been the MCNC benchmarks [10], the PREP benchmarks [8], and the use of random graphs. The use of random graphs is appealing because the supply is in nite, and the circuit size can be speci ed. However, only a small subset of random graphs can be considered reasonable with respect to electrical constraints (such as gate fanin or fanout), topological properties (such as maximum delay) and packaging constraints such as the number of pins. Compared to random graphs, circuits are inherently tame for implementation in gate arrays, and exhibit hierarchical structure which leads to empirical observations such as Rent's Rule1 [7]. In independent work, Darnauer and Dai [3] have proposed a method of generating random undirected graphs to meet a given I/O ratio and Rent parameter [3]. Their work reports results only for small circuits (from 77 to 128 lookup-tables) so it is dicult to evaluate the method's success at achieving the target parameterization because few partition points are available to determine the Rent parameter, r.

1 Rent's Rule: For a \reasonable" partition of a circuit into at least 5 modules, the relationship between the average number P of terminals/pins on a module, rand the average size B of a module follows the relationship P = k  B , where k is a constant and r is the Rent parameter which is a characteristic of the circuit in question.

Circuit Characterization Characteristics and Measured Parameters (n, nPI, nPO, delay, shape, edge−length, fanout dist’n)

Parameters not used in Generation (reconvergence, routed wirelength, track−count)

Circuit Generation Parameterized, Random Circuits

Validation

Generation Quality Measures

Figure 1: Approach to Circuit Generation In this paper we propose a method to generate benchmark circuits, illustrated in Figure 1, which combines the advantages of random graph generation and the realism obtained by using actual circuits. We have de ned a set of graph-theoretic characteristics and parameters of circuits and measured these on real circuits up to 4500 LUTs to form a pro le of realistic circuits. This measurement is done with a new software tool called circ. The pro le is used by a second tool, gen, to generate a random circuit with the speci ed parameters. In this way we produce netlists with the characteristics of realistic circuits, but also have the freedom to vary crucial parameters, including the size of the generated circuit. The interaction between the analysis and generation tools is of fundamental importance: circ can be used to analyze any private collection of circuits and determine alternative pro les for input to gen. In this paper we will validate the quality of the generated circuits by measuring circuit characteristics that are not speci ed in the generation, as illustrated in Figure 1. This system allows for features not possible with standard benchmark sets. For example, one parameter can vary while others are xed or scaled appropriately, to generate a \family" of circuits. In this paper we de ne the new algorithmic problem of random circuit generation with constraints. The circuit generation problem is very dicult and we present a heuristic algorithm to solve it inexactly, in a program called gen. The paper is organized as follows: Section 2 outlines the characterizations of circuits used for generation and validation of the random circuits and Section 3 describes the generation algorithm. We measure and discuss the quality of the generated circuits in Section 4 and then conclude.

2 Circuit Characterization

This section describes some of the statistical and structural characteristics of circuits which we have identi ed. For the purposes of this paper we focus on combinational circuits only, and have used the MCNC benchmark circuits to form the

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Figure 2: Size (2-LUTs) vs. I/O for MCNC circuits. basis for characterization and parameterization. Note that the users of our system could pro le their own circuits with circ and specify the results as parameters to gen (or modify the program default le) to customize the types of circuits generated. 2.1 Pre-processing of Analyzed Circuits. The MCNC benchmark circuits were converted from EDIF to BLIF, optimized with sis [9] (keeping the better result of script.rugged and script.algebraic) then technology mapped using flowmap [2] into k-input lookup tables. Speci cally, each circuit was mapped 7 times, into 2-input LUTs, 3-input LUTs up to 8-input LUTs. We chose to use lookup-tables because of their simplicity, functional completeness and the ease of changing to dierent LUT-sizes. We believe that the structural dierences of circuits are suciently captured by the use of LUTs to determine valid characterizations. 2.2 Characteristics and Parameters. There are two dierent types of characterizations: those needed to determine reasonable defaults for generation parameters which the user does not specify and those which characterize the fundamental structure of a circuit. In the remainder of this section we propose a set of characteristics. 1. Circuit Size and Number of I/Os. The most basic characteristic of a circuit is the relationship between the size of the circuit (number of LUTs, n) and the number of primary inputs (nPI ) and outputs (nPO). (De ne nIO := nPI + nPO.) Using linear regression and experimentation, we have determined that a Rent-like functional relationship, log(nIO) = a + b
log(n) best captures the relationship between IOs and circuit size2 . A simple linear relationship best describes the division of I/Os between inputs and outputs: nPI = c + d
nPO. Figure 2 shows a plot of log(n) vs. log(nIO), and a leastsquares regression line for the Rent-like relationship. We note that simply determining values for the coecients a; b; c; and d does not capture the increase in variance with n so we model these coecients as Gaussian distributions around the best- t line. The actual equations are shown in Figure 10. 2. Combinational Delay. De ne d(x), the delay of node x, as the maximum length over all directed paths beginning at a PI and terminating at x, corresponding to the unit delay model. The delay, d(C ) (or just d), of a circuit is the maximum delay over all nodes in C . Using a similar empirical analysis to the above, we have determined the relationship between delay and circuit size (n).

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Figure 4: Dierent shape functions. 3. Circuit Shape. Combinational delay is very important in the characterization of circuits, precisely because it is so important in the design and synthesis process. De ne the shape function, shape(C ), of a circuit as the vector of the number of nodes at each combinational delay level. Figure 3 shows a small example circuit (cm151a), and its shape function (12, 4, 2, 2) displayed as a histogram. Note that we do not count primary outputs in the shape function. While these examples are mapped to 4-LUTs, the form of the function changes only slightly with the LUT-size. The interesting thing about shape is that most circuits tend to have similar shapes. Figure 4 shows four shape functions. Of the 109 combinational multilevel circuits in the MCNC set, 36 have a shape which is strictly decreasing from the primary inputs (as \example2"), 53 have a \conical" shape, fanning out from the inputs to an extreme point, then strictly decreasing (as \alu2"), 12 have the conical shape with a \bump" and only 8 did not t into these categories. Importantly, this is fundamentally dierent from degree-constrained graphs we generated randomly, which had much \ atter" shapes. 4. Edge Length Distribution. Since nodes have a wellde ned delay, we can de ne the length of a directed edge by length(x; y) = d(y) ; d(x). Clearly, the edge length is always between 1 and delay(C ), and the edge length distribution is well de ned. In the example of Figure 3 there are 24 edges of length 1, and 2 each of length 2 and 3, so the edge length distribution is (24, 2, 2, 0). We nd that almost all circuits have an edge-length distribution with a similar shape: a large number of edges of length 1, and a quickly falling distribution over the combinational delay of the circuit. 5. Fanout Distribution. De ne fanout(x) as the number of edges leaving a node x. A circuit's fanout distribution (the number of nodes with fanout 0, 1, 2, etc.) is an important structural parameter. Note that fanin is less interesting for technology-mapped circuits because they have an a priori constraint on fanin. We have determined the fanout distributions of the MCNC circuits, and have developed an algorithm 2 Note that Rent's Rule explicitly does not apply uniformly for the [5] which generates reasonable fanout distributions given the circuit as a whole (i.e. to predict I/O given n), so we use dierent above size and shape parameters. 6. Reconvergence. Reconvergence occurs when multiple functional forms for ranges of n, determined empirically. The actual relationship is a piecewise combination. See Figure 10. fanouts from a single node x in the circuit branch back to-

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Figure 5: Reconvergence in combinational circuits. gether at a later point y - we say the circuit is reconvergent at y. Many circuits exhibit reconvergent fanout, but in widely varied amounts, and so an appropriate characterization is to quantify this amount. De ne the out-cone of a node x (in a circuit with no directed cycles) to be the recursive fanout of x: all nodes reachable by a directed path from x. Figure 5 shows out-cone(a). De ne the reconvergence number of node x, R(x), as the ratio of the number of fanin-2 (i.e. \reconvergent") nodes in out-cone(x) to the size of out-cone(x). (Note: for simplicity here we de ne reconvergence for 2-LUT mapped circuits only3 .) In the example, R(a) = 3/12 or 0.25. In most sequential circuits, the existence of ip- ops4 could result in back edges and directed cycles, and R(a) would no longer be wellde ned both because the de nition of out-cone is insucient and because the natural extension of counting reconvergent nodes results in overcounting. A more generalized de nition of reconvergence, based on spanning out-trees rather than a simple ratio, takes this into account [5] but it is beyond the scope of this paper. The reconvergence number of an entire circuit is the weighted average (by cone size) of the reconvergence number of the circuit's primary inputs. The reconvergence numbers of the MCNC circuits vary between 0.0 and 0.92 (the theoretical maximum for 2-LUT mapped circuits is 1.0), with a relatively even distribution of circuits through the range 0.0 to 0.85. R is somewhat a measure of complexity of the logic|we nd intuitively simple logical functions have low R, and more complex functions have higher R. Combinational and sequential arithmetic circuits fall mostly in the range 0.0 to 0.5, whereas nite state machines are mostly in the range 0.6 to 0.85. In a physical sense, there is some correlation between R and the shape of a circuit. Using the examples of Figure 4, circuits which have an exaggerated conical shape, such as alu2 (R = :53) and cordic (R = 0:45) tend to have higher reconvergence values, whereas circuits like example2 (R = 0:17) are lower. This also tends to explain the dierence between combinational and sequential circuits because the rst \sequential level" of most nite state machines tends to be very conical, due to a low I/O to logic ratio.

3 Circuit Generation

Figure 6 shows an example output from gen for the parameterization: n=23, k=2, nPI =7, nPO=2, d=5, shape=(.38, .31, .19, .12), fanouts=(.09, .65, .13, .04, .09), edges=(.75, mapped to 4-LUTs is calculated by R x P3vR2 for circuits v x

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Figure 6: Example of a completely parameterized circuit. .25). The gen program consists of two functional stages. The rst is to determine a complete parameterization of the circuit to be generated, using partially-speci ed user parameters and default distributions. The second stage is to output a random circuit with that parameterization, which we deal with rst. 3.1 The Generation Algorithm. The inputs to gen are n, nPI , nPO, (or nIO), d (depth), k (LUT-size), the shape function, and the edge length and fanout distributions. The output is a netlist of k-input lookuptables. Reconvergence is not a generation parameter but we use the reconvergence number of generated circuits in the validation process of Section 4. The input shape function is scaled5 to determine the set N (jN j = n) of all nodes, partitioned into sets Ni (i = 0::d) of nodes at each combinational delay level. The fanout distribution is scaled with n to become the set D of available outdegrees, where dj (j = 1::n) represents the eventual fanout of one node j . This also determines the number of edges m in the circuit. Finally, the edge length distribution is scaled to create the set E of available edges, where length(eh) (h = 1::m) represents the length of edge h. This gives rise to the following combinatorial assignment problem, illustrated in Figure 7.

Circuit Generation Problem

Given: D, Ni , E . Find: assignments of nodes in N to each dj 2 D, and pairs of nodes for each eh 2 E such that: I The number of edges leaving any x 2 N is exactly its corresponding fanout dx . II All x 2 Ni have at least one fanin from Ni;1 (i> 0). (i.e. d(x) equals its assignment.) III Fanin(x)  k for all x 2 N . IV Fanins of x 2 N are distinct (i.e. no two fanouts of gate y are both inputs to x.)

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rather than the simple ratio. Thus 0  R  j xj This assignment problem appears to be computationally log2 (k). A still more complicated de nition is required for sequential 5 First it is scaled to length d by linear interpolation, then adjusted to circuits|see [5]. 4 Nodes g and j are ip- ops, but they do not have edges which form ensure there are sucient nodes or POs to absorb the minimum fanout a directed cycle. of each level. out-cone( ) out-cone( )

dicult and we speculate it is NP-hard. It is important, moreover, to have a nearly linear time algorithm in order to generate large circuits. Therefore we solve the problem heuristically. Our approach is to rst determine, in steps 1 and 2, an assignment of edges and out-degrees to delay levels and then, in step 3, to divide the levels into individual nodes. We begin by collapsing the nodes at each delay level into a single \levelnode," ni , labeled with si = jNi j, the number of nodes it represents. This produces a modi ed problem: Assign levelnodes for each dj and pairs of level-nodes for each eh such that: (I 0 ) the number of edges leaving any ni is the sum of the si fanouts dj assigned to it. (II 0) There are at least si fanins to ni from ni;1 (i > 0). (III 0) Fanin(ni )  k
si . (Note: there is no IV 0 .) Step 1: Edge Assignment To Levels. To assign edges to level-nodes, we rst meet constraint II 0 , by assigning si unit edges (length one) between ni and ni+1 (i = 0::d ; 1). We then iteratively assign non-unit edges to meet constraints on minimum fanout and fanin of each ni . This is based on the interaction between shape and the supply of edges of each length, which restrict where edges of certain lengths will need to go in order to nd a feasible solution6 . Once as many edges as possible have been assigned in this way, we assign the remaining non-unit edges probabilistically: we calculate a distribution representing the ability of pairs of level-nodes to support edges of each length (based on their available fanin| constraint III 0|and fanout), and assign the edges randomly by sampling this distribution. Note that the remaining unit edges are not assigned until after the next step. Step 2: Fanout Assignment: The construction to this point is illustrated in the left side of Figure 8 (although the remaining unit edges are already shown). The fanout of each ni , (fanout(ni )) can be approximated from the already assigned edges. We now assign the elements of D to levels so as to satisfy the number of edges emanating from each level, and use the remaining unassigned unit edges to ensure a solution which exactly assigns all of the dj 2 D and meets I 0 without violating III 0. De ne Gi = fgij g to be the (initially empty) set of assigned fanouts (from D) for level i, and the unsatis ed fanout of level i, ui = fanout(ni ) ; j gij . De ne the mean unsatis ed fanout of level i, ui = ui =(si ; jGi j). The partition of out-degrees is done in a greedy manner7 . At each stage we assign the largest element of D to the ni with the largest mean unsatis ed fanout ui , then update Gi , ui and ui . Unit edges are assigned when ui falls below the number of remaining nodes (si ; jGi j). The process repeats until all dj have been assigned (meeting I 0 ), completing the situation illustrated in Figure 8. Step 3: Final Edge Assignment. We now return to the original problem speci cation. It remains to assign the edges and fanouts currently associated with ni to individual nodes of Ni. We proceed from the top down. At each level, we assign a fanout value gij to each one of the si nodes of Ni and randomly connect gij edges from the fanout list of ni to

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Figure 8: The generation algorithm it. The connection of fanin nodes is more dicult, because we have to complete the assignment without violating constraints II;III or IV . First we satisfy II by connecting one unit edge to each x 2 Ni . Then we build a list of edges from previous levels which have to be connected, and a list of (already de ned) heads of these edges. Proceeding iteratively with the list of head-nodes, sorted by the fanout to ni of that node, we assign the remaining edges. The assignment is random, but biased to enforce a certain amount of \locality" (closeness) in the result. Speci cally, when choosing the sets of fanout nodes for each node at a level, we sample l times (empirically l = 6) to minimize a distance metric between node labels in the fanin and fanout sets. Although we have not yet succeeded in producing a better characterization of locality, it is a fundamental feature of circuits, and so it is important to introduce a degree of locality in the generation process. The nal result of the generation algorithm on the structure of Figure 8 is the original example of Figure 6. 3.2 Closeness of Fit. Steps 1 and 2 are not guaranteed to nd a valid solution; when necessary, gen will modify D or create extra nodes to allow successful completion. With extensive experimentation, we have determined ve versions of Step 1 which together deal with the characteristics of dierent input sets, and we take the best result of each with Step 2 as input to Step 3. To evaluate the success of the heuristics, we compared the MCNC circuits to circuits generated with their exact pro les|gen typically made only minor changes to D or created few extra nodes, and these only on relatively few circuits8 . The degree of modi cation is larger when gen uses the entire default set|yet 85% of generated circuits are reasonable immediately, meaning they have a feasible number of I/Os. 3.3 Examples. Figure 9(c) shows four dierent circuits produced by gen using the default parameter distributions. We note that these circuits appear to be \normal" circuits, and include many features such as areas of high-fanout. The visual \quality" of the circuits is most striking when one observes the similarity to MCNC circuits (Figure 9(a)) and the contrast between MCNC circuits and random graphs (Figure 9(b)). 3.4 Parameterization. gen is augmented with a sophisticated C-like language, symple, for parameter generation. The default distributions are written in this language, and the user can specify modi -

6 This is one of the more involved steps in the algorithm, and it is 8 We nd d and nPI correspond exactly always, nPO exactly on not possible to describe all the details here. More detail will appear in a Tech. Report, and the code is is publically available from the authors. about of circuits, and on most others of by a reasonable amount. 7 We have we have omitted some details in the algorithm wich are Shape,75% edge-length and out-degree distributions were modi ed less than necessary to ensure that a reasonable solution can be found without 25% of the time, and usually by a minor amount. backtracking.

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Figure 9: MCNC circuits vs. random graphs vs. gen.

smallIO = gauss(0.431*size2 + 1.448, 1.562; medIO = gauss(0.225*size2 + 8.026, 8.006); largeIO = size2*gauss(-0.054*log(size2)+0.54,0.148); defaultIO = rand(20, 500); nIOfl = size2<30 ? smallIO : size2<100 ? medIO : size2<1000 ? largeIO : defaultIO; nIO = min(n-depth+2, nint(nIOfl));

9 This is because the coecients of unspeci ed relationships between parameters are drawn rst, then scaled to the dierent circuits, rather than chosen independently.

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In this section we judge the quality of the generated circuits with respect to parameters not speci ed in generation: reconvergence, and post-placement and routing wirelength and track count. Since one of the primary applications of the circuits produced by gen is to test and evaluate physical design algorithms, the point of this exercise is to determine how reasonable the output is for this process. We constructed the exact pro le of the MCNC circuits (i.e. n, nPI , nPO, d, shape, fanout and edge length distributions), and generated corresponding circuits meeting those pro les with gen. Our method of validation is to compare the unspeci ed parameters of the MCNC circuits against those of the corresponding generated circuits and against \random graphs" of the same size. Because the exact de nition of a random graph varies, we now have to be precise: the most common usage of the term refers to a graph G(n; p) on n vertices with each possible edge existing with equal probability p. However, this is so drastically unlike a real circuit (G(n; p) would be hopeless to route for even small p) that we have found it a more reasonable comparison to use a random k-regular graph|a random graph such that each node x has fanin(x)+fanout(x)=k|as these graphs are more realistic in an electrical sense and are relatively easy to generate. We will compare against circuits mapped to 4-LUTs, and so we will use, for each circuit, the appropriate k 2 f4; 5; 6; 7g to generate approximately the same number of edges. Two drawbacks of this method are that random k-regular graphs have an inordinate number of I/Os (approximately 20% of nodes) and no high fanout nodes, but they provide a convenient comparison to non-parameterized random generation. 4.1 Reconvergence. Reconvergence, R, is not a parameter to gen. Reconvergence captures numerous properties of a circuit, including high fanout, and the interaction between shape, edge length and fanout distribution, all of which aect the ability to place and route the circuit. We calculated R for the generated circuits and compared them to those of the original circuits from which the generation pro les were extracted and to those of random graphs of the same size. The results for the largest 12 MCNC circuits, and means for these 12 and all circuits, are shown in Table 1. Note that 0  R  2 for 4-LUT mapped circuits. (See the footnote on page 3.) We found that, for 70% of generated circuits, R was within 0.1 of the value for the corresponding MCNC circuit. This indicates that the correlation for a crucial parameter R did carry through the generation process. The mean for each class is shown in the table. In contrast, the reconvergence numbers of the random graphs did not match the MCNC circuits at all. We observe

 

Figure 10: The symple language: nIO speci ed by a Gaussian distribution around a Rent-like relationship (gen default). cations on the command line, or in a script. symple provides a great deal of control over parameters. For example, nIO is currently de ned as per Figure 10 in the default script. symple allows parameters to be speci ed as constants, drawn from statistical distributions, chosen as functions of other parameters, or as a range of parameters (in which case multiple circuits are output). The latter case is illustrated in Figure 11, where the circuit size varies from 60 to 100 by 20: symple scales related parameters (e.g. depth and shape) yet retains the similarity of other properties9 . This ability to scale circuits while retaining fundamental similarities introduces an entirely new paradigm for evaluating the scalability of architectures and algorithms.

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that random graphs exhibit diminishing R as n increases. This is due to the two factors mentioned earlier: the absence of high-fanout nodes and the large number of I/Os. 4.2 Routability. To test the \routability" of our output circuits, we used a locally available tool to place and global route the sets of MCNC circuits, generated circuits, and random graphs described above. The circuits are compared on two dierent metrics: the number of tracks per channel required to successfully route, and the total wirelength of the global routing. The software which we used [1] chooses a minimal square grid to support the size of the circuit, and minimizes both maximum track-count per channel and total wirelength. Table 2 shows the statistics for the largest 12 MCNC circuits and the summary statistics (dierences) for these and all 114 combinational circuits. We see that the track count for the generated circuits diered by 11%, on average, from the corresponding MCNC circuit, whereas the random graphs diered by 63%. Wirelength diered by 11% for the generated circuits and 78% for random graphs. For the largest 12 circuits, the generated circuits used slightly more wirelength and tracks than the MCNC circuits, but the random graphs used much more. These results clearly show the circuits produced by gen are very similar to the MCNC originals and signi cantly more realistic than random graphs as benchmark circuits. C7552 ex5p i10 apex4 misex3 alu4 seq des apex2 spla pdc ex1010 (12) (114)

size 945 1072 1252 1270 1411 1536 1791 1847 1916 3706 4591 4608

mcnc 0.49 1.12 0.72 0.90 0.55 0.50 0.48 0.50 0.47 0.97 1.01 1.08 0.73 0.39

R gen 0.45 1.22 0.48 1.17 0.72 0.62 0.48 0.30 0.59 1.08 1.13 1.09 0.79 0.43

rand 0.05 0.27 0.09 0.23 0.24 0.22 0.21 0.07 0.20 0.13 0.10 0.10 0.17 0.29

Table 1: Reconvergence: MCNC vs. gen vs. random.

C7552 ex5p i10 apex4 misex3 alu4 seq des apex2 spla pdc ex1010 (12) (114)

size 945 1072 1252 1270 1411 1536 1791 1847 1916 3706 4591 4608

mcnc 5 10 7 9 8 8 9 7 9 10 13 8 (diff) (diff)

Tracks gen rand 8 13 10 21 9 19 9 23 10 24 7 26 9 27 9 23 10 29 13 19 14 19 19 28 28% 218% 11% 63%

mcnc 5705 14748 10427 16653 16780 16434 22111 16229 23556 49676 73875 55002 (diff) (diff)

Wirelength gen rand 8320 15918 13309 27904 13155 28738 14567 34423 16912 40152 15556 45177 21590 57040 24116 50294 25072 63418 62043 167832 81982 225679 92530 231655 22% 181% 11% 78%

Table 2: Routability: MCNC vs. gen vs. random.

5 Concluding Remarks

In this paper we have introduced a new method for generating realistic parameterized benchmark circuits. The circuit generation is derived from the measurement of several new graph-theoretic properties which we propose in this paper. As a result the circuits are much more realistic than random graphs. It has been shown that the quality of the circuits (as measured by reconvergence and routability) is comparable to an existing benchmark set and much better than that of random graphs that don't use these properties. Because of the close tie between characterization and generation, users are able to characterize their own circuits using circ and create defaults which more closely meet their own needs (rather than the MCNC defaults). Using this method, we can generate a large set of circuits with the properties of the largest MCNC benchmark circuits. It remains to be seen if even larger circuits (which could easily be generated) have realistic circuit behaviour. The gen algorithm is fast, requiring less than 1 minute of SUN Sparc4 time to produce a circuit with 30000 4-LUT nodes. The code is publically available from the authors. In the future we will expand the gen system to generate sequential circuits (with ip- ops, back-edges and cycles) and to join sub-circuits together hierarchically. We are currently working on the ability to generate regular (datapath) structures and also adding LUT functionality so that we can apply our circuits to logic synthesis as well as physical-design problems. Another important aspect to future work is to better capture the concept of locality in large circuits and to generate system-level circuits from combinational and sequential components. Acknowledgements. Thanks to Stephen North and AT&T Bell Labs for academic license to use dot[4] and Vaughn Betz for the use of his place-and-route software [1].

References [1] V. Betz, On biased and non-uniform global routing architectures [2] [3] [4] [5] [6] [7] [8] [9] [10]

and CAD tools for FPGAs. Tech. Report in preparation. University of Toronto, 1996. J. Cong and Y. Ding, FlowMap: An Optimal Technology Mapping Algorithm for Delay Optimization in Lookup-Table Based FPGA Designs, IEEE Trans. CAD, 13 (June, 1994), pp. 1{12. J. Darnauer and W. Dai, A Method for Generating Random Circuits and Its Application to Routability Measurement, in 4th ACM/SIGDA Int'l Symp. on FPGAs, FPGA96, Feb., 1996, pp. 66{ 72. E. R. Gasner, E. Koutso os, S. C. North, and K.-P. Vo, A Technique for Drawing Directed Graphs, IEEE. Trans. Soft. Eng., 19 (1993), pp. 214{230. M. D. Hutton, Characterization and Automatic Generation of Digital Circuits and Systems. Ph.D. Thesis in preparation, University of Toronto, 1996. M. D. Hutton and J. S. Rose, Automatic Generation of Hierarchical Digital Circuit Systems. Tech. Report in preparation. University of Toronto, 1996. B. S. Landman and R. L. Russo, On a Pin Versus Block Relationship for Partitions of Logic Graphs, IEEE Trans. Comp., C-20 (1971), pp. 1469{1479. Programmable Electronics Performance Corporation, PREP PLD Benchmark Suite#1, V1.2. 504 Nino Ave. Los Gatos, CA 95032, 1993. E. M. Sentovich et.al, SIS: A System for Sequential Circuit Analysis. Tech. Report No. UCB/ERL M92/41. University of California, Berkeley, 1992. S. Yang, Logic Synthesis and Optimization Benchmarks, Version 3.0. Tech. Report. Microelectronics Centre of North Carolina. P.O. Box 12889, Research Triangle Park, NC 27709 USA, 1991.