Solid-State Electronics 48 (2004) 2315–2319 www.elsevier.com/locate/sse
Characterization of double gate MOSFETs fabricated by a simple method on a recrystallized silicon film Xinnan Lin *, Chuguang Feng, Shengdong Zhang, Wai-Hung Ho 1, Mansun Chan Department of Electrical and Electronic Engineering, Hong Kong University of Science and Technology, Clear Water Bay, Kowloon, Hong Kong Received 11 March 2004; accepted 5 April 2004 Available online 25 June 2004
The review of this paper was arranged by Prof. C. Hunt
Abstract A simple process to fabricate double gate SOI MOSFET is proposed. The new device structure utilizes the bulk diffusion layer as the bottom gate. The active silicon film is formed by recrystallized amorphous silicon film using metalinduced-lateral-crystallization (MILC). While the active silicon film is not truly single crystal, the material and device characteristics show that the film is equivalent to single crystal SOI film with high defect density, like SOI wafers produced in early days. The fabricated double gate MOSFETs are characterized, which demonstrate excellent device characteristics with higher current drive and stronger immunity to short channel effects compared to the single gate devices. 2004 Elsevier Ltd. All rights reserved. Keywords: SOI MOSFET; Double gate; Recrystallization
1. Introduction The mainstream CMOS technology for integrated circuits has been scaled for many years, and it is quite clear that the trend will continue for several more technology generations. Scaling beyond sub-50 nm, however, has been shown to be difficult and double gate MOSFET on silicon-on-insulator (SOI) film is considered as the future technology to pick up the mainstream manufacturing due to its immunity to short channel effects [1,2]. On the other hand, there is comparatively less attention to the study of double-gate device than other advanced device structures. It is mainly due to the dif-
* Corresponding author. Tel.: +852-2358-8842; fax: +8522358-1485. E-mail address:
[email protected] (X. Lin). 1 Microelectronics Fabrication Facility.
ficulty to fabricate experimental double gate devices. Most of the studies on double-gate device physics have to resort to 2-D or 3-D device simulator and experimental validation is usually not available. In this paper, we have developed a simple method to fabricate experimental double gate MOSFETs on a recrystallized amorphous silicon film (referred as large grain polysilicon-on-insulator or LPSOI film [3]) using nickel as the crystallization agent. As simplicity is the main objective, the bottom gate is larger than the top gate and is not self-aligned. A self-aligned process is possible, with the cost of much higher complexity [4]. The technique is general enough that other recrystallization methods such as selective epitaxial lateral overgrowth [5] or laser recrystallization [6] can be used. The characteristic of the LPSOI film is similar to the SOI film, except for higher defect density, like SOI wafers produced in early days. Thus, all physical properties of double gate SOI devices are preserved. Compared with
0038-1101/$ - see front matter 2004 Elsevier Ltd. All rights reserved. doi:10.1016/j.sse.2004.04.015
2316
X. Lin et al. / Solid-State Electronics 48 (2004) 2315–2319
single gate MOSFETs, double gate MOSFETs displays higher subthreshold slope and lower threshold voltage, leaving a larger operation margins with supply voltage scaling when the same Ion =Ioff ratio is maintained. The better immunity to short channel effects such as draininduced barrier lowing (DIBL) is observed. The current drive of the double gate MOSFETs is found to be higher than the sum of currents from the top and bottom channel which is caused by channel coupling [7].
2. Device structure and fabrication Fig. 1 shows the process to fabricate the double gate devices starting from a normal p-type bulk wafer for N buffer oxide was first grown channel MOSFETs. 250 A nitride. Semifollowed by the deposition of 1100 A recessed LOCOS process is used to isolate and define the bottom gate, which would give a more planar surface
Fig. 1. Key steps in the fabrication process of the experimental double gate LPSOI MOSFET.
and at the same time reduces the extension of the ‘‘bird beak’’. The bottom gate is designed to be wider than the channel region to guarantee the bottom gate extends over the entire channel and avoid the bird beak to extend to the channel. It is followed by the bottom gate implant. The dose and energy should be carefully selected to avoid oxide quality degradation associated with thermal oxidation from heavily doped substrate. In our process, the dose and energy used are 8 · 1014 cm2 and 60 keV respectively. After forming the bottom oxide by thermal oxidation from the bottom gate, amorphous silicon is deposited to form the body of the double gate MOSFET. The thicknesses used are 500 and 1000 A. Nickel-induced recrystallization is followed to recrystallize the amorphous silicon layer at 580 C for 24 h to guarantee large enough grain of more than 100 lm. With more optimized process, this long annealing time can be reduced to a few hours and still achieve similar result [8]. After nickel removal, the wafers are annealed in N2 ambient at 850 C for 30 min. The subsequent process follows that of a standard CMOS process. The final structure is shown in Fig. 1(g). Compared with the gate-all-around process on recrystallized film reported before [9], the process is more flexible especially in the fabrication of wide devices and asymmetric double gate structures with different top and bottom gate oxide thickness. The top and bottom gate can be connected or separately biased by using different layout method. This process is also extendible to fabricate device with film thickness below 50 nm with improved film quality [10]. The process is much simpler than the most commonly used process to fabricate double gate MOSFET such as the selectively epitaxial lateral overgrow (SELO) [11]. The SEM cross-section of the double gate MOSFET is shown in Fig. 2.
Fig. 2. SEM picture showing the cross-section of the experimental double gate LPSOI MOSFET.
X. Lin et al. / Solid-State Electronics 48 (2004) 2315–2319
3. Results and discussion The double gate MOSFETs fabricated in our exper iment has asymmetric gate oxide thickness with a 130 A bottom oxide. Single gate top oxide and a 280 A MOSFETs on LPSOI and SOI films are also fabricated gate oxide thickness for comparison. To with 130 A verify the film quality over a large area, a number of large (10 lm/10 lm) single gate MOSFETs on the LPSOI and SOI films are compared to calibrate the performance degradation due to the material quality difference. The ID vs VDS characteristics of various single gate and double gate devices are shown in Fig. 3. From the graph, it can be shown that devices fabricated on the LPSOI film are just similar to that on SOI film even for large devices. A 20% reduction in mobility is observed
Fig. 3. ID –VDS characteristic of long channel (10 lm) single gate and double gate LPSOI MOSFET ðTSi ¼ 100 nm) together with that of a single gate SOI MOSFET for comparison.
Fig. 4. Subthreshold characteristics of long channel (10 lm) single gate and double gate LPSOI MOSFET ðTSi ¼ 100 nm) together with that of a single gate SOI MOSFET for comparison.
2317
due to the slightly higher defect density, and the difference diminished at small dimension and the device characteristics of the single gate LPSOI MOSFETs becomes identical to that of SOI MOSFETs when the dimension is reduced to below 1 lm. The measured mobility and saturation drain current are 373 cm2 /V s and 200 lA/lm respectively at VG VT ¼ 1:55 V when L equals to 0.25 lm. The breakdown field of the front and back gate oxide are also measured and found to be ranging from 8 to 10 MV/cm indicating reasonable oxide quality is achieved despite the incorporation of little nickel in the channel. Comparison between single gate and double gate devices are then performed. As shown in Fig. 3, the total current from the double-gate device is less than two times that of the single gate device due to the thicker bottom gate oxide, but it is already higher than the total sum of the top gate and bottom gate MOS currents. Fig. 4 demonstrates the ID –VG of the fabricated LPSOI SG, LPSOI DG and SOI SG MOSFET characteristics. The turn-on voltages are both 1.1 V for SOI and LPSOI SG MOSFETs while it is 0.88 V for LPSOI DG MOSFETs. The measured subthreshold slopes are 141, 102, 68 mV/ dec respectively. Due to the higher defect density in the LPSOI film, the subthreshold characteristics of the LPSOI MOSFETs are poorer than that of SOI MOSFETs. But the resulting values are still reasonable, and the improvement in of subthreshold slope due to the backgate coupling effects in LPSOI DG MOSFET is clearly observed. As the coupling effect is more dominant at thin silicon film, stronger enhancement in current is obtained by using thinner silicon film. This is observed when we compare the turn on characteristics of LPSOI SG and DG MOSFETs with different channel thickness in Fig. 5. The S-factors of SOI SG, LPSOI SG, and LPSOI DG MOSFETs with 100 nm channel film thickness are 88, 112 and 89 mV/dec respectively. When
Fig. 5. Subthreshold characteristics of short channel (0.25 lm) single gate and double gate LPSOI MOSFET together with that of a single gate SOI MOSFET for comparison.
2318
X. Lin et al. / Solid-State Electronics 48 (2004) 2315–2319
Fig. 6. The threshold voltage shift due to DIBL from single gate and double gate LPSOI MOSFET ðTSi ¼ 100 nm) as a function of effective channel length.
the film thickness is reduced to 50 nm, the S-factors of the LPSOI SG and LPSOI DG MOSFETs become 107 and 82 mV/dec. Fig. 6 shows the threshold voltage shift as a result of drain-induced barrier lowering (DIBL) in single gate and double gate devices. The DIBL voltage shift of double-gate device is much smaller than single gate MOSFET. Also the significant increase in voltage shift of single gate device begins at effective channel length ðLeff Þ of 0.65 lm, while the double-gate device maintain a low DIBL voltage shift until Leff is reduced to about 0.35 lm. It verified that the double gate MOSFETs has better immunity to short channel effects even with a thicker bottom gate oxide. It is due to the effective shielding of the fringing E-field from the bottom surface in a double gate structure [12].
4. Conclusion A simple process to fabricate double-gate device from bulk wafer is presented. The device performance is similar to double-gate device fabricated on early day SOI films with higher defect density. With the reduction of device dimension, the MOSFET fabricated by this method becomes identical to the double gate SOI MOSFET. Due to the simplicity of the process, it is perfect for fabricating experimental devices for the study of double-gate device physics.
Acknowledgements This work is sponsored by a Competitive Earmarked Research Grant HKUST6190/01E from the Research
Grant Council of Hong Kong. The authors would also like to thanks M. Xue, Z.K. Zhang, C. Shen, A.C.-K. Chan, S. Jagar and S. Leung for their help in paper preparation and valuable discussion.
References [1] Taur Y. CMOS scaling beyond 0.1 lm: how far can it go? International Symposium on VLSI Technology, Systems, and Applications, 1999. p. 6–9. [2] Suzuki K, Tanaka T, Tosaka Y, Hori H, Arimoto Y. Scaling theory for double-gate SOI MOSFET’s. IEEE Trans Electron Dev 1993;40(12):2326–9. [3] Wang W, Chan M, Jagar S, Poon VMC, Qin M, Wang Y, Ko PK. Super thin-film transistor with SOI CMOS performance formed by a novel grain enhancement method. IEEE Trans Electron Dev 2000;47(8):1580–6. [4] Zhang S, Han R, Sin JKO, Chan M. Implementation and characterization of self-aligned double-gate TFT with thin channel and thick source/drain. IEEE Trans Electron Dev 2002;49(5):718–24. [5] Denton JP, Neudeck GW. Fully depleted dual-gate thinfilm SOI P-MOSFET’s fabricated in SOI islands with isolated buried polysilicon backgate. IEEE Electron Dev Lett 1996;17(November):509–11. [6] Zeng X, Xu Z, Sin JKO, Dai Y, Wang C. A novel two-step laser crystallization technique for low-temperature polysi TFTs. IEEE Trans Electron Dev 2001;48(May):1008– 10. [7] Kim K, Fossum JG. Double-gate CMOS: symmetricalversus asymmetrical-gate devices. IEEE Trans Electron Dev 2001;48(February):294–9. [8] Cheng CF, Poon MC, Kok CW, Chan M. Modeling of grain growth mechanism by nickel silicide reactive grain boundary effect in metal-induced-lateral-crystallization. IEEE Trans Electron Dev 2003;50(6):1467–74.
X. Lin et al. / Solid-State Electronics 48 (2004) 2315–2319 [9] Chan VWC, Chan PCH. High performance gate-allaround devices using metal induced lateral crystallization, Proceedings of 2000 International SOI Conferences. p. 112. [10] Jin Z, Kowk HS, Wong M. Performance of thin-film transistors with ultrathin Ni-MILC polycrystalline silicon channel layers. IEEE Electron Dev Lett 1999;20(April): 167–9.
2319
[11] Pae S, Denton JP, Neudeck GW. Multi-layer SOI Island Technology by Selective Epitaxial Growth for Single-Gate and Double-gate MOSFETs 1999, IEEE SOI conference, October 1999. [12] Park JT, Colinge JP. Comparison of gate structures for short-channel SOI MOSFETs 2001, IEEE SOI conference, October 2001.
