APPLIED PHYSICS LETTERS 93, 183504 (2008)

Capacitance-Voltage (CV) characterization of GaAs-Al2O3 interfaces. G. Brammertz, H.-C. Lin, K. Martens, D. Mercier, S. Sioncke, A. Delabie, W.E Wang, M. Caymax, M. Meuris, M. Heyns. Interuniversity Microelectronics Center (IMEC vzw), Kapeldreef 75, B-3001 Leuven, Belgium.

Abstract The authors apply the conductance method at 25°C and 150°C to GaAs-Al2O3 metaloxide-semiconductor (MOS) devices in order to derive the interface state distribution (Dit) as a function of energy in the bandgap. The Dit is governed by two large interface state peaks at mid-gap energies, in agreement with the Unified Defect Model. S-passivation and forming gas anneal reduce the Dit in large parts of the bandgap, mainly close to the valence band, reducing noticeably the room temperature frequency dispersion. But the mid-gap interface state peaks are not affected by these treatments, such that Fermi level pinning at mid-gap energies remains. We have recently shown that due to the larger bandgap of GaAs as compared to Si, the mid-gap interface states in GaAs are too slow to respond to the usual CV-characterization frequencies at room temperature1. In addition to room temperature measurements, measurements at higher substrate temperatures are also needed in order to deduce the characteristics of the interface states over the whole bandgap and in particular at mid-gap energies. In the following, we will apply the conductance method2 to alternating current (AC) CV-measurements performed with substrate temperatures of 25°C and 150°C on both n- and p-type GaAs substrates, in order to deduce the Dit as a function of energy in the whole bandgap. Alternative methods to derive the interface state density over the whole bandgap are quasistatic CV-measurements with very slow sweep rates and long integration times3 or Photoluminescence Intensity measurements3. The samples analyzed in this work consist of 5 1017 cm-3 Si- (n-type) or Zn- (p-type) doped GaAs substrates on which 10 nm Al2O3 was grown by atomic layer deposition (ALD) in an ASM Pulsar ALD reactor. The Al2O3 was deposited at 300°C using alternating pulses of H2O and trimethylaluminum (TMA). Prior to deposition, two different surface treatments were applied. A first set of samples (n- and p-type) received a 5 min HCl clean and a second set of samples (n- and p-type) received a 5 min (NH4)2S wet chemical clean. The resulting four samples got an ohmic contact on the backside consisting of AuZn/Au (p-type) or AuGe/Ni/Au (n-type) multilayers, followed by a 30 sec 380°C forming gas anneal (FGA). On the front side Pt metal dots were deposited through a shadow mask. In addition, the samples with the (NH4)2S clean were further treated with a 30 min forming gas anneal at 400°C. 200 µm diameter metal dot capacitors were then

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measured with a standard HP 4284 LCR meter. In order to get a continuous picture of the Dit, 25 frequencies were measured varying logarithmically from 100 Hz to 1 MHz. The experimental results from the samples with HCl clean are shown in Figure 1, whereas the data for the S-treated samples with forming gas anneal is shown in Figure 2. The four figures on the upper line show the regular CV data for the 25 measured frequencies of the n- and p-type samples at both 25°C and 150°C. The four figures on the lower line represent the conductance data, plotted as a conductance map, which shows a two dimensional contour plot of the normalized substrate conductance (Gp/Aωq) as a function of bias voltage and measurement frequency. Here, Gp is the substrate conductance, derived from the measured conductance Gm by correcting for the oxide capacitance (Cox)2, ω is the measurement pulsation and q the majority carrier charge. In the conductance plots of figures 1 and 2, the measurement frequency f on the vertical axis was directly transformed into trap energy in the bandgap Et, using the characteristic emission time constants of the interface states, which behave according to general FermiDirac statistics4:

τ=

1 exp(∆E / kT ) , σvt N

(1)

where ∆E is the energy difference between the majority carrier band edge energy and the trapping state energy Et (depth of the trap), k is the Boltzmann constant, T is the semiconductor temperature, σ is the capture cross section of the trapping state, vt is the thermal velocity of the majority charge carriers and N is the density of states in the majority carrier band. From this characteristic emission time τ, one can directly derive the characteristic response frequency f=1/2πτ of a trapping state, knowing the depth of the trapping state in the bandgap. This equation shows that the characteristic emission frequency depends exponentially on the depth of the trapping state in the bandgap. The further the trap is away from the band edge, the slower it will emit a trapped charge. More details can be found in Ref. 1. Concerning the parameter values from equation (1), the thermal velocity and density of states are well known and well defined values for a specific semiconductor5, whereas the trap capture cross section depends strongly on the nature of the trap6. The capture cross section can take values varying from 10-12 to 10-20 cm2. Even larger values than 10-12 cm2 can not be excluded. Nevertheless, the largest majority of trapping states has capture cross sections of the order of 10-15 cm2 (Ref. 6). In the following, a capture cross section of 10-15 cm2 is assumed in order to illustrate the effects of the characteristic emission time constant. Assuming a value for the capture cross section leads of course to an uncertainty concerning the absolute position of the interface state position in the bandgap. The further the real trap capture cross section is off with respect to our assumed value of 10-15cm-2, the larger the error. Nevertheless, the exponential term in equation (1) is dominant and simple arithmetic on equation (1) show that even a variation of the capture cross section by three orders of magnitude will only give rise to an energy difference of 0.18 eV. This somewhat exotic method of positioning the interface states in the bandgap is necessary, because usually the conductance method relies on the determination of the flatband voltage in order to position the interface states in the bandgap, whereas this value can not be determined for our heavily pinned devices7.

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In order to clarify the data in the conductance maps, figure 3 shows a subset of the data of figure 1g in a more generally accepted way of representing conductance data. This will allow the reader to interpret the data in the conductance maps. Nevertheless, the conductance maps show the conductance data in a more efficient and intuitive way, as it allows visualizing the movement of the surface Fermi level as the gate bias is varied. Clearly, the frequency for which the maximum in the conductance data for every gate bias occurs corresponds to the characteristic frequency of the trapping states at the energy position in the vicinity of the surface Fermi level position at that precise gate bias. Therefore, following the maxima in the conductance map visualizes how the surface Fermi level moves over the energy gap as the gate bias is varied. When this trace of maximum conductance turns horizontal, as can be seen in particular on figures 1f, 1g, 2f and 2g, the Fermi level is effectively hindered from moving, which is generally expressed by the term Fermi level pinning. This can be easily visualized in such a conductance map. Applying the conductance method2, i.e. extracting the interface state data from the height of the conductance peaks, the Dit shown in the lower parts of figures 1 and 2 can be derived. Note that in the region where Gp/ω approaches Cox (Dit>1013/eVcm2), the extracted values are lower limits to the real Dit7. We can see that for both the HCl-cleaned and the S-cleaned samples, the Dit is governed by two large peaks around mid-gap energies. This is in agreement with the Unified Defect Model (UDM)8 and the pinned Fermi level around mid-gap energies for the vast majority of GaAs interfaces9, with the exception of the Ga2O3 passivated interface10. In addition, we see that somewhat closer to the conduction band, there is another, much smaller peak. Photoluminescence spectroscopy data of Si-doped samples (not shown here) as well as Deep Level Transient Spectroscopy (DLTS) measurements11 indicate that this smaller peak seems to be related to a Si defect in the bulk of the GaAs layer. This is also confirmed by the shape of the conductance peaks in figure 1h and 2h, which have a more plateau-like shape towards accumulation, without a clear maximum, which is a typical signature of bulk defects2. The effect of the S-passivation and forming gas anneal can also be clearly seen. It reduces the Dit close to the valence band to levels close to mid 1011/cm2eV. As a consequence of this reduction, the frequency dispersion in the room temperature CV-curves of the p-type samples is strongly reduced (figure 2a). The region close to the conduction band does not seem to be affected as much by the S-passivation and forming gas anneal (figures 1d and 2d). Most importantly, the two large mid-gap peaks, which completely dominate the Dit, although somewhat reduced or shifted in energy position, do not disappear. The Fermi level is still pinned around mid-gap energies. ALD Al2O3 with S-passivation and forming gas anneal is therefore not able to passivate the GaAs interface. Fermi level pinning around mid-gap energies for both n- and p-type GaAs remains, similar to MBE deposited Al2O3 on GaAs10. We have shown how the conductance method can be applied at 25°C and 150°C in order to derive the Dit over the whole bandgap of GaAs. Experimental measurements on HCl- and S-cleaned GaAs-Al2O3 MOS capacitors show that two large peaks around midgap energies govern the properties of the GaAs surface, which is in agreement with the Unified Defect Model by Spicer et al. Although S-passivation and forming gas anneal have some beneficial effects on the interface state density, reducing notably the room

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temperature frequency dispersion of p-type devices, Fermi level pinning around mid-gap energies is still present.

Acknowledgments The authors acknowledge support by the European Commission’s project FP7-ICTDUALLOGIC no. 214579 “Dual-channel CMOS for (sub)-22 nm high performance logic”.

References 1

G. Brammertz, K. Martens, S. Sioncke, A. Delabie, M. Caymax, M. Meuris and M. Heyns, Appl. Phys. Lett. 91, 133510 (2007). 2 E. H. Nicollian and J. R. Brews, MOS (Metal Oxide Semiconductor) Physics and Technology, p. 286, Wiley, New York (1981). 3 M. Passlack, in Materials Fundamentals of Gate Dielectrics, p. 403, Springer, The Netherlands (2005). 4 W. Shockley and W. T. Read, Phys. Rev. 87, 835 (1953). 5 http://www.ioffe.rssi.ru/SVA/NSM/ 6 N. P. Khuchua, L. V. Khvedelidze, M. G. Tigishvili, N. B. Gorev, E. N. Privalov and I. F. Kodzhespirova, Russian Microelectronics 32 (5), 257 (2003). 7 K. Martens, C. O. Chui, G. Brammertz, B. De Jaeger, D. Kuzum, M. Meuris, M. M. Heyns, T. Krishnamohan, K. Saraswat, H. E. Maes and G. Groeseneken, IEEE Trans. Electr. Devices, 55 (2), 547 (2008). 8 W.E. Spicer, I. Lindau, P. Skeath and C.Y. Su, J. Vac. Sci. Technol. 17 (5), 1019 (1980). 9 H. Lüth, Solid Surfaces, Interfaces and Thin Films, Fourth Edition, p. 343, Springer, Berlin (2001). 10 M. Passlack, M. Hong, J.P. Mannaerts, J.R. Kwo, and L.W. Tu, Appl. Phys. Lett. 68, 3605 (1996). 11 B. J. Skromme, S. S. Bose, B. Lee, T. S. Low, T. R. Lepkowski, R. Y. DeJule, G. E. Stillman, and J. C. M. Hwang, J. Appl. Phys. 58, 4685 (1985).

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Figure Captions

Figure 1: Capacitance- and Conductance-Voltage measurements on 200 µm diameter GaAs/Al2O3 MOS capacitors with HCl-clean: (a) 25°C CV-curves of p-type GaAs capacitor. (b) 120°C CV-curves of p-type GaAs capacitor. (c) 150°C CV-curves of n-type GaAs capacitor. (d) 25°C CV-curves of n-type GaAs capacitor. (e) 25°C Gp/Aωq map of p-type GaAs capacitor (f) 120°C Gp/Aωq map of p-type GaAs capacitor. (g) 150°C Gp/Aωq map of n-type GaAs capacitor. (h) 25°C Gp/Aωq map of n-type GaAs capacitor. The lower graph shows the GaAs-Al2O3 (HCl-clean) Dit derived from the four conductance maps, the arrows indicating which measurement measures the interface state density in what portion of the bandgap.

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Figure 2: Capacitance- and Conductance-Voltage measurements on 200 µm diameter GaAs/Al2O3 MOS capacitors with S-passivation and FGA: (a) 25°C CV-curves of p-type GaAs capacitor. (b) 150°C CV-curves of p-type GaAs capacitor. (c) 150°C CV-curves of n-type GaAs capacitor. (d) 25°C CV-curves of n-type GaAs capacitor. (e) 25°C Gp/Aωq map of p-type GaAs capacitor (f) 120°C Gp/Aωq map of p-type GaAs capacitor. (g) 150°C Gp/Aωq map of n-type GaAs capacitor. (h) 25°C Gp/Aωq map of n-type GaAs capacitor. The lower graph shows the GaAs-Al2O3 (S-passivated) Dit derived from the four conductance maps, the arrows indicating which measurement measures the interface state density in what portion of the bandgap.

Figure 3: More common representation of a subset of the conductance data from figure 1(g): Gp/Aωq as a function of frequency for different gate bias voltages.

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