Comparing Crossbar-based nano/CMOS Architectures Ciprian TEODOROV∗† ∗ Universit´e

Europ´eenne de Bretagne, France. de Brest ; CNRS, UMR 3192 Lab-STICC, ISSTB. 6 avenue Victor Le Gorgeu, CS 93837, 29238 Brest, France. Email: [email protected]

† Universit´e

Abstract—During the last few years, a novel set of nanoscale technologies has emerged as an alternative to traditional CMOS circuits. They bring certain promises such as high-density, reduced manufacturing costs, but they also present some challenges. Trying to compare some of the proposed architectures we realized that it is impossible to objectively evaluate them, problem that hinder our ability to practically develop these architectures. To compare these architectures we extracted the similarities between these fabrics and based on these similarities we tried to match the results presented in the literature. Following this methodology we were unable to objectively compare these emergent architectures. In this paper we present the main reasons why such an evaluation is not practical and we show how a common vocabulary and design methodology can solve this problem. Index Terms—Nanotechnology, Integrated circuit design

I. I NTRODUCTION During the last years a set of nanoscale circuit architectures emerged as an alternative to traditional CMOS circuits. NanoPLA [1], CMOL [2], FPNI [3], and NASIC [4] are some examples. These architectures are being built using a combination of lithographic process and bottom-up selfassembly which imposes a number of constraints like the regularity of assembly. All these architectures are hybrids since they all include CMOS support circuitry and they are expected to have defect rates orders of magnitude greater than typical CMOS architectures. To get these architectures as a viable replacement for the CMOS-based fabrics we need to be able to create, evaluate and compare them to their CMOS counterparts and to each other to be able to have an objective view of the domain and of each architecture separately. At the moment it is known that each of these architectures has its advantages and disadvantages but it is almost impossible to compare them mainly because of their architectural differences, the different physical parameters, the different evaluation strategies, and the different evaluation hypotheses used in the context of each architecture as it was being designed. Except the architectural differences, all the other reasons can be subsumed as the lack of tools for architectural design evaluation and exploration of nanoscale fabrics. In this article we propose a solution, which we name the common vocabulary approach (CVA), for this problem, consisting of the creation of an integrated development environment for architecture exploration and evaluation specifically

targeted for nanoscale crossbar-based hybrid architectures. This environment enables the rapid prototyping and evaluation of such architectures while letting the architecture designer focus on architecture modeling and not on software tool implementation issues, as it is the case today. This article is organized as follows. In section II we are briefly presenting some of the nanoscale architectures which are studied for this work. The similarities between these architectures are analyzed in section III, and the main reasons that hinder our ability to compare them are shown in section IV. An overview of the proposed solution is given in section V, and using two case studies, in section VI, we try to convey that CVA solves this problem by modeling two of the architectures presented in section II. Section VII presents some of the related works, and section VIII concludes this paper. II. A RCHITECTURES A. NanoPLA In 2004, Andr´e DeHon [1] proposed a PLA-like architecture, named nanoPLA, which implements a NOR-NOR logic style based on nanoscale crossbars having programmable diodes at crosspoints. To overcome the limitations of diode logic the authors propose to insert rectifying field-effect stages between diode stages. To solve the nano/CMOS interface problem DeHon proposes the use of a stochastic decoder [5] for addressing the nanowires. The reconfiguration is used as the main technique to tolerate permanent defects in the NanoPLA architecture [6]. But in [7] the same authors also propose a fine-grained rollback recovery technique for tolerating transient faults. B. CMOL Likharev and Strukov [2] introduced CMOL, a hybrid crossbar-based architecture which uses 3D integration (nanoon-CMOS) for solving the nano/CMOS interconnect problem. Based on this approach the authors proposed a number of architectures like memories [2], reconfigurable architectures similar to cell-based FPGAs [8], neuromorphic networks [2]. For this study we focus on the reconfigurable architecture proposed in [8], named CMOL FPGA, which implements a NOR-NOR logic style using the nanoscale crossbar for OR logic and interconnect, and CMOS cells for inverters, latches, etc.

The CMOL FPGA architecture uses reconfiguration as a defect tolerance technique, the principal type of defect studied is stuck-open crossbar junction, but since this kind of defect manifests itself in an unusable CMOS cell, it is modeled as a defective CMOS cell, this implies that the nano/CMOS interface defects, and broken NW are somewhat covered too. C. FPNI At the beginning of 2007, Snider and Williams, at HP labs, introduced a generalization of CMOL circuits, namely FieldProgrammable Nanowire Interconnect (FPNI) [3]. The FPNI architecture trades of some of the advantages of CMOL, such as speed, density, defect tolerance, in exchange for easier fabrication, lower power dissipation and easier routing. FPNI approach is more like traditional cell-based FPGA where CMOS cells implement arbitrary logic. The difference being the signal routing that is done entirely using the nano layer. Thus achieving better densities than traditional CMOS only FPGAs, which dedicate a large part of their area just for interconnect. Like for CMOL the reconfiguration is used to tolerate the defects of FPNI circuits. The stuck open crossbar junctions and the broken nanowires are the defect types studied. D. NASIC Moritz et al. proposed a hierarchical nanofabric architecture that can be tuned towards an application domain. The basic building blocks of this proposal are the nanotiles, built up as a grid of silicon NWs (SiNW) having the junctions acting as FET. NASIC architecture has raised many interesting issues in designing nano/CMOS integrated circuits. Some of these are: 1) Latching on the wire [9] to build pipelined circuits without the use of explicit latching (which implies the use of registers); 2) In one of the latest papers [10] Moritz et al. showed the possibility to combine AND-OR and NOR-NOR logic styles to obtain denser logic; 3) Furthermore in [11] they have shown the possibility to design nanoscale logic circuits using only one type of FET at the nanoscale with no degradation of performance, defect-masking, or density, meanwhile reducing the manufacturing requirements. 4) While in the first stages of the development [12] the fabric was conceived as being reconfigurable, in the later papers [13] the authors renounced at the reconfigurability to ease the manufacturing process. But, on the other hand, without a reconfigurable fabric, another approach was needed to render the fabric fault tolerant. 5) To solve this problem, in [4] Moritz and al. propose structural redundancy based techniques to render NASIC a self-healing circuit architecture. III. S IMILARITIES By analyzing the architectures presented in section II a number of commonalities were identified: • they are nanowire based; • the regularity of assembly, imposed by the bottom-up fabrication process, leads to: – a crossbar-like structure;

• •

– PLA and/or FPGA-like fabric architecture; they all use a CMOS superstructure, leading to the need of a nano-CMOS interface; they are expected to have large number of defects, due to the fabrication process and to the small size of the components.

Since all the studied architectures have structures based on nanowires they roughly share the same device level constraints and physical properties even though they are built using different fabrication processes. One example of these constraints is the regularity of assembly that imposes the main common structure in these architectures, namely the crossbar. The regularity of assembly, manifested by the crossbar structure imposes an architectural organization similar to (re)configurable architectures. The exception is NASIC which is not a reconfigurable architecture, but still, in the fabrication process proposed in [14], the nanowire functionalisation can be seen as some kind of configuration (in the PLA style) that happens during the fabrication and not after it. Another important similarity between the studied architectures is the use of a CMOS-based superstructure, seen as a reliable infrastructure which provides different architectural functions (e.g. clocking, power and ground, control, or even logic in the case of FPNI). At the same time the use of CMOS structures imposes the design of a nano/CMOS interface which represents one of the most important differences between 2D fabrics like NanoPLA and NASIC, and 3D fabrics as CMOL and FPNI. Furthermore, since the defect and fault densities of selfassembled structures are projected to be orders of magnitude greater than in traditional CMOS-based structures, it is very important to investigate the fault models studied in the context of these architectures. In Table I we can see the fault models used for the architectures presented in section II along with the defect/fault distribution and the fault tolerance techniques proposed by the designers of each architecture. It can be easily seen that 3 from the 4 architectures use reconfiguration for fault tolerance and that just the defects/faults uniformly distributed are studied. The defect/fault types considered are based on the same abstract fault model from which only a subset is covered. The reason behind this can be found in the limitations of the reconfiguration approach to fault tolerance and the limited expression power of the tools used to model and evaluate these architectures. Another interesting characteristic of the studied architectures is the way the logic implemented. NanoPLA uses NORNOR arrays build with a diode-based OR stage followed by a FET based inversion/buffering stage. CMOL uses NOR-NOR logic which is built using latching switches (which is basically a switch with the capacity to stay in a certain state (ON/OFF) once configured in that state) for the OR stage which is followed by a CMOS inversion stage based on a CMOS inverter. FPNI uses the nanoscale crossbar just for routing and thus uses CMOS custom gates for logic implementation. NASIC proposes to implement different logic styles, and

FPNI [3] reconfiguration

Defect/fault distribution

uniform

Permanent

Fault tolerance technique

CMOL [8] reconfiguration

NanoPLA [1] reconfiguration & rollback recovery uniform

uniform

broken NW bridged NW stuck open stuck close

• • -

• • -

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-

• treated as a defective CMOS cell -

Intermittent Transient

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• • • Treated as nanowire deffects. Unusable horizontal and vertical nanowires [6] • stochastic decoder • rollback recovery [7]

Nasic [4] self healing circuits uniform & clustered • • • • • • •

TABLE I T HE FAULT TYPES STUDIED FOR THE PRESENTED ARCHITECTURES

even a combination of different styles based on FET based logic designs. In conclusion, even if each architecture uses different nanoscale devices for implementing the functionality all these nanoscale devices can be abstracted to a set of generic primitives (like diode, switch, etc.). IV. W HY IT IS IMPOSSIBLE TO COMPARE THEM ? For the architectures presented in section II the nanoscale devices play different roles, in NASIC they are used for logic and routing, in CMOL for OR logic and routing, in NanoPLA for logic, and in FPNI just for routing. Each approach has its advantages and disadvantages but it is almost impossible to compare the result presented for each one. The main reasons for this are: 1) architectural differences, 2) different physical parameters used for evaluation, 3) different evaluation strategies, 4) different hypotheses during evaluation for the aspects not being investigated. The architectural differences refer to the different design choices that were made for each architecture to optimize a specific aspect of the system. For example, FPNI trades off some of the speed, density and defect-tolerance of CMOL in exchange for easier fabrication, lower power dissipation, and greater freedom in nanodevice selection. NASIC trades off the advantages of fault tolerance by reconfiguration for easier fabrication process. The different physical parameters used for evaluation, like nanowire pitch (NWP), nanowire width (NWW), nanowire resistance, CMOS wire width, etc., differ from one architecture to another. For example FPNI uses a 9nm NWP and a 5nm NWW while NASIC architecture bases its results on 10nm NWP and 3∼4nm NWW. Different evaluation strategies refer to the fact that each architecture was evaluated using a specific tool according to a specific evaluation policy. For example, while FPNI and NASIC were evaluated using a yield simulator, CMOL and NanoPLA architectures used a place and route approach based on configuration around defects. Even if there is one aspect being evaluated for all architectures, the results cannot be compared because the evaluation is based on different hypotheses for the other aspects not investigated. The high rate of defects and the need for novel fault tolerance techniques render the comparison even more difficult

since for each architecture the faults studied are different as well as the techniques used to create a robust architecture. In conclusion, except the architectural differences all the other reasons point clearly to the lack of a common vocabulary along with a set of integrated tools targeted for these specific architectures, which imposes the development of specific tools for analyzing each architecture alone using different metrics and under different sets of assumptions. V. C OMMON VOCABULARY AND TOOLS As we already stated the lack of tools is the principal reasons for the impossibility to objectively compare the proposed nanoscale architectures. In this section we propose a solution, which we name the common vocabulary approach(CVA), consisting in the creation of an integrated development environment targeted to architecture exploration and evaluation of the nanoscale crossbar-based architectures. The main purpose of this environment is to create a common vocabulary for describing and reasoning about these architectures. A. Architectural building blocks At the core of this approach lies the capacity to hierarchically describe and compose the building blocks of nanoscale architectures, mainly the crossbars, and the nano/CMOS interfaces in the case of the architectures presented in section II. A crossbar is a set of orthogonally crossed wires with the crosspoints (the point where two orthogonal wires cross) capable of changing their states between two or more states1 . In the architectures presented in section II we can identify two states for the crosspoints: a null state, with the meaning that no active device is found at the crosspoint, so two crossing wires does not interfere with each other, and a configured state, meaning that between two crossing wires we have an active device (i.e. a FET in the case of NASIC, a diode or a FET in the case of NanoPLA, a latching switch in the case of CMOL and FPNI) connecting them together. In CVA the crosspoints of a crossbar are constrained to have all the same type of active device in the configured state in the case of a fault-free 1 By state we understand actually the nature of the device formed at the crosspoint

E. Advantages of CVA

Fig. 1. An AND-OR PLA configured as a full adder obtained by the composition of two crossbar components. It should be noted that the control circuitry is not shown in the figure.

crossbar, but this constraint can be altered when investigating faulty crossbar structures. The nano/CMOS interface appears from the need to interface nanoscale and microscale components in the same architectural structure. In the context of CVA the concept of nano/CMOS interface permits to abstract away the details of such an interface, and, to some extent, enables the interchange of such interfaces between two or more architectures. This way one can investigate, for example, the effectiveness of a stochastic interface like the one proposed by Andr´e DeHon in [5] for NanoPLA in the context of another architecture (say NASIC for instance), without being forced to remodel it. B. Hierarchical composition - from building blocks to fabrics The architectural building blocks presented in the last section can be composed to form larger functional structures. An example is the AND-OR PLA shown in Fig. 1 which is configured to perform a full-adder function. A larger, more complicated example is the NASIC tile model shown in Fig. 2 which will be detailed in section VI-A. By using hierarchical composition we can assemble, for example, several NASIC tiles together to create a complete NASIC fabric. C. Circuit layout automation The circuit layout on nanoscale architectures is to be done in several hierarchical steps, from a coarse-grain placement and routing of the circuit on architecture-specific functional units to a fine-grain placement and routing on the different architectural building block (crossbars, in our case). For the coarse-grain placement and routing traditional algorithms (e.g. Pathfinder [15]) could be employed. The fine grain logic placement on crossbars can be done using graph monomorphism algorithms like the ones presented in [16] and [17]. D. Fault simulation and defect tolerance Since the presented architectures are expected to have large number of defects (mainly introduced during manufacturing), and faults (due to the small feature size which renders them more sensible to environmental factors like radiations, interference, etc.) the tool support for fault simulation and defect tolerance modeling is a very important aspect studied in the CVA but a detailed description of this aspect is beyond the scope of this paper.

Besides the capacity to objectively evaluate and compare existing (and prospective) architectures another important advantage of the CVA is the raise of the abstraction level from device level to the architectural level, by providing a set of common primitives specific to nanoscale architectures (nanowire crossbar, nano/CMOS interfaces, etc). Thus enabling the architecture designer to focus on architectural modeling and not on the tool implementation issues, as is the case today (e.g. UMass yield simulator [4], CMOL CAD2 flow [8], FPNI CAD flow and yield simulator [3]). Which in turn gives the opportunity to rapidly design new architectures and to evaluate them objectively against the existing ones. VI. C ASE S TUDIES To illustrate the CVA this section presents the architectural modeling support via two case studies based on the developments around two of the architectures presented in section II: an application-specific architecture, namely NASIC, and a reconfigurable architecture, namely NanoPLA. In the case of the other two architectures presented in section II (CMOL and FPNI) the results are similar and thus they are not presented in detail. It should be noted that CVA is under development at the moment, and there are some aspects not fully covered. But even at this early stage it provides the capacity to model the most promising crossbar-based nano-architectures using the same abstractions and tools which, to the best of our knowledge, are not covered in the existing literature. A. Case I: NASIC To model the NASIC fabric architecture using CVA the particularities of the fabric have been identified and classified as nanoscale specific, nano/CMOS interface and CMOS superstructure elements. The main architectural building block is the NASIC tile which is composed from two nanoscale crossbars assembled together to form a PLA-like structure. One particularity of these crossbars is that they are applicationspecific (non-reconfigurable), the functionalisation of the PLA is done during the manufacturing process and cannot be changed afterwards. One important observation is that from a software engineering point of view the functionalisation [14] process can be seen as one time configuration of a reconfigurable architecture (a configuration which cannot be changed during the lifetime of the PLA). Based on this observation, in CVA, the NASIC crossbars are represented using the concept of reconfigurable crossbar as presented in section V-A with the constraint that the crossbar can be configured only once during its lifetime. Around the PLAlike structure in NASIC we can identify some additional nanoscale control circuitry for pull-up/down or for dynamic logic implementation. These structures are modeled at device level by composition of the wires and the active devices which implement them. The nano/CMOS interface is represented by direct connections between nanoscale wires and microscale 2 Computer

Aided Design

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Dynamic style NASIC tile modeled using CVA

wires. For a NASIC tile the CMOS superstructure consists of microwires, surrounding the NASIC nano-tile, which carry ground, power supply voltage, and control signals for the dynamic evaluation of the output. Fig. 2 presents a high-level view of a dynamic-style NASIC tile modeled using CVA. In the middle of the figure the two crossbars creating the PLA-like structure can be identified, having around the additional nanoscale control circuitry (veva, hdis, vpre, and heva), required to implement a fully operating dynamic-style NASIC tile. The nano/CMOS interfaces, presented in the figure, create the connection between the nanoscale components and the CMOS superstructure. For the moment the logic placement on a NASIC tile is implemented using a simple mapping algorithm that maps the logic circuit expressed as a PLA to the tile according to the logic type of the PLA-like structure (e.g. AND-OR, NORNOR, etc.). Once the mapping is computed the crosspoints of the crossbars are configured in the final state. The obtained tile can then be simulated using a switch level circuit simulator (targeted specifically for the simulation of nano/CMOS architectures), or a device level simulator like SPICE. To simulate a specific tile a model-to-model transformation is done between the high-level tile model (presented in Fig. 2) and the specific simulation model used (switch level model or device level model). B. Case II: NanoPLA The NanoPLA architecture uses a reconfigurable PLA-like structure as the main architectural building block. Two types of crossbars, in the sense described in section V-A, have been identified: a reconfigurable crossbar having diodes at the crosspoints in the configured state (see Fig. 3 the crossbars labeled OR), which is used to implement an OR (or an AND) logic stage, and a crossbar structure used for inversion and buffering which is somehow similar to the crossbars present in the NASIC architecture since they are not reconfigurable (the crosspoint FETs are created during manufacturing step). There have been identified three nano/CMOS interfaces in NanoPLA architecture: one configuration interface (see Fig. 3, to the left labeled config.), used to configure the reconfigurable crossbars, one control interface (see Fig. 3, around the crossbars labeled control) realized by the funtionalisation of the crosspoint

control Crossbar

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Next Stage

Fig. 2.

nano/CMOS Interface

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Fig. 3.

nano/CMOS Interface

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control

NanoPLA tile modeled by CVA

between a nanowire and a microwire used for passing control signals to the crossbars, and one direct nano/CMOS interface, realized via ohmic contacts between nanowires and microwires, used for interfacing with the CMOS superstructure carrying power, ground signals. For the NanoPLA tiles the same approach and tools are used for logic circuit mapping and tile simulation as described in the case of NASIC. In conclusion, we proved our point of being able to model different nanoscale architectures using the same vocabulary and the same tools built around this vocabulary. VII. R ELATED W ORK With the evolution of nanoscale computation technology a variety of software tools has emerged to experiment with nanoscale computational structure through simulation, modeling, and analysis. There exist tools for analyzing nanoscale transistors, device modeling, molecular simulations, small molecule visualization and a wide range of tools in conventional CAD such as Spice. But if we raise the abstraction level to architectural or system level we will find just a few tools that can help to create a reliable hybrid nano/CMOS design. a) Fault simulation: is a simple technique to study the impact of faults in a system, by replacing a number components with faulty components and by simulating the obtained system. The Space-based Reconfigurable Computing project [18] exploits this concept in order to study the impact of radiation-induced faults in SRAM-based FPGAs. For hybrid nano/CMOS architectures such a tool would be useful to characterize the reliability of an application for varying degrees of fault rates and types in the case of a specific fault tolerance technique. b) Design space exploration: represents a set of automated tools that can help the designer decide which choice to make in designing its architecture according to a specific metric. For example in [19], [20] the authors present automated analysis tools to help the designer quantitatively understand the relation between the redundancy factor and the circuit reliability. One of these tools, NANOLAB [20], is developed specifically for Markov random field-based architecture [21]. The other one, NANOPRISM [19], is used to determine the

reliability of a logic circuit. Some similar tools are developed for statistical analysis of fault-tolerant QCA circuits [22]. In [23] Snider et al. present a tool, developed at HP, that enables the construction and evaluation of simple crossbar architectures. This tool is able to synthesize circuits described in a subset of C language onto crossbar architectures. But this tool is proprietary and it appears (from [23]) that it doesn’t have the modeling capabilities to describe the architectures presented in section II. Other tools that are worth citing are VPR [24], and Madeo [25] which based on generic models and tools provide a way to model, use, and objectively evaluate real or prospective FPGA architectures. Moreover, Lagadec et al. [26] showed that it is relatively easy to extend the FPGAoriented model and tool-flow of the Madeo framework to target a FPGA-like architecture based on the NASIC fabric. But finally none of these tools can be directly used in conjunction with the presented crossbar-based circuits to objectively evaluate and compare their performance according to some given metric (surface, yield, etc). A set of generic design space exploration tools articulated by a high level domain specific model for crossbar based architectures will surely help the designers solve some of the challenges presented in these architecture, by: greatly reducing the development effort, increasing the quality of the designs, and providing a perennial support for the development of such architectures. VIII. C ONCLUSIONS Among other challenges the emerging nanoscale architectures have to face, is the impossibility to objectively compare them due to the lack of precisely defined metrics and integrated tool support. This paper sketches a solution based on the use of a common vocabulary along with a set of generic tools built around this vocabulary. This approach proved to be highly efficient for modeling and evaluating FPGA architectures, see VPR [24] and Madeo [25], and we argue that applying it to nanoscale architectures will certainly increase our understanding of nanotechnologies, and will bridge the gap between the technological advancements and their mass market exploitation. A number of issues are still to be examined, some of these are: 1) the integration of fault models in the architecture modeling and the fault simulation at different abstraction levels; 2) the integration of fault tolerance techniques into the modeled architecture; 3) the adaptation of common place and route optimization strategies to nanoscale architectures. R EFERENCES [1] A. DeHon and M. J. Wilson, “Nanowire-based Sublithographic Programmable Logic Arrays,” in FPGA ’04: Proceedings of the 2004 ACM/SIGDA 12th international symposium on Field programmable gate arrays. New York, NY, USA: ACM, 2004, pp. 123–132. [2] X. Ma, D. B. Strukov, J. H. Lee, and K. K. Likharev, “Afterlife for Silicon: CMOL Circuit Architectures,” IEEE-NANO, July 2005. [3] G. S. Snider and R. S. Williams, “Nano/CMOS Architectures Using a Field-Programmable Nanowire Interconnect,” Nanotechnology, vol. 18, no. 3, p. 035204 (11pp), 2007. [Online]. Available: http://stacks.iop.org/0957-4484/18/035204

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