Conductance method applied to high mobility substrates Presenter: Guy Brammertz imec

© imec 2011

G. Brammertz, PT/LDD

Outline

• Conductance method • Basics • Pitfalls • In0.53Ga0.47As/Al2O3 interface properties

• Full conductance method • Basics • In0.53Ga0.47As/Al2O3 example

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G. Brammertz, PT/LDD

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Conductance method: Basics

M

O

S

• Simple MOS structure. Ef

Ef

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G. Brammertz, PT/LDD

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Conductance method: Basics

M

O

S

•A bias voltage VG is applied to the gate. Ef eVG Ef

•This causes a movement of the Fermi level at the semiconductor surface.

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G. Brammertz, PT/LDD

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Conductance method: Basics

M

O

S

•On top of this bias voltage a small AC signal is applied (typically 30 mV) with a well defined frequency f (typically between 100 Hz and 1 MHz).

Ef eVG Ef

•This causes the Fermi level at the semiconductor surface to slightly oscillate up and down.

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G. Brammertz, PT/LDD

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Conductance method: Basics

M

O

•With this AC signal the capacitance and conductance of the structure can be measured, by analyzing the phase and amplitude of the AC current going through the structure.

S

Ef eVG

•Sweeping the gate bias will result in the measurement of well known CV curves. Cox

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Cd

Rs

G. Brammertz, PT/LDD

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Conductance method: Basics

M

O

S

•If there are interface states at the semiconductor surface, these will be filled with electrons up to the Fermi energy.

Ef eVG

•The small AC signal will now cause emptying and filling of the interface states at the Fermi energy within the oscillation amplitude.

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Conductance method: Basics

M

O

•The characteristic time of charge emission τ from a trap is function of the depth of the trap ∆E:

S

 ∆E  exp  kT   τ(∆E ) = σv t N c

Ef eVG

e∆E

EC

EV

σ: Capture cross section vt: Thermal velocity Nc: Effective density of states Cd Cox

Rs

Cit

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Rit

•The interface states induce an additional capacitance and resistance in the structure, represented by Cit and Rit in parallel with the depletion capacitance.

G. Brammertz, PT/LDD

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Conductance method: Basics M

O

•The additional trap capacitance and conductance will be measured if the measurement frequency is sufficiently close to the characteristic trap frequency f=1/2πτ.

S

f = 1kHz

Ef eVG

Cd Cox

Rs

Cit

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Rit

•In the example case, at Vg=1V, the Fermi level at the semiconductor surface passes through the trap level with a characteristic frequency of 1 kHz. G. Brammertz, PT/LDD

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Conductance method: Basics • The amount of interface states can be derived from the height of the conductance peak Gp, which is the conductance corrected for the oxide capacitance Cox, which needs to be assumed to perform the correction:

Gp =

2 ω 2Cox Gm 2 Gm + ω 2 (Cox − Cm )2

• The proportionality factor 1/fD between Dit and peak Gp can be derived from the width of the conductance peak on a log(f) graph*. A: Capacitor area ω: Pulsation (2πf) q: Electron charge

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0.12

5

1/fD

12

2

Gp/(Aωq) (10 /eVcm )

Dit = 1/fD Gp/Aωq

0.10 0.08 0.06

fp

5fp

4 3 2 1 0 0.5

2 3 4 5 6 Log( Frequency (Hz)) G. Brammertz, PT/LDD

0.6

0.7

0.8

0.9

[G p ω ]5 f [G p ω ] f p

1

p

* For details see Nicollian-Brews

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•One obtains the Dit as a function of bias voltage. The relationship bias voltage-surface potential needs to be derived.

6.4

2

Dit (10 /eVcm )

Conductance method: Basics

12

6.0 5.6 5.2 -0.8

-0.7 -0.6 -0.5 -0.4 Bias voltage Vg (V)

6.4

2

Dit (10 /eVcm )

Vg vs ψs

12

6.0

-0.3

•The usual procedure consists in performing simulations of an ideal high frequency C-V curve and to compare it to the experimental data in order to find the flatband voltage position (see pitfall 4 for problems). •By integrating low frequency CV-curves from the flatband position to other bias voltages, one can derive the relationship bias voltage-surface potential through application of the Berglund integral. Assumptions: • •

5.6

Interface states respond to AC signal. Interface states respond to bias sweep.

5.2 0.24 0.28 0.32 Energy level in bandgap (eV)

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•For quantum well structures this becomes very complicated and necessitates solution of Schroedinger-Poisson equation. G. Brammertz, PT/LDD

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Pitfall 1: Weak inversion response M

real Dit = 5 1011 /eVcm2 ; extracted would be > 2 1012/eVcm2

O

S

frequencies shown 1kHz → 1MHz

300K Ef eVG

Weak inversion responses, due to interactions of minority carriers with interface states, do behave in a similar way as majority carrier interface state responses. This can lead to overestimation of the Dit, if one applies equations that only take majority carriers into account. Solution: Full conductance measurements or full numerical admittance simulation including effects of minority carriers.

*K. Martens et al., TED 55 (2), 547 (2008) © imec 2011

G. Brammertz, PT/LDD

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Pitfall 2: Trap time constants

10 10 10 10 10 10

4 0 -4 -8 -12 -16 -20

0

0.4 0.8 1.2 1.6

2

2.4 2.8 3.2

10 10 10 10 10 10 10

10 8 6 4 2 0 -2

0

10 10 10 10 10 10

10

Si

8 6 4 2 0 -2

0

0.2

0.4

0.6

0.8

Energy in bandgap (eV)

0.2

0.4

0.6

0.8

1

1.2

1.4

10 10 10 10 10 10 10

10

InP

8 6 4 2 0 -2

0

1

10 10 10 10 10 10 10

10 8

In0.53Ga0.47As

6 4 2 0 -2

0

0.2

0.4

0.6

Energy in bandgap (eV)

0.2

0.4

0.6

0.8

1

1.2

Energy in bandgap (eV)

Energy in bandgap (eV) Characteristic trap frequency (Hz)

Characteristic trap frequency (Hz)

Energy in bandgap (eV)

10

GaAs

Characteristic trap frequency (Hz)

10

GaN

8

Characteristic trap frequency (Hz)

10

Characteristic trap frequency (Hz)

Characteristic trap frequency (Hz)

σ =10-16 cm2

10 10 10 10 10 10 10

10

InAs

8 6 4 2 0 -2

0

0.2

Energy in bandgap (eV)

The characteristic trap frequency varies strongly with the energy level of the trap in the bandgap, such that with typical AC measurement frequencies only small parts of the bandgap can be measured. © imec 2011

G. Brammertz, PT/LDD

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Pitfall 2: Trap time constants σ =10-15 cm2

To asses the other parts of the bandgap, high or low temperature measurements might be helpful. *K. Martens et al., TED 55 (2), 547 (2008). *M. Passlack et al., TED 57 (11), 2944 (2010). © imec 2011

G. Brammertz, PT/LDD

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Pitfall 3: Conductance limitation by Cox

The amplitude of the measured interface state conductance Gm is limited by the oxide capacitance, such that the largest Dit that can be reliably extracted is of the order of Cox/q. The oxide capacitance correction introduces a very large error for Dit values that exceed Cox/q. *K. Martens et al., TED 55 (2), 547 (2008) © imec 2011

G. Brammertz, PT/LDD

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Pitfall 4: Gate bias-surface potential extraction p-type In0.53Ga0.47As 0.7

100 Hz

2

Capacitance (µF/cm )

40

Dit (1012/eVcm 2)

0.6 0.5 0.4

D it from electrostatic simulations

35

1 MHz

0.3

D it from conductance method

30 25 20 15 10 5

0.2 -3

-2

-1 0 1 Gate voltage (V)

2

3

0 0

0.2

0.4

0.6

0.8

1

E-Ev (eV)

Flatband voltage determination for energy-voltage relationship extraction can be very problematic if large frequency dependent flatband voltage shift is present. Simulation of ideal high frequency CV-curves is not obvious, because of the low effective density of states in the conduction band, the possible presence of fast interface states close to (or inside) the conduction band and fast defect states inside the oxide (border traps). *G. Brammertz et al., APL 95, 202109 (2009) © imec 2011

G. Brammertz, PT/LDD

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Conductance method applied to In0.53Ga0.47As-Al2O3 n-In0.53Ga0.47As-Al2O3-Pt

300°K

300°K

2 2

Capacitance (µF/cm )

0.7

2

Capacitance (µF/cm )

100Hz

0.5

1MHz -2 -1 0 Gate voltage (V)

0.5 0.4 0.3 0.2

0.6 0.5 0.4 0.3

210°K

-2

-1 0 1 Gate voltage (V)

2

3

-2

-1 0 1 Gate voltage (V)

0.6 0.5 0.4 0.3 0.2 -3.0

-2.0 -1.0 Gate voltage (V)

77°K

0.7

100Hz

0.6 0.5 0.4 0.3

0.2 -3

1

0.7

2

2

-3

Capacitance (µF/cm )

0.4

0.6

Capacitance (µF/cm )

0.6

Capacitance (µF/cm )

77°K

0.7

2

Capacitance (µF/cm )

p-In0.53Ga0.47As-Al2O3-Pt

1MHz -2

2

-1

180°K

0.7

0 1 2 Gate voltage (V)

3

0.6 0.5 0.4 0.3 0.2

0.0

-2

-1

0 1 2 Gate voltage (V)

3

σ =10-15 cm2

*H.C. Lin et al., Microelectr. Eng. 86, 1554 (2009) © imec 2011

G. Brammertz, PT/LDD

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Full conductance method: Basics Vg

•The full conductance method is applied on MOSFET devices with S/D regions. •The S/D regions are shorted to the substrate.

S

G

D

•Carriers can freely float from S/D into the substrate to the gate, such that the minority carrier generation-recombination conductance in the substrate is eliminated. •Advantages:
Eliminates weak inversion response.
Allows Dit extraction in both electron- and hole-dominated bandgap regions on the same sample. •It does not solve the issues with: Trap time constants Conductance limitation by Cox Gate bias-surface potential extraction

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Full conductance method: n-In0.53Ga0.47As Gp/Aωq map

0.48

0.4 0.3

5.0

0.4 0.2

0.5

0.6

0.44 1

0.40 0. 8

0.2 -1

0 VG (V)

1

2

0.36 -2

-1

Weak 4.5 inversion 4.0 Inversion 3.5

0 VG (V)

1

30

D (1012/eVcm 2)

Electron 5.5 branch

it Log(Frequency(Hz))

6.0

0.52

0.6

-2

Extracted Dit

(1012/eVcm2)

E-EV (eV)

Conductance measurement

2

Capacitance (µF/cm )

C-V

25

From electron branch

20 15 10 5 0

2

0

0.5

1

E-Ev (eV)

0.6 0.4 0.2

Hole0.2 branch

0.50

0.4

0.45

0.6

0.6

Electron branch

Cmin=0.057038

0.0 -2

0.40

-1

0 VG (V)

1

30

0.2

Dit (1012/eVcm 2)

0.55

0.4

0.8 E-E V (eV)

Full conductance measurement

2

Capacitance (µF/cm )

•Strong weak inversion and inversion response

20 15

-2

-1

0 VG (V)

1

From electron branch

10 5 0

2

From hole branch

25

0

0.5

1

E-Ev (eV)

•No inversion response. •λ-shape of Dit trace allows Dit extraction in both halves of bandgap © imec 2011

G. Brammertz, PT/LDD

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References •Nicollian & Brews: MOS Physics and Technology, Chapter 5, pages 176-234 . •K. Martens et al., TED 55 (2), 547 (2008). •M. Passlack et al., TED 57 (11), 2944 (2010). •G. Brammertz et al., APL 95, 202109 (2009). •H.C. Lin et al., Microelectr. Eng. 86, 1554 (2009). •G. Brammertz et al., ECS Trans. 34 (1), 1017 (2011). •H.C. Lin et al., ECS Trans. 34 (1), 1065 (2011). Other papers, presentations and preprints can be found here: http://sites.google.com/site/guybrammertz/

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Acknowledgements • imec: Christoph Adelmann, AliReza Alian, Matty Caymax, Annelies Delabie, Marc Heyns, Dennis Lin, Koen Martens, Clement Merckling, Marc Meuris, Laura Nyns, Sonja Sioncke.

• TSMC affiliate at imec: Matthias Passlack.

• Intel affiliate at imec: Wei-E Wang.

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G. Brammertz, PT/LDD

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