Design of a Low Cost All-Digital PSK/PM Satellite Telemetry Transceiver G.Susinderrajan, S.Saran Kumar,T.Shankar,K.Sreeram,P.V.Ramakrishna Department of Electronics and Communication Engineering, College of Engineering, Guindy, Anna University, Chennai – 600 025 (Corresponding Author: [email protected])

Abstract Phase Shift Keying – Phase Modulation (PSK/PM) is a composite modulation scheme and has been widely used for telemetry and ranging for many satellites. In this paper, the design of an all-digital portable low cost PSK/PM transceiver implemented using Field Programmable Gate Array (FPGAs) is presented. First, the modulation scheme is explained, and then an architecture capable of carrying out the transceiver operations is proposed, followed by simulation results for tracking at Signal to Noise Ratios (SNRs), typical of Low Earth Orbit (LEO) ground station receivers. The various design issues are discussed and also design guidelines for choosing the tracking loop bandwidths are presented. Hardware realization of the proposed transceiver architecture has been carried out and the results are presented. Indexing Terms: Telemetry modem, PSK/PM Transceiver.

suitable for portability. There is no end-to-end characteristics or performance details available anywhere for this scheme. Only a very little information even about the modulation scheme and its performance is available in the open literature, and virtually none as far as the receiver architecture is concerned. With the advent of software radio concepts and the availability of high performance FPGA’s and DSP’s, today one can realize a custom-built telemetry transceiver at low cost. The objective of this paper is to propose a transceiver architecture and present details of its validation. The present paper is organized as follows. Section 2 describes the transceiver blocks. Section 3 explains the complete receiver block diagram and the design issues involved in designing each block. Section 4 presents the important simulation results that will be used to establish the design guidelines. Section 5 explains the hardware implementation and presents some important results and section 6 summarizes the paper and presents the conclusions.

1. Introduction PSK/PM is a two-step modulation scheme. First, Pulse Code Modulated – Non Return to Zero (PCM-NRZ) is used to generate PSK, modulated using a subcarrier, resulting in a low carrier frequency Binary Phase Shift Keying (BPSK) signal. The resulting BPSK waveform is subsequently used to carry out phase modulation of carrier frequency leading to the composite PSK/PM signal. The resulting signal has a residual carrier component whose power level can be altered by controlling the modulation index. This carrier component is used in the ground station for ranging applications. Use of sub carriers originated from the need to move the modulated spectrum away from the carrier frequency especially at very low data rates [1]. Because of their spectral efficiency, sine wave subcarriers have been recommended in [2]. The performance of the various modulation schemes used for deep space telemetry, have been compared in terms of their spectral efficiency and BER in [3]. T o th e b e s t o f th e a u th o r s ’ k n o w le d g e mo s t o f th e I ndian Space Research Organization (ISRO) satellites currently use PSK/PM modulation scheme for telemetry and in future missions also, they are expected to incorporate this scheme. These receivers are normally deployed only in satellite ground stations and as such need not be manufactured in large volumes, and thus they are normally available from only very few manufacturers (for examples see [4] and [5]). The commercially available receivers usually have been very costly (typically in the range of a few tens of thousands of dollars), bulky and not

2. Transceiver Design The transmitter is designed by generating the input

Fig.1 PSK/PM Modulator Block Diagram data from the (Pseudo Random Bit Sequence) PRBS generator which is then given to the BPSK modulator built using NCO. Analog PM modulation is done on the BPSK waveform in the digital domain. The resulting digital BPSK/PM waveform is converted into analog waveform using the Digital to Analog converter (IC DAC08). The main blocks of the transmitter is shown in Fig.1.

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phase changes in the PM signal itself. This would allow more noise into the system, which is undesirable. In this paper, PM demodulation is carried out using arc-tangent method. The idea is to measure the phase difference between the PM signal and the carrier component of the PM signal. This phase difference gives the PM signal demodulated directly. Next, the BPSK demodulator should recover the subcarrier and perform bit synchronization to enable coherent BPSK demodulation. The proposed architecture to realize the above mentioned function is shown in Fig.3 and the description of the architecture is provided next. Fig.2 Block Diagram of PSK/PM Demodulation The received RF signal is first bandpass filtered, amplified and down converted to a comfortable IF. The IF signal is then digitized and fed to the FPGA. First, the PM demodulation task is carried out, resulting in a BPSK modulated signal along with the estimates of carrier Doppler and then BPSK demodulation is carried out using Costas Loop. The block diagram of the receiver is shown in Fig.2

3.1 PM demodulator The PSK/PM signal is multiplied with the in-phase and quadrature-phase versions of the locally generated carrier signal and then low pass filtered using integrate and dump filters to eliminate the sum frequency component. The duration of accumulation for the accumulate and dump filters should be chosen large enough to reject the sum frequency component and small enough to allow the sidebands due to the modulating signal (i.e., sub-carrier). The four quadrant arctangent of the ratio of Q arm value to the I arm value, arctan(Q/I), gives the phase difference between the received signal and the locally generated signal. The arctangent is implemented using a look up table. The selection of the four-quadrant scheme also eliminates the

3. Telemetry Receiver design issues PM demodulation can be performed by carrying out FM demodulation using Phase Locked Loop (PLL) followed by integration of the resulting signal. But this would require a large loop bandwidth for the PLL, since it has to track the

Fig.3 Architecture of PSK PM Demodulator

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problem of phase ambiguity encountered in conventional Costas loops. The output from the phase estimation block, after passing through the loop filter, is then fed back as a correction to the NCO resulting in an architecture similar to PLL. It can be shown that the spectrum has a distinct line spectrum at the carrier frequency. Since the sidebands (due to modulation) are separated from the carrier by atleast one sub carrier frequency, a loop bandwidth sufficient to track the carrier component alone needs to be used. In the proposed architecture, a Type 2 second order PLL is used to track the carrier component of the PM signal alone. Once the PLL is locked to the carrier, the output of the arctangent block gives the PM demodulated signal. Hence the arctangent block serves both as a PM demodulator as well as a phase detector for the PLL. The loop bandwidth should be selected as narrow as possible so that the tracking is not disturbed by the sidebands. In order to estimate the Doppler, two techniques exist. One is to take an FFT of the received signal and then identify the carrier frequency by identifying the most significant peak. The resolution of the FFT decides the uncertainty in the estimation of Doppler. The second method is to select a slightly wider loop bandwidth so that the PLL tracks the Doppler in the carrier but simultaneously rejects the sidebands. The value of Doppler can be obtained by averaging the value of the NCO control voltage. The actual Doppler in the received signal ramps up or down depending on the trajectory of the satellite. This is a typical acceleration input in phase. This would require a third order loop to track with zero residual phase error but it has the inherent problem of instability. However, a second order loop could be designed to track an acceleration input with minimal residual phase error. The optimal values of the loop natural frequency and damping factor for an acceleration input are reported in [6]. Thus the loop natural frequency and damping factor are critical parameters in the design and should be judiciously chosen to satisfy the above criteria. Once the loop parameters are fixed, by applying the bilinear transformation to the transfer function of the PLL, the transfer function in the Z domain can be obtained. Then the Z domain representation of the VCO and loop filters has to be used. A NCO in the discrete time domain replaces the VCO. The transfer function use in the realization of the loop filter is y[n]=y[n-1]+(c1+c2)*x[n]-c1*x[n-1] where c1 and c2 are constants. The design of the loop filter coefficients namely c 1 and c2, given the loop parameters are presented in [7].

clock is very less, the loop bandwidth can be kept minimum for both these feedback loops. Selecting a very narrow loop bandwidth would improve the noise performance but simultaneously increases the lock time, thus losing many data bits. Thus it is a compromise between lock time and performance in the presence of noise. The phase detector used in the costas loop is sign (I)*Q. The bit synchronizer (used for clock recovery) is a digital phase locked loop which operates by integrating the input signals in both the I and Q channels over one symbol period. In addition to the nominally “on time or prompt” integration, “quarter period early” and “quarter period late” integrations are also carried out. The difference between the modulus of early and late integrator outputs gives an indication of the timing error, since the averaged difference will be zero when the timing is correct. Similar integrations are carried out in the Q arm to allow both the bit synchronizer and the costas loop to work in parallel. This timing error is fed to the loop filter whose output is used to drive a numerically controlled oscillator, which produces the prompt, quarter period early and quarter period late versions of the symbol clock. Once locked the prompt version of the symbol clock will be aligned with the symbol. The loop filter coefficients for both the costas loop and bit synchronizer are designed in a similar manner as the PM demodulator. The demodulated symbols are obtained by taking the most significant bit of the prompt integrator output in the I arm. Costas loop has an inherent phase ambiguity of ∏. This ambiguity has to be resolved either using preamble bits or by carrying out differential encoding prior to PSK modulation.

3.2 BPSK demodulator The BPSK demodulator consists of a Costas loop for carrier recovery and a Bit synchronizer for timing synchronization. Since the Doppler for the subcarrier and

4.1 PM demodulator The input PSK/PM signal was simulated with Doppler varying from -5 KHz to 5 KHz in 10 minutes which is a typical Doppler rate variation for LEO satellites

4. Simulation Results The simulation of the entire transceiver architecture was done in MATLAB. The digital data at 512 bps is given from a PRBS generator. Then PSK/PM modulation is done as follows. First, BPSK modulation is performed on the input data at a sub-carrier frequency of 25 KHz. This BPSK modulated waveform is then given to the PM modulation block. The modulation index o f P M i s k e p t a t 1 radian. The modulator output signal is centered at 2.7 MHz and is given out at the sampling clock rate of 8 Mega-samples per second. The alias of this signal is obtained at 10.7MHz (8+2.7MHz). The output waveform is then filtered using a standard 10.7 MHz crystal filter. Simulation results of the PM demodulator and the BPSK demodulator are presented in subsections 4 .1 and 4.2 respectively. All simulations were carried out with required quantization at the appropriate places. The input ADC quantization is kept 8 bits.

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transmitting at a frequency of the order of 140MHz. The Carrier to Noise Ratio (CNR) is kept at 13 dB for simulation purpose. The plot of the NCO control voltage in Fig.4 shows that the NCO frequency finally settles at 2.7MHz– 5KHz that is the input frequency. This confirms that the PLL is able to acquire lock with a Doppler of -5 KHz even in the presence of noise. The Doppler was found by averaging 512 values of the NCO control voltage. The output of the arctangent block is shown in Fig.5. It is observed that the difference frequency (beat- notes) slowly decreases and the demodulated BPSK signal at 25 KHz is available once the loop has locked. The magnified version of Fig.5 when the loop has locked is shown in Fig.6.

Fig.6 Arctangent Output (when locked) at CNR = 13dB

4.2 BPSK demodulator A BPSK signal of 25 KHz modulated by a data pattern of alternating ones and zeros was considered as the

Fig.7 Sign(I) x Q

Fig.4 NCO Control Voltage (CNR = 13dB)

Fig.8 NCO Control Voltage

Fig.5 Arctangent Output (CNR=13dB) input. A subcarrier Doppler of 5 Hz was given since 5 Hz Doppler is much more than the nominal Doppler expect ed for the subcarrier. Fig.7 shows the phase detector output of the Costas loop. It is observed that the phase error settles to a value close to zero after about 80 msec. The plot of the NCO control voltage in Fig.8 shows that the NCO frequency settles to a value around 25 KHz +5 Hz since the given Doppler was 5 Hz. The plot of power in the I arm is shown in Fig.9. The power in the I arm is found to increase

Fig.9 Power in I arm

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bandwidth of the spectrum analyzer is 300Hz, which is insufficient to display a modulation of 512 bps clearly. Therefore, the data rate has been increased to 3 Kbps in order to increase visibility and the resulting spectrum is shown in Fig.11. This spectrum matches with the spectrum obtained in Matlab simulation. The percentage utilization in Actel FPGA including both the modulator and demodulator is shown below. Total 26504 Fig.10 Timing Error and settle at a maximum value and the power in the Q arm settles at a minimum value. More than 90% of the total power is found to be in the I arm. This confirms that the loop has locked. Similarly the plot of the timing error (|early|-|late|) in Fig.10 is found to settle to a value close to zero, which confirms the synchronization of the symbol clock. The proper working of the entire architecture is confirmed from the above simulation results.

Used 7645

Percentage 35.6

Table.1 Number Of Core Slots Used In Actel APA 600PQ208 6. Conclusion The main contribution of this paper is in presenting a scheme for PSK/PM t ransceiver and realizing and verifying its performance in hardware. Though the present paper makes use of FPGAs one can easily implement the entire functionality in a low cost fixed point Digital Signal Processor as well. I n addition to PSK/PM, the digital architecture can be easily adapted to other modulation schemes like BPSK only, QPSK, FSK or MSK and even to cases where base band filtering is employed to conserve bandwidth. Further, by suitably changing the front end LNA and LO sections, the same architecture can be used as the baseband demodulator with a wide variety of RF front ends starting from VHF/UHF, S, C, X and Ku bands.

5. Hardware Realization The complete transceiver architecture was tested in hardware and was found to work according to the design specifications. The hardware implementation is performed using the same scheme as detailed above. First the PSK/PM modulation is carried out and this modulated signal is fed to the demodulator to retrieve the data.

7. References [1]. J.H Yuen, Ed., Deep Space Telecommunications Systems Engineering. New York: Plenum, 1983. [2]. CCSDS – 401.0 B-1 , Recommendations for Space Data System Standards, May 1998 [3]. CCSDS – SFCG, Efficient Modulation Methods Study at NASA/JPL, September 1997 [4]. http://www.rtlogic.com/datasheets/rt_logic_digital.pdf [5]. http://www.gdspace.com/products/rdm020.htm [6]. Mordechai Rennert and Ben-zion Bobrovosk, “Costas loops and PLLs under Doppler acceleration”, pp.373 377, Globecom 1995 [7]. Henry Samueli, Rajeev Jain, Charles Chien, Performance Analysis of an All-Digital BPSK Direct-sequence spreadSpectrum IF Receiver Architecture. September 1983. Fig.11 PSK/PM Spectrum obtained in Spectrum Analyzer The output data from the PSK/PM demodulator is found to match with the input data given to the PSK/PM modulator and the whole transceiver architecture is found to work satisfactorily in hardware. The Fig.11 shows the PSK/PM spectrum in spectrum analyzer. Since the resolution

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