IJRIT International Journal of Research in Information Technology, Volume 2, Issue 4, April 2014, Pg: 468- 473

International Journal of Research in Information Technology (IJRIT) www.ijrit.com

ISSN 2001-5569

Design of Double Precision IEEE Floating Point Adder K.Varun, M-Tech VLSI Design, E. Siva Kumar, M-Tech. Faculty Of Engineering and Technology, Dept of ECE,SRM University Email: [email protected] ; [email protected]

Abstract Floating-Point addition imposes a great challenge during implementation of complex algorithm in hard real-time due to the enormous computational burden associated with repeated calculations with high precision numbers. Moreover, at the hardware level, any basic addition or subtraction circuit has to incorporate the alignment of the significands. This work presents a novel technique to implement a double precision IEEE floating-point adder that can complete the operation within two clock cycles. The proposed technique has exhibited improvement in the latency reduction and operational chip area management.

Keywords: Floating-Point Addition, IEEE 754, Delay Optimization.

1. Introduction In recent years computer applications have increased in their computational complexity. The industry-wide usage of performance benchmarks, such as SPEC marks forces processor designers to pay particular attention to implementation of the floating point unit or FPU. Special purpose applications, such as high performance graphics rendering systems, have placed further demands on processors. High speed floating point hardware is a requirement to meet these increasing demands. This work examines the state-of-the-art in FPU design and proposes techniques for improving the performance and the performance/area ratio of future FPUs. A floating point number representation can simultaneously provide a large range of numbers and a high degree of precision. As a result, a portion of modern micro-processors is often dedicated to hardware for floating point computation. Previously, silicon area constraints have limited the complexity of the floating point unit or FPU. Advances in integrated circuit fabrication technology have resulted in both smaller feature sizes and increased die areas. Together, these trends have provided a larger transistor budget to the processor designer. It has therefore become possible to implement more sophisticated arithmetic algorithms to achieve higher FPU performance. Efficient use of the chip area and resources of an embedded system poses a great challenge while developing algorithms in embedded platforms for hard real-time applications, like control systems, digital signal processing, vision based sensing, and so on. Although, different computational requirement of the algorithms involves different degrees of precision in any engineering and scientific applications, the floating point operations are almost always employed in such applications for accurate and reliable algorithmic computations. However, addressing the problem of floating-point representation of numbers and the computational resources required while execution of the algorithm, at the software level, may not result into an optimal and dependable solution. Therefore, some hardware based solution at the chip development level is most suitable for this case where a dedicated digital circuit would be responsible for representation of the floating point numbers and as well as performing the arithmetic and logical operations as demanded by the algorithms. However, Development of such a digital circuit for the purpose of representation of the floating point numbers and as well as performing the arithmetic and logical operations on them is quite difficult at the chip level due to the high level of Complexities involved. This paper presents a novel technique to implement a double precision IEEE floating-point adder that can complete the operation within two clock cycles. This investigation presents a novel technique to implement a double precision IEEE floating-point adder that can complete the operation within two clock cycles. A number K.Varun,

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IJRIT International Journal of Research in Information Technology, Volume 2, Issue 4, April 2014, Pg: 468- 473

of works have been reported in the literature with an aim to achieve a reduced latency realization of floating point operations.

II. REPRESENTATION OF IEEE 754 DOUBLE FLOATING PPOINT NUMBER In accordance with IEEE 754-2008 there are half, single, double and quadruple precision binary numbers having a mantissa of bit length 16, 32, 64, 128 respectively. Out of these, the double precision number is most widely used in the area of binary applications. This type of representation of the numbers is advantageous due to fact that a large spectrum of numbers can be expressed With a limited number of bits.

S-Sign bit E-Exponent bits F-Significand bits Example Example Decimal number=18.75 Convert the digits before and after the decimal point in binary format Value is 10010.1001011 Exponent consist of a bias and for double precision it is 0 < E < 2047 Actual exponent is: e = shifted places +1023 Hence, 1023+4=1027 1027 representation in binary=1000000011 Remaining mantissa=0010110000000000000000000000000000000000000000000000 III. General Algorithm The standard algorithm for the floating-point addition [7] has been described as follows. Let, the two input numbers, defmed by their bit vector be, (sa, ea, fa) and (sb, eb, fb), and say SOP denote the arithmetic operation that is required to be done (0 – for addition; 1 - for negation). The requested operation is the rnd(sum) = rnd(( _l)^sa ·2^ea . fa + (_l )^sOP+sb) • 2^eb • fb) Let, the effective sign of operation be, S.EFF = sa xor sb xor SOP So, for S.EFF = 0 the circuit will perform an essential addition and if S.EFF = 1 then the arithmetic operation will essentially be a subtraction. From these two numbers, and the exponent difference 0, the small operand is defined as(ss, es, fs) and the large operand is denoted as, (sl, el, fl).The resulting sum can be computed as Sum = (_1)^sl ·2^el . (fl + (_l)^sEFF (fs.2^|ᵟ |)

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IJRIT International Journal of Research in Information Technology, Volume 2, Issue 4, April 2014, Pg: 468- 473

IV. Proposed Algorithm The floating point arithmetic in is two stage pipe lined which are divided into two paths, namely "R-Path" and "N-Path". The two paths are selected on the basis of the exponent difference. The new algorithm has been arrived at by following a few implemental changes in the standard algorithm .This algorithm is broken into two pipeline stages, which are executed in two different clock cycles. The advantage of the pipelining mechanism is that, despite having a higher input-output sequential length, they offer an unmatched throughput by virtue of their assembly line structure.

Fig 2:Higher level representation of algorithm First cycle: • Normalization of the inputs. • Determination of the effective sign of operation.(S.EFF) • Determination of the alignment shift amount, δ or MAG_MED signal Second Cycle: • Addition of the Significand. • Rounding of the result. • Normalization of the result. Detailed representation of first cycle:

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IJRIT International Journal of Research in Information Technology, Volume 2, Issue 4, April 2014, Pg: 468- 473

Fig 3:first clock cycle First cycle: • Normalization of the inputs. • Determination of the effective sign of operation.(S.EFF) • Determination of the alignment shift amount, δ or MAG_MED signa Detailed representation of second cycle:

Fig 4:second clock cycle Second cycle: • Addition of the Significand. • Rounding of the result. • Normalization of the result.

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V.SIMULATION RESULTS Simulation of this circuit we have used Model sim-altera 6.6d. The top level source is Hardware Description Language type, with a Verilog code written and synthesis of this design is carried out in Altera Quartus II. Figure 5.a shows the simulation result using model sim and Figure 5.b shows the synthesis report carried out in Altera Quartus II

Fig 5.a

Fig 5.b

VI. CONCLUSIONS This paper has successfully demonstrated an implementation of a high speed, IEEE 754, double precision floating point adder with a significant decrease in latency. This paper has shown a latency of 4.6 ns. This manifest in the fact that FPGA based embedded systems has a higher advantage of lower computational aspects. Also, an implementation work of this algorithm, on the recent Xilinx Virtex-6 FPGA would give results with further improvement.

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