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Switching Circuits
Digital Integrated Circuit Chapter 10
• Uses diodes, bipolar junction transistor (BJT) and Metal Oxide Semiconductor Field Effect and Metal Oxide Semiconductor Field Effect Transistors (MOSFETs) • TTL (Transistor Transistor Logic) is most popularly used in 7400 series • 74C00 and 74HC00 series widely uses MOSFETs.
Semiconductor Diode • PN Junction. • Behaves like a one way switch. • Operates in 2 mode:
LED • Light Emitting Diode • Arrow shows light emission. • Working is similar to the normal diode.
– Forward bias – Reverse bias
• In forward bias, acts like a closed switch. I f d bi t lik l d it h • In reverse bias, acts like an open switch.
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BJT • Available in two polarities : – npn – pnp
• It is a 3 terminal device, these terminals are called: – Emitter – Base B – Collector
Working of BJT • Voltage between the base and emitter is zero th th then the switch is open. it h i • If Voltage is present between the base and the emitter, the switch is closed. – Current flows between collector & emitter. Current flows between collector & emitter – Voltage between collector and emitter is zero.
• BJT behaves like an electronic switch.
MOSFETs • MOSFET is widely available in two polarities: – N channel – P channel
Complementary Metal Oxide Semiconductors (CMOS) FETs • Gates may be constructed using both n channel and p channel MOSFETs. h l d h l MOSFET
• MOSFET is a 3 terminal device. • The terminals are : – Gate – Drain Drain – Source
• n channel and p channel MOSFETs are complementary devices. • So these devices are called CMOS Ics.
• Working is very much similar to BJT
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CMOS Inverter
7400 TTL
• In the CMOS inverter shown, – V1=0V; Qn is OFF and Qp is On; so V2 is +5 V dc. – V1=+5V; Qn is ON and Qp is OFF; so V2 is 0 V dc.
• A multiple emitter input transistor is used at i input. t • Q3 and Q4 form the Totem Pole connection (one npn in series with another)
• If A&B is low, base of Q1 is pulled down to approximately 0.7V. Thus, reducing the base voltage of Q2 to almost 0V. So, Q2 cuts off. When Q2 is open, Q4 is also cut off & Q3 is pulled high. Emitter of Q3 is 0.7V below the base and thus Y is pulled up to a high voltage.
• Only one of the two transistors in ON ie when Q3 is ON o/p is high. • When Q4 is ON o/p is low.
• When A&B is both high, high emitter diode of Q1 stops conducting and the collector diode goes into forward bias. Thus Q2 turns on. In turn Q4 goes high and Q3 turns off. Thus producing low output.
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TTL Parameters • Without the diode D1, Q3 will conduct slightly when the output is low. To prevent this, the h th t ti l T t thi th diode has been used inserted.
• Schottky TTL (Self Study)
Floating inputs
• When TTL input is high, the emitter current is ideally 0. • When a TTL input is floating (left open), no emitter current is possible because of open circuit current is possible because of open circuit. • Therefore, a floating TTL is equivalent to high output. • An open i/p allows the rest of the gate to function properly.
• To work reliably over a temperature range of 0 t 700C and over a supply of 4.75 to 5.25 V. to 70 C d l f 4 75 t 5 25 V These points must be taken into account – Floating inputs – Worst case input voltages – Worst case output voltages p g – Compatibility – Sourcing and Sinking
Worst case Input/output voltages
• VIL,max =0.8 V • VIH, min=2V i 2V • VOL,max=0.4V • VOH,min=2.4V This is called the window.
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Compatibility
Sourcing and Sinking
• The TTL devices are compatible because the l low and high output windows fit inside the d hi h t t i d fit i id th low and high input window of another TTL device. • The output of any TTL device is suitable to drive the input of another TTL device. p • The first device is called driver and the second is called the load.
TTL Overview • NAND gate – Backbone of 7400 series B kb f 7400 i – Derived from the 2 i/p NAND gate to produce 3‐4‐ 8 i/p NAND gates. – Cheaper.
• NOR gate – Obtained by the modification of the basic NAND Ob i d b h difi i f h b i NAND gate design. – OR gate is built and the o/p is inverted.
• AND & OR gate – AND is produced by inverting the o/p of NAND. – OR gate is produced by inverting the o/p of NOR.
• BUFFER gates. – IC buffers can source and sink more current then the standard TTL gates. the standard TTL gates. – 7437 is quad 2 i/p NAND buffer i.e four 2i/p NAND are obtained to get high o/p current.
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Open Collector Gates.
• Instead of Totem pole output, some TTL have an open collector outputs. • Only the lower transistor of the Totem pole pair is used.
External Drive for TTL Loads • • • •
Tristate Buffer A 0 1
Disable 0 0
X
1
Y 0 1 High High Impedance / Float
• Tristate buffer has 3 states at the output. • Equivalent to a switch • When disable is high, switch opens thus high Wh di bl i hi h it h th hi h impedance or float appears at the input. • Used to connect Registers to common BUS.
CMOS Inverter
Switch Drive T Transistor Drive it Di Operational Amplifier Drive Comparator Drive
– TTL driving External Loads (Page 537)
(Self Study)
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7400 CMOS
CMOS Characteristics • • • • •
Floating Inputs Easily Damaged Compability Sourcing and sinking (1 uA sourcing sinking) Fan out
Problems with IC interfacing • High and low voltage levels can be different f diff for different IC families t IC f ili • The IC power supply requirement can vary from family to family.
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CMOS to TTL Interface •CMOS CMOS Buffer is used Buffer is used •No problem with HIGH input •LOW Input causes problem due to sinking current
Applications (Chapter 11) • Multiplexing Displays • Frequency Counter • Time Measurement
Multiplexing Displays
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Frequency Counter
Time Measurement • See board
HDL • HDL : Hardware description language. Hardware description language. • 2 types of HDL: 2 types of HDL: – Verilog HDL – VHDL : Very High Speed integrated circuit Hardware Description Language.
• Verilog HDL is most widely used today for the circuit simulation and verification circuit simulation and verification. • The language is almost similar to C language.
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Intro to HDL
Structural model of 2 i/p OR gate
module test_circuit (x,y,a,b,c); //module name with port list input a,b,c; //define input port output x,y ; // define output port
module or_gate(a,b,y); input a,b; output y; or g1(y,a,b); /*gate declaration with predefined keyword or
. .//module body begins here with logical relation
. endmodule
representing logic OR, g1 is the user g / defined gate identifier. */
endmodule
Realization of the circuit given below OR Æor(output, input 1, input 2, input 3………. ); NOTÆnot(output, input); AND Æand(output, input 1, input 2, ……. ); *** Verilog accepts up to 12 inputs.
module and_or_combination (a,b,c,d,y); i input a,b,c,d; t b d output y; wire and_op1, and_op2; and g1 (and _op1, a, b); and g2 (and op2 c d); and g2 (and_op2, c, d); or g3 (y, and_op1, and_op2); endmodule
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Realization of the circuit given below module testckt (a,b,c,x,y); input a b c; input a,b,c; output x,y; wire or_op1, or_op2; or g1 (or_op1, a, b) or g2 (or_op2, b, c) nor g3 (x c or op1); nor g3 (x, c, or_op1); nand g4 (y, or_op1, or_op2); endmodule
Dataflow model • Gate level modeling is very easy but requires more space in describing complex circuit. i d ibi l i it • Verilog provides a keyword assign and a set of operators. • We now don’t use intermediate variables like wire or gate structures like and, or etc.
HDL implementation models • Implementation models : – Data flow model – Behavioral model
• Book (Page no: 108) Book (Page no: 108)
List of Verilog operators Relational Operator Less Than Less Than or equal to Greater than Equal to Not equal to
Symbol < <= > == !=
Bitwise operator Bit‐wise NOT Bit‐wise AND Bit‐wise OR Bit‐wise EX‐OR
Symbol ~ & | ^
Logical Operation Logical NOT Logical AND Logical OR
Symbol ! && ||
Arithmetic Operator Binary addition Binary Substraction Binary Multipication Binary Division
Symbol + ‐ * /
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Realize equation y=c’+a’d’+b’d’ module and_or(a,b,c,d,y); input a,b,c,d; output y; assign y=(a&b)|(c&d); endmodule
module realization(a,b,c,d,y); input a,b,c,d; output y; assign y=~c| (~a&~d)|(~b&~d); endmodule
Behavioral model • Statements are executed sequentially following algorithmic description following algorithmic description.
• It uses always keyword followed by a sensitivity list. iti it li t
• Ideally suited to describe a sequential logic circuit.
• The procedural statements following always is executed only if variable within sensitivity list changes its value changes its value.
• This model may be used to describe the combinational circuit but not always preferable.
always x=s? a:b;
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Implementation of D Flip‐flop module dlatch (d, en, q); input d, en; output q; reg q; always @(en or d) if (en) q =d; endmodule
2X1 Mux module mux2to1 (a,d0,d1,y); input a,do,d1; output y; assign y=(~a&d0)|(a&d1); endmodule
module srlatch (s, r, en, q); input s, r, en; output q; reg q; always @(en or s or r) if (en) q=s | (~r&q); endmodule
2X1 Mux module mux2to1 (a,d0,d1,y); input a,do,d1; output y; always y=a? d1:d0; /*conditional assignment*/ endmodule
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