DM-OLEDC15-622

 

1.5’ COLOR OLED DISPLAY WITH SERIAL OR 6800/8080-SERIES MPU PARALLEL INTERFACE   

DM-OLEDC15-622

Contents Revision History Main Features Pin Description Panel Pin Description Module Pin Description Mechanical Drawing Electrical Characteristics Optical Characteristics Timing Characteristics 68XX-Series MPU Parallel Interface Timing Characteristics: 80XX-Series MPU Parallel Interface Timing Characteristics Serial Interface Timing Characteristics: (4-wire SPI) Serial Interface Timing Characteristics: (3-wire SPI) Driver/Controller Information Functional Specification Power down and Power up Sequence Power up Sequence Power down Sequence Reset Circuit Module Schematic Example Initialization Sequence Reliability Warranty and Conditions

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1 Revision History Date 2015-03-13

Changes First release

2 Main Features Item Diagonal Size Display Mode Display Colors Resolution Controller IC Duty Interface Power Supply Active Area Module Dimension Weight

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Specification 1.5 Passive Matrix OLED 262,144 128(RGB) x 128 SSD1351 1/128 Serial or 6800/8080-series MPU Parallel 2.8V 26.855 x 25.864 33.8 x 40.0 9.5

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Unit inch Colors pixel duty V mm mm g

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3 Pin Description 3.1 Panel Pin Description Pin No.

Symbol

1

NC(GND)

2

VCC

3

VCOMH

4

VDDIO

5

VSL

6

N.C.

7~14

D7~D0

15

E/RD#

16

R/W#

17 18

BS0 BS1

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Function Description Reserved Pin (Supporting Pin) The supporting pins can reduce the influences from stresses on the function pins. These pins must be connected to external ground. Power Supply for OEL Panel This is the most positive voltage supply pin of the chip. It must be connected to external source. Voltage Output High Level for COM Signal This pin is the input pin for the voltage output high level for COM signals. A tantalum capacitor should be connected between this pin and VSS. Power Supply for I/O Pin This pin is a power supply pin of I/O buffer. It should be connected to VCI or external source. All I/O signal should have VIH reference to VDDIO. When I/O signal pins (BS0~BS1, D0~D7, control signals​ …​ ) pull high, they should be connected to VDDIO. Voltage Output Low Level for SEG Signal This is segment voltage reference pin. When external VSL is not used, this pin should be left open. When external VSL is used, this pin should connect with resistor and diode to ground. Reserved Pin The N.C. pins between function pins are reserved for compatible and flexible design. Host Data Input/Output Bus These pins are 8-bit bi-directional data bus to be connected to the microprocessor’s data bus. When serial mode is selected, D1 will be the serial data input SDIN and D0 will be the serial clock input SCLK. Unused pins must be connected to VSS except for D2. Read/Write Enable or Read This pin is MCU interface input. When interfacing to a 68XX-series microprocessor, this pin will be used as the Enable (E) signal. Read/write operation is initiated when this pin is pulled high and the CS# is pulled low. When connecting to an 80XX-microprocessor, this pin receives the Read (RD#) signal. Data read operation is initiated when this pin is pulled low and CS# is pulled low. When serial mode is selected, this pin must be connected to VSS. Read/Write Select or Write This pin is MCU interface input. When interfacing to a 68XX-series microprocessor, this pin will be used as Read/Write (R/W#) selection input. Pull this pin to “High” for read mode and pull it to “Low” for write mode. When 80XX interface mode is selected, this pin will be the Write (WR#) input. Data write operation is initiated when this pin is pulled low and the CS# is pulled low. When serial mode is selected, this pin must be connected to VSS. Communicating Protocol Select These pins are MCU interface selection input. See the following table: BS0 BS1 3-wire SPI 1 0

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DM-OLEDC15-622 4-wire SPI 68XX-parallel (8-bit) 80XX-parallel (8-bit)

19

CS#

20

D/C#

21

RES#

22

IREF

23 24

GPIO1 GPIO0

25

N.C.

26

VDD

27

VCI

28

VSS

29

N.C.

30

N.C.(GND)

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0 1 0

0 1 1

Chip Select This pin is the chip select input. The chip is enabled for MCU communication only when CS# is pulled low. Data/Command Control This pin is Data/Command control pin. When the pin is pulled high, the input at D7~D0 is treated as display data. When the pin is pulled low, the input at D7~D0 will be transferred to the command register. For detail relationship to MCU interface signals, please refer to the Timing Characteristics Diagrams. When 3-wire serial mode is selected, this pin must be connected to VSS. Power Reset for Controller and Driver This pin is reset signal input. When the pin is low, initialization of the chip is executed. Current Reference for Brightness Adjustment This pin is segment current reference pin. A resistor should be connected between this pin and VSS. Set the current lower than 12.5uA. General Purpose Input/Output These pins could be left open individually or have signal inputted/outputted. They are able to use as the external DC/DC converter circuit enabled/disabled control or other applications. Reserved Pin The N.C. pins between function pins are reserved for compatible and flexible design. Power Supply for Core Logic Circuit This is a voltage supply pin which is regulated internally from VCI. A capacitor should be connected between this pin & VSS under all circumstances. Power Supply for Operation This is a voltage supply pin. It must be connected to external source & always be equal to or higher than VDD & VDDIO. Ground of OEL System This is a ground pin. It also acts as a reference for the logic pins, the OEL driving voltages, and the analog circuits. It must be connected to external ground. Reserved Pin The N.C. pins between function pins are reserved for compatible and flexible design. Reserved Pin (Supporting Pin) The supporting pins can reduce the influences from stresses on the function pins. These pins must be connected to external ground.

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3.2 Module Pin Description Pin No.

Symbol

1

VCC

2

GND

3

VCC

4-11

D7 - D0

12

E/RD

13

R/W

14

CS

15

DC

16

RES

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Function Description Power Supply for Operation This is a voltage supply pin. It must be connected to external source. Ground This is the ground pins for analog circuits. It must be connected to external ground Power Supply for Operation This is a voltage supply pin. It must be connected to external source. Host Data Input/Output Bus These pins are 8-bit bi-directional data bus to be connected to the microprocessor’s data bus. When serial mode is selected, D1 will be the serial data input SDIN and D0 will be the serial clock input SCLK. Unused pins must be connected to VSS except for D2. Read/Write Enable or Read This pin is MCU interface input. When interfacing to a 68XX-series microprocessor, this pin will be used as the Enable (E) signal. Read/write operation is initiated when this pin is pulled high and the CS# is pulled low. When connecting to an 80XX-microprocessor, this pin receives the Read (RD#) signal. Data read operation is initiated when this pin is pulled low and CS# is pulled low. When serial mode is selected, this pin must be connected to VSS. While using SPI, it must be connected to VCC or Gnd. Read/Write Select or Write This pin is MCU interface input. When interfacing to a 68XX-series microprocessor, this pin will be used as Read/Write (R/W#) selection input. Pull this pin to “High” for read mode and pull it to “Low” for write mode. When 80XX interface mode is selected, this pin will be the Write (WR#) input. Data write operation is initiated when this pin is pulled low and the CS# is pulled low. When serial mode is selected, this pin must be connected to VSS. Chip Select This pin is the chip select input. The chip is enabled for MCU communication only when CS# is pulled low. Data/Command Control This pin is Data/Command control pin. When the pin is pulled high, the input at D7~D0 is treated as display data. When the pin is pulled low, the input at D7~D0 will be transferred to the command register. For detail relationship to MCU interface signals, please refer to the Timing Characteristics Diagrams. When 3-wire serial mode is selected, this pin must be connected to VSS. Power Reset for Controller and Driver This pin is reset signal input. When the pin is low, initialization of the chip is executed.

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4 Mechanical Drawing

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5 Electrical Characteristics Item Supply Voltage for Logic Digital Operation Current Low Level Input Voltage High Level Input Voltage Low Level Output Voltage High Level Output Voltage Operating Temperature Storage Temperature

Symbol VCC Icc V​ IL V​ IH V​ OL V​ OH TOP TST

Condition

Min 2.8

-

Absolute Max Absolute Max

0 0.8xV​ DD 0 0.9xV​ DDIO -30 -40

Typ. 3.3 160 -

Max 3.5 330 0.2xV​ DDIO V​ DDIO 0.1xV​ DDIO V​ DDIO 70 80

Unit V mA V V V V ℃ ℃

6 Optical Characteristics Item View Angles Top View Angles Bottom View Angles Left View Angles Right Response Time (25°C) Brightness Contrast Ratio Lifetime

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Symbol AV AV AH AH Tr + Tf

Min

80 CR 10,000

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Typ 80 80 80 80 20 100 2,000:1

Max

Unit ° ° ° ° us cd/m² Hrs

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DM-OLEDC15-622

7 Timing Characteristics 7.1

68XX-Series MPU Parallel Interface Timing Characteristics:

Symbol  tcycle ​ t​ AS t​ AH t​ DSW t​ DHW t​ DHR t​ OH t​ ACC PW​ CSL PW​ CSH t​ R t​ F

Item Clock Cycle Time Address Setup Time Address Hold Time Write Data Setup Time Write Data Hold Time Read Data Hold Time Output Disable Time Access Time Chip Select Low Pulse Width(Read) Chip Select Low Pulse Width(Write) Chip Select High Pulse Width(Read) Chip Select High Pulse Width(Write) Rise Time Fall Time

Min 300 10 0 40 7 20 120 60 60 60 -

Typ -

Max -

-

70 140

15 15

Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns

V​ -V​ =2.4V to 2.6V, V​ =1.65V, V​ =2.8V, Ta=25​ °C DD​ SS​ DDIO​ CI​

When 8-bit Used: D[7:0] Instead

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7.2 80XX-Series MPU Parallel Interface Timing Characteristics Symbol Item t​ Clock Cycle Time cycle t​ Address Setup Time AS t​ Address Hold Time AH t​ Write Data Setup Time DSW t​ Write Data Hold Time DHW t​ Read Data Hold Time DHR t​ Output Disable Time OH t​ Access Time ACC t​ Read Low Time PWLR t​ Write Low Time PWLW t​ Read High Time PWHR t​ Write High Time PWHW t​ Chip Select Setup Time CS t​ Chip Select Hold Time to Read Signal CSH t​ Chip Select Hold Time CSF t​ Rise Time R t​ Fall Time F V​ -V ​ =2.4V to 2.6V, V​ =1.65V, V​ =2.8V, Ta=25°C DD​ SS​ DDIO​ CI​

Min 300 10 0 40 7 20 150 60 60 60 0 0 20 -

Typ -

Max -

-

70 140

15 15

Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns

When 8-bit Used: D[7:0] Instead

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7.3 Serial Interface Timing Characteristics: (4-wire SPI) Symbol Item t​ Clock Cycle Time cycle t​ Address Setup Time AS t​ Address Hold Time AH t​ Chip Select Setup Time CSS t​ Chip Select Hold Time CSH t​ Write Data Setup Time DSW t​ Write Data Hold Time DHW t​ Clock Low Time CLKL t​ Clock High Time CLKH t​ Rise Time R t​ Fall Time F V​ -V ​ =2.4V to 2.6V, V​ =1.65V, V​ =2.8V, Ta=25°C DD​ SS​ DDIO​ CI​

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Min 50 15 15 20 10 15 15 20 20 -

Typ -

Max -

-

-

15 15

Unit ns ns ns ns ns ns ns ns ns ns ns

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DM-OLEDC15-622

7.4 Serial Interface Timing Characteristics: (3-wire SPI) Symbol Item t​ Clock Cycle Time cycle t​ Chip Select Setup Time CSS t​ Chip Select Hold Time CSH t​ Write Data Setup Time DSW t​ Write Data Hold Time DHW t​ Clock Low Time CLKL t​ Clock High Time CLKH t​ Rise Time R t​ Fall Time F V​ -V ​ =2.4V to 2.6V, V​ =1.65V, V​ =2.8V, Ta=25°C DD​ SS​ DDIO​ CI​

Min 50 20 10 15 15 20 20 -

Typ -

Max -

15 15

Unit ns ns ns ns ns ns ns ns ns

8 Driver/Controller Information Built-in SSD1351 Controller: https://drive.google.com/file/d/0B0U8oRNrY9XuZHYzUm95blVwZEU/view?usp=sharing

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9 Functional Specification 9.1 Power down and Power up Sequence To protect OEL panel and extend the panel life time, the driver IC power up/down routine should include a delay period between high voltage and low voltage power sources during turn on/off. It gives the OEL panel enough time to complete the action of charge and discharge before/after the operation. 9.1.1 1. 2. 3. 4. 5. 6. 7. 9.1.2 1. 2. 3.

Power up Sequence  Power up V​ DD&V ​ ​ DDIO Send Display off command Initialization Clear Screen Power up V​ CC Delay 100ms(When V​ CC is ​ stable) Send Display on command Power down Sequence  Send Display off command Power down V​ CC Delay 100ms (When V​ is reach 0 and CC​ panel is completely discharges)

4.

Power down V​ &V​ DD​ DDIO

9.2 Reset Circuit When RES# input is low, the chip is initialized with the following status: 1. Display is OFF 2. 128(RGB) x 128 Display Mode 3. Normal segment and display data column and row address mapping (SEG0 mapped to column address 00h and COM0 mapped to row address 00h) 4. Display start line is set at display RAM address 0 5. Column address counter is set at 0 6. Normal scan direction of the COM outputs 7. Command A2h, B1h, B3h, BBh, BEh are locked by command FDh

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10 Module Schematic

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11 Example Initialization Sequence OLED_RST_Clr(); Delay(1); OLED_RST_Set(); OLED_RST_Set(); Set_Command_Lock(0x12); Set_Command_Lock(0xB1); Set_Display_On_Off(0x00); Set_Display_Clock(0xF1); Set_Multiplex_Ratio(0x7F); Set_Display_Offset(0x00); Set_Start_Line(0x00); Set_Remap_Format(0x74);

// Unlock Driver IC (0x12/0x16/0xB0/0xB1) // Unlock All Commands (0x12/0x16/0xB0/0xB1) // Display Off (0x00/0x01) // Set Clock as 90 Frames/Sec // 1/128 Duty (0x0F~0x7F) // Shift Mapping RAM Counter (0x00~0x7F) // Set Mapping RAM Display Start Line (0x00~0x7F) // Set Horizontal Address Increment // Column Address 0 Mapped to SEG0 // Color Sequence D[15:0]=[RRRRR:GGGGGG:BBBBB] // Scan from COM127 to COM0 // Enable COM Split Odd Even // 65,536 Colors Mode (0x74) // * 262,144 Colors Mode (0xB4) Set_GPIO(0x00); // Disable GPIO Pins Input Set_Function_Selection(0x01); // Enable Internal VDD Regulator // Select 8-bit Parallel Interface Set_VSL(0xA0); // Enable External VSL Set_Contrast_Color(0xC8,0x80,0xC8); // Set Contrast of Color A (Red) // Set Contrast of Color B (Green) // Set Contrast of Color C (Blue) Set_Master_Current(Brightness); // Set Scale Factor of Segment Output Current Control Set_Gray_Scale_Table(); // Set Pulse Width for Gray Scale Table Set_Phase_Length(0x32); // Set Phase 1 as 5 Clocks & Phase 2 as 3 Clocks Set_Precharge_Voltage(0x17); // Set Pre-Charge Voltage Level as 0.50*VCC Set_Display_Enhancement(0xA4);// Enhance Display Performance Set_Precharge_Period(0x01); // Set Second Pre-Charge Period as 1 Clock Set_VCOMH(0x05); // Set Common Pins Deselect Voltage Level as 0.82*VCC Set_Display_Mode(0x02); // Normal Display Mode (0x00/0x01/0x02/0x03) Fill_RAM(0x00,0x00); // Clear Screen Set_Display_On_Off(0x01); // Display On (0x00/0x01)

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12 Reliability Test Item High Temperature Storage Low Temperature Storage High Temperature Operation

Low Temperature Operation High Temperature/ Humidity Operation

Thermal Shock Resistance

Content of Test Endurance test applying the high storage temperature for a long time. Endurance test applying the high storage temperature for a long time. Endurance test applying the electric stress (Voltage & Current) and the thermal stress to the element for a long time. Endurance test applying the electric stress under low temperature for a long time. The module should be allowed to stand at 60℃,90%RH max, for 96hrs under no-load condition excluding the polarizer. Then taking it out and drying it at normal temperature. The sample should be allowed stand the following 10 cycles of operation

Test Condition 80℃ 200hrs -30℃ 200hrs 70℃ 200hrs

-20 ℃ 200hrs

Note 2 1,2

-

1

60℃,90%RH 96hrs 1,2

-30℃/70℃ 10 cycles -

Vibration Test

Static Electricity Test

Endurance test applying the vibration during transportation and using

Endurance test apply the electric stress to the terminal.

Total fixed amplitude: 15mm; Vibration: 10~55Hz; One cycle 60 seconds to 3 directions of X, Y, Z, for each 16 minutes. VS=800V, RS=1.5k​ Ω​ , CS=100pF, 1 time.

3

-

Note1: No dew condensation to be observed. Note2: The function test shall be conducted after 4 hours storage at the normal. Temperature and humidity after remove from the rest chamber. Note3: The packing have to including into the vibration testing.

13 Warranty and Conditions http://www.displaymodule.com/pages/faq

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