DM-OLEDC17-623
1.69” COLOR OLED DISPLAY WITH SERIAL OR 6800/8080-SERIES MPU PARALLEL INTERFACE
DM-OLEDC17-623
Contents Revision History Main Features Pin Description Panel Pin Description Module Pin Description Mechanical Drawing Electrical Characteristics Optical Characteristics Timing Characteristics 68XX-Series MPU Parallel Interface Timing Characteristics: 80XX-Series MPU Parallel Interface Timing Characteristics Serial Interface Timing Characteristics: Functional Specification Power down and Power up Sequence Power up Sequence Power down Sequence Reset Circuit Reference Parameters Driver/Controller Information Module Schematic Example Initialization Sequence Reliability Warranty and Conditions
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1 Revision History Date 2015-03-13 2015-04-17
Changes First release Schematic update.
2 Main Features Item Diagonal Size Display Mode Display Colors Resolution Controller IC Duty Interface Power Supply Active Area Module Dimension Weight
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Specification 1.69 Passive Matrix OLED 262,144 160(RGB) x 128 SEPS525 1/128 Serial or 6800/8080-series MPU Parallel 2.8V 33.575 x 26.864 39.9 x 60 15.0
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Unit inch Colors pixel duty V mm mm g
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3 Pin Description 3.1 Panel Pin Description Pin No. 1 2 3 4
Symbol NC VSSH VDDH VSDH
5
IREF
6
OSCA2
7
OSCA1
8 9 10 11 12
VDDIO VSYNCO VSYNC HSYNC DOTCLK
13
ENABLE
16~24
D17~D9
25
RS
26
CSB
27
RDB
28
WRB
29
RESETB
30 31 32 33 34 35
VSS VDD VSDH VSSH VDDH NC
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Function Description No Connection Scan Driver Ground Data, Scan Driver Power Supply Data Driver Ground Current Reference for Brightness Adjustment Tie 68KΩ resistor to VSS. Fine adjustment for oscillation Tie 10 KΩ resistor to OSCA1 between OSCA2. When the external clock mode is selected, OSCA1 is used external clock input. MPU I/F PAD Power Supply RGB Mode Functional Pins VSYNCO: Vertical Sync. Output VSYNC: Vertical Sync. Input HSYNC: Horizontal Sync. Input DOTCLK: Dot Clock Input ENABLE: Video Enable Input Host Data Input/Output Bus These pins are 9-bit bi-directional data bus to be connected with MCU data bus. PS Description 1 8_bit bus : D[17:10] 9_bit bus : D[17:9] 0 D[17]SCL : Synchronous clock input D[16]SDI : Serial data input D[15]SDO : Serial data output Selects the data/command Low: command, High: parameter/data Chip Select Low: SEPS525 is selected and can be accessed High: SEPS525 is not selected and cannot be accessed Read or Read/Write Enable 80-system bus interface: read strobe signal (active low) 68-system bus interface: bus enable strobe (active high) When serial mode, fix it to VDD or VSS level Write or Read/Write Select 80-system bus interface: write strobe signal (active low) 68-system bus interface: read/write select Low: write, High: read When serial mode, fix it to VDD or VSS level Chip Reset Reset SEPS525 (active low) Logic Ground Logic Power Supply Data Driver Ground Scan Driver Ground Data, Scan Driver Power Supply No Connection
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3.2 Module Pin Description Pin No.
Symbol
1
VCC
2 3 4 5 6
GND VSYNC HSYNC DOTCLK ENABLE
7-15
D17 - D9
16
RS
17
CSB
18
RDB
19
WRB
20
RESETB
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Function Description Power Supply for Operation This is a voltage supply pin. It must be connected to external source. Ground Vertical Sync. Input Horizontal Sync. Input Dot Clock Input Video Enable Input Host Data Input/Output Bus These pins are 9-bit bi-directional data bus to be connected with MCU data bus. PS Description 1 8_bit bus : D[17:10] 9_bit bus : D[17:9] 0 D[17]SCL : Synchronous clock input D[16]SDI : Serial data input D[15]SDO : Serial data output Selects the data/command Low: command, High: parameter/data Chip Select Low: SEPS525 is selected and can be accessed High: SEPS525 is not selected and cannot be accessed Read or Read/Write Enable 80-system bus interface: read strobe signal (active low) 68-system bus interface: bus enable strobe (active high) When serial mode, fix it to VDD or VSS level Write or Read/Write Select 80-system bus interface: write strobe signal (active low) 68-system bus interface: read/write select Low: write, High: read When serial mode, fix it to VDD or VSS level Chip Reset Reset SEPS525 (active low)
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4 Mechanical Drawing
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5 Electrical Characteristics Item Supply Voltage Operation Current for VDD Low Level Input Voltage High Level Input Voltage Low Level Output Voltage High Level Output Voltage Operating Temperature Storage Temperature
Symbol VDD I VDD V IL V IH V OL V OH TOP TST
Condition -
Absolute Max Absolute Max
Min 2.8 0 0.8xV DD V -0.4 DD -30 -40
Typ. 3.3 180 -
Max 3.5 350 0.4 V DD 0.4 70 80
Unit V mA V V V V ℃ ℃
6 Optical Characteristics Item View Angles Top View Angles Bottom View Angles Left View Angles Right Response Time (25°C) Brightness Contrast Ratio Lifetime
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Symbol AV AV AH AH Tr + Tf
Min
70 CR 10,000
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Typ 80 80 80 80 20 100 1,000:1
Max
Unit ° ° ° ° us cd/m² Hrs
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7 Timing Characteristics 7.1
68XX-Series MPU Parallel Interface Timing Characteristics:
Symbol Item Write Timing t Address setup timing AS6 t Address hold timing AH6 t System cycle timing CYC6 t Write “L” pulse width ELW6 t Write “H” pulse width EHW6 t Data setup timing DS6 t Data hold timing DH6 Read Timing t Address setup timing AH6 t Address hold timing AS6 t System cycle timing CYC6 t Read “L” pulse width ELR6 t Read “H” pulse width EHR6 t Read data output delay time RDD6 t Data hold timing RDH6 All the timing reference is 10% and 90% of VDD
Min 5 5 100 45 45 40 10 10 10 200 90 90 -
Typ
Max
-
-
-
-
ns ns ns ns ns ns ns
70 70
ns ns ns ns ns ns ns
-
Unit
Write Timing
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Read Timing
7.2 80XX-Series MPU Parallel Interface Timing Characteristics Symbol Item Write Timing t Address setup timing AS8 t Address hold timing AH8 t System cycle timing CYC8 t Write “L” pulse width WRLW8 t Write “H” pulse width WRHW8 t Data setup timing DS8 t Data hold timing DH8 Read Timing t Address setup timing AH8 t Address hold timing AS8 t System cycle timing CYC8 t Read “L” pulse width RDLR8 t Read “H” pulse width RDHR8 t Read data output delay time RDD8 t Data hold timing RDH8 All the timing reference is 10% and 90% of VDD
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Min 5 5 100 45 45 30 10 10 10 200 90 90 0 0
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Typ
Max
-
-
-
-
ns ns ns ns ns ns ns
60 60
ns ns ns ns ns ns ns
-
Unit
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Read Timing
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7.3 Serial Interface Timing Characteristics: Symbol Item t Serial clock cycle cycs t SCL “H” pulse width SHW t SCL “L” pulse width SLW t Data setup timing DSS t Data hold timing DHS t CSB-SCL timing CSS t CSB-hold timing CSH All the timing reference is 10% and 90% of VDD
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Min 60 25 25 25 25 25 25
Typ -
Max -
-
-
Unit ns ns ns ns ns ns ns
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8 Functional Specification 8.1
Power down and Power up Sequence
To protect OEL panel and extend the panel life time, the driver IC power up/down routine should include a delay period between high voltage and low voltage power sources during turn on/off. It gives the OEL panel enough time to complete the action of charge and discharge before/after the operation. 8.1.1 1. 2. 3. 4. 5. 6. 8.1.2 1. 2. 3.
Power up Sequence Power up V &V DD DDIO Send Display off command Clear Screen Power up VDDH Delay 100ms(When VDD is stable) Send Display on command Power down Sequence Send Display off command Power down VDDH Delay 100ms (When VDDH is reach 0 and panel is completely discharges)
4.
Power down V &V DD DDIO
8.2 Reset Circuit When RESETB input is low, the chip is initialized with the following status: 1. Frame frequency: 90Hz 2. OSC: internal OSC 3. Internal OSC: ON 4. DDRAM write horizontal address: MX1 = 00h, MX2 = 9Fh 5. DDRAM write vertical address: MY1 = 00h, MY2 = 7Fh 6. Display data RAM write: HC = 1, VC = 1, HV = 0 7. RGB data swap: OFF 8. Row scan shift direction: G0, G1, … , G126, G127 9. Column data shift direction: S0, S1, … , S478, S479 10. Display ON/OFF: OFF 11. Panel display size: FX1 = 00h, FX2 = 9Fh, FY1 = 00h, FY2 = 7Fh 12. Display data RAM read column/row address: FAC = 00h, FAR = 00h 13. Precharge time(R/G/B): 0 clock 14. Precharge current(R/G/B): 0 uA 15. Driving current(R/G/B): 0 uA
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8.3 Reference Parameters Command Parameter Set Display ON_OFF Set SOFT_RST Set REDUCE_CURRENT Set OSC_CTL Set CLOCK_DIV Set PRECHARGE_TIME_R Set PRECHARGE_TIME_G Set PRECHARGE_TIME_B Set PRECHARGE_CURRENT_R Set PRECHARGE_CURRENT_G Set PRECHARGE_CURRENT_B Set DRIVING_CURRENT_R Set DRIVING_CURRENT_G Set DRIVING_CURRENT_B Set DISPLAY_MODE_SET Set RGB_IF Set RGB_POL Set MEMORY_WRITE_MODE Set MX1_ADDR Set MX2_ADDR Set MY1_ADDR Set MY2_ADDR Set MEMORY_ACCESS_POINTER X Set MEMORY_ACCESS_POINTER Y Set DUTY Set DSL Set D1_DDRAM_FAC Set D1_DDRAM_FAR Set D1_DDRAM_SAC Set D1_DDRAM_SAR Set SCR1_FX1 Set SCR1_FX2 Set SCR1_FY1 Set SCR1_FY2 Set IREF Set DISP_ON_OFF
Normal Operation Mode Power Saving Mode 0x06 , 0x00 0x05 , 0x00 0x04 , 0x01 wait 1ms 0x04,0x00 0x02 , 0x01 0x03 , 0x09 0x08 , 0x03 0x08 , 0x00 0x09 , 0x05 0x09 , 0x00 0x0A , 0x05 0x0A , 0x00 0x0B , 0x56 0x0B , 0x00 0x0C , 0x4D 0x0C , 0x00 0x0D , 0x46 0x0D , 0x00 0x10 , 0x0A 0x10 , 0x0D 0x11 , 0x0A 0x11 , 0x0C 0x12 , 0x0A 0x12 , 0x0B 0x13 , 0x00 0x14 , 0x01 0x15 , 0x00 0x16 , 0x76 0x17 , 0x00 0x18 , 0x9F 0x19 , 0x00 0x1A , 0x7F 0x20 , 0x00 0x21 ,0x00 0x28 , 0x7F 0x29 , 0x00 0x2E , 0x00 0x2F , 0x00 0x31 , 0x00 0x32 , 0x00 0x33 , 0x00 0x34 , 0x9F 0x35 , 0x00 0x36 , 0x7F 0x80 , 0x00 0x06 , 0x01
9 Driver/Controller Information Built-in SEPS525 Controller: https://drive.google.com/file/d/0B0U8oRNrY9XuQU5YejBZdk5PRGs/view?usp=sharing
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10 Module Schematic
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11 Example Initialization Sequence OLED_RST_Clr(); Delay(10); OLED_RST_Set(); Set_Power_Save(0x01); uDelay(200);
// Set Normal Driving Current // Disable Oscillator Power Down // Enable Power Save Mode Set_Power_Save(0x00); // Set Normal Driving Current uDelay(200); // Disable Oscillator Power Down // Disable Power Save Mode Software_Reset(0x00); // Set All Internal Register Value as Normal Mode Set_Display_On_Off(0x00); // Display Off (0x00/0x01) Set_Clock_Control(0x01); // Set EXPORT1 Pin at Internal Clock // Oscillator operates with external resistor. // Internal Oscillator On Set_Display_Clock(0x30); // Set Clock as 90 Frames/Sec Set_Multiplex_Ratio(0x7F); // 1/128 Duty (0x0F~0x7F) Set_Display_Offset(0x00,0x00); // Shift Mapping RAM Counter Set_Start_Line(0x00); // Set Mapping RAM Display Start Line (0x00~0x7F) Set_RGB_IF(0x31); // Set MCU Interface Mode Set_RGB_POL(0x00); // Set RGB Interface Polarity as Active Low // Dot Clock Polarity Sampled as Rising Edge // Disable Vertical Synchronization Output on VSYNCO Pin Set_Display_Mode(0x00); // Set Color Sequence D[15:0]=[RRRRR:GGGGGG:BBBBB] // Alternative Gate Pin Configuration // Scan from G0 to G127 // Column Address 0 Mapped to S0 // One Screen Mode // Normal Display Set_Pixel_Format(0x66|((Color_Depth<<4)&0x70)); // Set Horizontal Address Increment // Vertical Address Increment // The data is continuously written horizontally. // Enable 8-bit Bus Interface // 65,536 Colors Mode (0x66) // * 262,144 Colors Mode (0x76) Set_Driving_Current(0x2F,0x31,0x1E); // Set Driving Current of Red // Set Driving Current of Green // Set Driving Current of Blue Set_Gray_Scale_Table(); // Set Pulse Width for Gamma Table Set_Precharge_Period(0x03,0x04,0x01); // Set Pre-Charge Time of Red // Set Pre-Charge Time of Green // Set Pre-Charge Time of Blue Set_Precharge_Current(0x1A,0x19,0x0A); // Set Pre-Charge Current of Red // Set Pre-Charge Current of Green // Set Pre-Charge Current of Blue Set_IREF(0x00); // Set Reference Voltage Controlled by External Resistor First_Screen(0x00,0x9F,0x00,0x7F); Fill_RAM(0x00,0x00); // Clear Screen Set_Display_On_Off(0x01); // Display On (0x00/0x01)
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12 Reliability Test Item High Temperature Storage Low Temperature Storage High Temperature Operation
Low Temperature Operation High Temperature/ Humidity Operation
Thermal Shock Resistance
Content of Test Endurance test applying the high storage temperature for a long time. Endurance test applying the high storage temperature for a long time. Endurance test applying the electric stress (Voltage & Current) and the thermal stress to the element for a long time. Endurance test applying the electric stress under low temperature for a long time. The module should be allowed to stand at 60℃,90%RH max, for 96hrs under no-load condition excluding the polarizer. Then taking it out and drying it at normal temperature. The sample should be allowed stand the following 10 cycles of operation
Test Condition 80℃ 200hrs -30℃ 200hrs 70℃ 200hrs
-20 ℃ 200hrs
Note 2 1,2
-
1
60℃,90%RH 96hrs 1,2
-30℃/70℃ 10 cycles -
Vibration Test
Static Electricity Test
Endurance test applying the vibration during transportation and using
Endurance test apply the electric stress to the terminal.
Total fixed amplitude: 15mm; Vibration: 10~55Hz; One cycle 60 seconds to 3 directions of X, Y, Z, for each 16 minutes. VS=800V, RS=1.5kΩ, CS=100pF, 1 time.
3
-
Note1: No dew condensation to be observed. Note2: The function test shall be conducted after 4 hours storage at the normal. Temperature and humidity after remove from the rest chamber. Note3: The packing have to including into the vibration testing.
13 Warranty and Conditions http://www.displaymodule.com/pages/faq
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