EC6304 ELECTRONIC CIRCUITS-I 1- By EasyEngineering.net.pdf ...

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EC6304- ELECTRONIC CIRCUITS – I OBJECTIVES: The student should be made to • Learn about biasing of BJTs and MOSFETs • Design and construct amplifiers • Construct amplifiers with active loads • Study high frequency response of all amplifiers UNIT I - BIASING OF DISCRETE BJT AND MOSFET DC Load line, operating point, Various biasing methods for BJT-Design-Stability-Bias compensation, Thermal stability, Design of biasing for JFET, Design of biasing for MOSFET UNIT II - BJT AMPLIFIERS Small signal Analysis of Common Emitter-AC Loadline, Voltage swing limitations, Common collector and common base amplifiers – Differential amplifiers- CMRR- Darlington AmplifierBootstrap technique - Cascaded stages - Cascode Amplifier, UNIT III - JFET AND MOSFET AMPLIFIERS Small signal analysis of JFT amplifiers- Small signal Analysis of MOSFET and JFET, Common source amplifier, Voltage swing limitations, Small signal analysis of MOSFET and JFET Source follower and Common Gate amplifiers, - BiMOS Cascode amplifier UNIT IV - FREQUENCY ANALYSIS OF BJT AND MOSFET AMPLIFIERS Low frequency and Miller effect, High frequency analysis of CE and MOSFET CS amplifier, Short circuit current gain, cut off frequency – fα and fβ unity gain and Determination of bandwidth of single stage and multistage amplifiers UNIT V - IC MOSFET AMPLIFIERS IC Amplifiers- IC biasing Current steering circuit using MOSFET- MOSFET current sourcesPMOS and NMOS current sources. Amplifier with active loads - enhancement load, Depletion load and PMOS and NMOS current sources load- CMOS common source and source followerCMOS differential amplifier- CMRR. TOTAL (L: 45+T: 15): 60 PERIODS OUTCOMES: Upon Completion of the course, the students will be able to: • Design circuits with transistor biasing. • Design simple amplifier circuits. • Analyze the small signal equivalent circuits of transistors. • Design and analyze large signal amplifiers.

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TEXT BOOK: 1. Donald .A. Neamen, Electronic Circuit Analysis and Design –2nd Edition,Tata Mc Graw Hill, 2009. REFERENCES: 1. Adel .S. Sedra, Kenneth C. Smith, “Micro Electronic Circuits”, 6th Edition, Oxford University Press, 2010. 2. David A., “Bell Electronic Devices and Circuits”, Oxford Higher Education Press, 5th Editon, 2010 3. Behzad Razavi, “Design of Analog CMOS Integrated Circuits”, Tata Mc Graw Hill, 2007. 4. Paul Gray, Hurst, Lewis, Meyer “Analysis and Design of Analog Integrated Circuits”, 4thEdition ,John Willey & Sons 2005 5. Millman.J. and Halkias C.C, “Integrated Electronics”, Mc Graw Hill, 2001. 6. D.Schilling and C.Belove, “Electronic Circuits”, 3rd Edition, Mc Graw Hill, 1989.

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Sl.No UNIT 1 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 1.10 1.11 1.12 1.12.1 1.12.2 1.13 1.14 UNIT 2 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 2.9.1 2.9.2 2.10 2.11 2.12 2.13 2.14 2.14.1 2.14.2

Contents Biasing of Discrete BJT and MOSFET Introduction Need for Biasing Load line and Variation of quiescent point Biasing Methods Fixed Bias (Base Resistor Bias) Requirements of a biasing circuit Method of stabilizing the Q point Stability Factors Collector to Base Bias circuit Modified collector to base bias circuit Voltage divider bias circuit Compensation technique Diode Compensation Techniques Thermistor Compensation FET Biasing Biasing of MOSFET BJT Amplifiers Introduction Common Emitter Amplifier Common Collector Amplifier Common Base Amplifier Small Signal Low Frequency H-parameter Model h-Parameters for all three configurations Midband analysis of BJT Single Stage Amplifiers Introduction of Differential Amplifier Transistorised Differential Amplifier Differential Mode Operation Common Mode Operation Configurations of Differential Amplifier D.C. Analysis of Differential Amplifier A.C. Analysis of Differential Amplifier using h-Parameters Common Mode rejection Ratio (CMRR) Techniques of Improving Input Impedance Darlington Transistors Bootstrap Emitter Follower

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01 02 02 09 10 14 15 15 17 18 20 25 25 28 30 37 52 53 54 54 55 56 59 69 71 73 74 74 75 77 81 82 82 87

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UNIT 3 3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9 3.10 3.11 3.12

JFET and MOSFET Amplifiers JFET Amplifiers JFET low frequency a.c Equivalent Circuit Common Source Amplifier with Fixed Bias Common Source Amplifier with Self Bias (Bypassed Rs) Common Source Amplifier with Self Bias (Un bypassed Rs) Common source amplifier with Voltage divider bias (bypassed Rs) Common source amplifier with Voltage divider bias (unbypassed Rs) Common Drain Amplifier Common Gate Amplifier Multistage Amplifiers Small signal Analysis of MOSFET Cascaded Amplifiers

UNIT 4 Frequency Analyses of BJT and MOSFET Amplifiers 4.1 General shape of frequency response of Amplifiers 4.2 Definition of cut-off frequencies and Bandwidth 4.3 Low frequency analysis of amplifier to obtain lower cut-off frequency 4.4 Effect of various capacitors on frequency response 4.5 Miller Theorem 4.6 Low frequency analysis of BJT 4.7 Low frequency analysis of FET amplifier 4.8 Hybrid - π equivalent circuits of BJTs 4.9 High frequency analysis of FET 4.10 Frequency Response of Multistage Amplifiers 4.11 Rise time and its Relation to Upper Cut-off Frequency 4.12 Relation between Bandwidth and Rise time UNIT 5 5.1 5.2 5.3 5.4

IC MOSFET Amplifiers Integrated Circuit Amplifier IC Design Biasing - Basic MOSFET current source MOS current-steering circuits

101 101 101 102 104 105 107 107 110 113 115 119 122 122 123 126 126 127 131 133 147 154 156 158 162 162 162 163

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5.5 5.6 5.7

NMOS Current Sources and Sinks PMOS Current Source MOSFET Differential amplifier

165 166 166

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UNIT I BIASING OF DISCRETE BJT AND MOSFET 1.1 Introduction BJT consists of 2 PN junctions. It has three terminals: emitter, base and collector. Transistorcan be operated in three regions, namely cut-off, active and saturation by applying proper biasing conditions.

Region of Operation Emitter Base Junction Collector Base Junction Cut-off Reverse biased Reverse biased Active Forward biased Reverse biased Saturation Forward biased Forward biased • Active: – Most important mode, e.g. for amplifier operation and switching application – The region where current curves are practically flat. • Saturation: – Barrier potential of the junctions cancels each other out causing a virtual short. – Ideal transistor behaves like a closed switch. • Cutoff: – Current reduced to zero – Ideal transistor behaves like an open switch. In order to operate transistor in the desired region we have to apply external d.c. voltages of correct polarity and magnitude to the two junctions of the transistor. This is nothing but the biasing of the transistor. When we bias a transistor we establish a certain current and voltage conditions for the transistor. These conditions are known as operating conditions or d.c. operating point or quiescent point. The operating point must be stable for proper operation of the transistor. However, the operating point shifts with changes in transistor parameters such as β, Ico and VBE. As transistor parameters are temperature dependent, the operating point also varies with changes in temperature.

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1.2 Need for biasing

Fig.1.1 (a) Bias establishes the DC operating point for proper linear operation of an amplifier. If an amplifier is not biased with correct DC voltages on the input and output, it can go into saturation or cutoff when an input signal is applied. Figure 1.1 shows the effects of proper and improper DC biasing of an inverting amplifier. In part (a), the output signal is an amplified replica of the input signal except that it is inverted, which means that it is 1800 out of phase with the input. The output signal swings equally above and below the dc bias level of the output, VDC(out).

Fig.1.1 (b), (c) Improper biasing can cause distortion in the output signal, as illustrated in parts (b) and (c). Part (b) illustrates limiting of the positive portion of the output voltage as a result of a Qpoint (dc operating point) being too close to cutoff. Part (c) shows limiting of the negative portion of the output voltage as a result of a de operating point being too close to saturation. 1.3 Load line and Variation of quiescent point Biasing is the application of dc voltages to establish a fixed level of current and voltage. For transistor amplifiers the resulting dc current and voltage establish an operating point on the characteristics that define the region that will be employed for amplification of the applied signal. Since the operating point is a fixed point on the characteristics, it is also called the quiescent point (abbreviated Q-point). The operating point of a device, also known as bias

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point, quiescent point, or Q-point, is the point on the output characteristics that shows the DC collector–emitter voltage (Vce) and the collector current (Ic) with no input signal applied. Consider the fixed bias circuit,

Fig 1.2 We have,

We can draw a straight line on the graph of IC versus VCE which is having slope -1/Rc.To determine the two points on the line we assume VCE = VCC and VCE =0 a) When VCE =VCC ; IC =0 and we get a point A b) When VCE=0 ; IC=VCC/RC and we get a point B The figure below shows the output characteristic curves for the transistor in CE mode. The DC load line is drawn on the output characteristic curves. Load line - To draw load line, we have to find saturation current and the cutoff voltage. Saturation point - The point at which the load line intersects the characteristic curve near the collector current axis is referred to as the saturation point. At this point of time, the current through the transistor is maximum and the voltage across collector is minimum for a given value of load. So, saturation current for the fixed bias circuit, Ic (sat) =Vcc/Rc . Cutoff point -The point where the load line intersects the cutoff region of the collector curves is referred as the cutoff point (i.e. end of load line). At this point, collector current is approximately zero and emitter is grounded for fixed bias circuit. so, Vce (cut) = Vc = Vcc Operating point - The "Q point" for a transistor amplifier circuit is the point along its operating region in a "quiescent ", where no input signal gets amplified. The figure below shows the output characteristic curves for the transistor in CE mode with points A and B, and line drawn between them. The line drawn between points A and B is called d.c load line. The d.c word indicates that only d.c conditions are considered, i.e input signal is assumed to be zero.

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Fig 1.3 The d.c load line is a plot of IC versus VCE. For a given value of Rc and a given value of Vcc. So, it represents all collector current levels and corresponding collector emitter voltages that can exist in the circuit. Knowing any one of Ic, IB, or VCE , it is easy to determine the other two from the load line. The slope of the d.c load line depends on the value of RC. It is the negative and equal to reciprocal of the RC. Applying KVL to the base circuit, we get

The intersection of curves of different values IB of with d.c load line gives different operating points. For different values of IB, we have different intersection points such as P, Q and R. Selection of operating point The operating point can be selected at different positions on the d.c load line, near saturation region, near cut-off region or at the centre, i.e in the active region. The selection of operating point will depend on its application. When transistor is used as an amplifier, the Q point should be selected at the center of the d.c. load line to prevent any possible distortion in the amplified output signal. Case 1 Biasing circuit is designed to fix a Q point at point P which is very near to the saturation region. It results collector current is clipped at the positive half cycle. i.e. distortion is present at the output. Therefore, point P is not a suitable operating point.

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Fig 1.4 Case 2 Biasing circuit is designed to fix a Q point at point R as shown in Fig. Point R is very near to the cut-off region. Here, the collector current is clipped at the negative half cycle. So, point R is also not a suitable operating point.

. Fig 1.5 Case 3 Biasing circuit is designed to fix a Q point at point Q as shown in Fig.. The output signal is sinusoidal waveform without any distortion. Thus point Q is the best operating point.

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Fig 1.6 DC Load Line (Example)

Fig 1.7 The figure 1.7 shows the biasing of transistor in common emitter configuration. In Figure 1.8, we assign three values to IB and observe what happens to IC and VCE. First, VBB is adjusted to produce an IB of 200 A, as shown in Figure 1.8(a), Since IC = βDC IB, the collector current is 20 mA, as indicated, and VCE = VCC - IcRc = 10 V - (20 mA) (220 Ω) = 10 V - 4.4 V = 5.6 V This Q-point is shown on the graph of Figure 1.3(b) as Q1. Next, as shown in Figure 1.8(b), VBB is increased to produce an IB of 300 µA and an Ic of 30mA. VCE = 10 V - (30 mA) (220 Ω) = 10V – 6.6 V = 3.4 V The Q-point for this condition is indicated by Q2 on the graph. Finally. as in Figure 1.8 (c), VBB is increased to give an IB of 400 µA and an Ic of 40 mA. VCE = 10 V - (40 mA) (220 Ω) = 10 V - 8.8 V = 1.2 V Q3 is the corresponding Q-point on the graph.

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Figure 1.8 increases, Ic increases and VCE decreases. When IB decreases, Ic Notice that when IB decreases and VCE increases. As VBB is adjusted up or down, the dc operating point of the transistor moves along a sloping straight line, called the DC load line, connecting each separate Q-point.

Figure 1.9 SCE

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At any point along the line, values of IB, Ic, and VCE can be picked off the graph, as shown in Figure1.9. The dc load line intersects the VCE axis at 10 V. The point where VCE = VCC. This is the transistor cutoff point because IB and IC are zero (ideally). Actually, there is a small leakage current, ICBO , at cutoff as indicated, and therefore VCE is slightly less than 10 V but normally this can be neglected. The dc load line intersects the IC axis at 45.5 mA ideally. This is the transistor saturation point because IC is maximum at the point where VCE = 0 V and IC = VCC / RC. Actually, there is a small voltage (VCE (sat)) across the transistor, and IC(sat) is slightly less than 45.5 mA, as indicated in Figure 1.4. Note that Kirchhoff's voltage law applied around the collector loop gives, VCC - ICRC - VCE = 0. These results in a straight line equation for the load line of the form y = mx + b as follow: IC = - (1/RC) VCE +VCC / RC Where, - (1/RC) is the slope and VCC / RC is the y-axis intercept point. Variation of quiescent point due to hFE variation within manufacturers tolerance It is clear that the biasing circuit should be designed to fix the operating point or Q point at the center of the active region. But only fixing of the operating point is not sufficient. While designing the biasing circuit, care should be taken so that the operating point will not shift into an undesirable region (i.e. into cut-off or saturation region). Designing the biasing circuit to stabilize the Q point is known as bias stability. Two important factors are to be considered while designing the biasing circuits which are responsible for, shifting the operating point. I. Temperature 1) Ico: The flow of current in the circuit produces heat at the junctions. This heat increases the temperature at the junctions". We know that the minority carriers are temperature dependent. They increase with the temperature. The increase in the minority carriers increases the leakage current ICE0, Specifically, ICB0 doubles for every 10°C rise in temperature. Increase in ICE0 in turn increases the collector current The increase in IC further raises the temperature at the collector junction and the same cycle repeats. This excessive increase in IC shifts the operating point into the saturation region, changing the operating condition set by biasing circuit. As the power dissipated within a transistor is predominantly the Power dissipated at its collector base junction, the power dissipation is given as The increase in the collector current increases the power dissipated at the collector junction. This, in turn further increases the temperature of the junction and hence increases SCE

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the collector current. The process is cumulative. The excess heat produced at the collector base junction may even burn and destroy the transistor. This situation is called 'Thermal runaway’ of the transistor. For any transistor, maximum Power dissipation is always a fixed value. That is known as maximum power dissipation rating of a transistor. This value is specified by the manufacturer in data sheet. If this limit is crossed, the device will fail. 2) VBE : Base to emitter voltage VBE changes with temperature at the rate of 2.5mV/°C Base current, IB depends upon VBE .As base current IB depends on VBE, and Ic depends on IB, Ic depends on VBE. Therefore collector current Ic. Change with temperature due to change in VBE. The change in collector current change the operating point. 3)βdc: βdc of the transistor is also temperature dependent. As βdc varies, Ic also varies, since Ic = βIB. The change in collector current change the operating point. Therefore, to avoid thermal instability, the biasing circuit should be designed to provide a degree of temperature stability i.e. even though there are temperature changes, the changes in the transistor parameters (VCE , ICQ , PDmax )should be very less so that the operating point shifting is minimum in the middle of the active region. II) Transistor current gain hFE/β Eventhough there is tremendous advancement in semiconductor technology, there are changes in the transistor parameters among different units of the same type, same number. This means if we take two transistor units of same fire (i.e. same number, construction, parameter specified etc.) and use them in the circuit, there is change in the β value in actual practice. The biasing circuit is designed according to the required β value. But due to change in β from unit to unit, the operating point may shift Figure shows the common emitter output characteristics for two transistors of the same type. The dashed characteristics are for a transistor whose p is much larger than that of the transistor represented by the solid curves. So for stabilizing the operating point the factors discussed so far should be considered while designing the biasing circuit.

Figure: Common emitter output characteristics 1.4 BIASING METHODS The common biasing circuits used in the bipolar transistor amplifiers are 1. Fixed bias 2. Collector-to-base bias 3. Fixed bias with emitter resistor

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1.5 Fixed Bias (Base Resistor Bias)

The Figure shows the fixed bias circuit. It is the simplest d.c. bias configuration. For the d.c. analysis we can replace capacitor with an open circuit because the reactance of a capacitor for d.c. is In the base circuit, Apply KVL, we get Therefore,

VCC = IBRB + VBE

IB = (VCC - VBE)/RB For a given transistor, VBE does not vary significantly during use. As VCC is of fixed value, on selection of RB, the base current IB is fixed. Therefore this type is called fixed bias type of circuit. In the Collector circuit Apply KVL, we get VCC = ICRC + VCE Therefore, VCE = VCC - ICRC The common-emitter current gain of a transistor is an important parameter in circuit design, and is specified on the data sheet for a particular transistor. It is denoted as β. IC = βIB

In this circuit VE =0

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Stability factor S for Fixed bias circuit

Merits: • It is simple to shift the operating point anywhere in the active region by merely changing the base resistor (RB). • A very small number of components are required. Demerits: • The collector current does not remain constant with variation in temperature or power supply voltage. Therefore the operating point is unstable. • Changes in Vbe will change IB and thus cause RE to change. This in turn will alter the gain of the stage. • When the transistor is replaced with another one, considerable change in the value of β can be expected. Due to this change the operating point will shift. • For small-signal transistors (e.g., not power transistors) with relatively high values of β (i.e., between 100 and 200), this configuration will be prone to thermal runaway. In particular, the stability factor, which is a measure of the change in collector current with changes in reverse saturation current, is approximately β+1. To ensure absolute stability of the amplifier, a stability factor of less than 25 is preferred, and so smallsignal transistors have large stability factors. Usage: Due to the above inherent drawbacks, fixed bias is rarely used in linear circuits (i.e., those circuits which use the transistor as a current source). Instead, it is often used in circuits where transistor is used as a switch. However, one application of fixed bias is to achieve crude automatic gain control in the transistor by feeding the base resistor from a DC signal derived from the AC output of a later stage. Problems 1. Design the fixed bias circuit from the load line given in the figure.

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2. For the circuit shown in figure. Calculate IB,IC,VCE,VB,VC and VBC. Assume VBE= 0.7V and β=50.

3. Design a fixed biased circuit using a silicon transistor having β value of 100. Vcc is 10 V SCE

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and dc bias conditions are to be VCE = 5 V and IC = 5 mA,

Solution Applying KVL to collector circuit,

Applying KVL to base circuit,

4. Calculate the operating point (Q-point)

Base biased CE connection

IC = βdc * IB = 100 * 29µA = 2.9 mA VCE = VCC - (IC * RC) = 15V - (2.9 mA * 3KΩ) = 6.3V By plotting IC (2.9 mA) and VCE (6.3V), we get the operation point ----> Q-point (quiescent point).

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Collector curve with load line and Q – point 5. Draw the load line and Q-point.

base biased CE connection, β=50 Solution:

IC = IB * β = 2.15 mA VCE = VCC - (RC * IC)= 5.7V

VCE (cut) = VCC = 3.0V

1.6 Requirements of a biasing circuit 1. Emitter base junction must be forward biased and collector base junction must be reverse biased. That means the transistor should be operated in the middle of the active region or Q point should be fixed at the centre of the active region. 2. Circuit design should provide a degree of temperature stability. 3. Q point should be made independent of the transistor parameters such as β.

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To maintain the Q point stable by keeping IC and VCE constant so that the transistor will always work in active region, the following techniques are normally used, 1. Stabilization technique 2. Compensation technique 1.7 Method of stabilizing the Q point Stabilization technique: It refers to the use of resistive biasing circuits which allow IB to vary so as to keep IC relatively constant with variations in ICO, β and VBE. Compensation technique: It refers to the use of temperature sensitive devices such as diodes, transistors, thermistors which provide compensating voltage and current to maintain Q point stable. 1.8 Stability Factors It is defined as the degree of change in operating point due to variation in temperature. There are three variables which are temperature dependent. Three stability factors are defined as follows,

Stability factor S:

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The above equation can be considered as a standard equation for the derivation of stability factors of other biasing circuits. Stability factor S’:

Stability factor S”:

Relation between S and S”: We know that S = 1+β and S” = IC/β Multiplying numerator and denominator by (1+β), S” = IC(1+β) ______ β(1+β) S” = IC S ______ β(1+β)

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1.9 Collector to Base Bias

Figure shows the dc bias with voltage feedback. It is also called as collector to base bias circuit. It is an improvement over fixed bias method. In this, biasing resistor is connected between collector and base of the transistor to provide feedback path. Circuit analysis: Base circuit: Consider the base circuit and applying voltage law then we get,

Only the difference between the equation for IB and that obtained for fixed bias configuration is βRC, so the feedback path results in a reflection of the resistance RC to the input circuit. Collector circuit: Applying KVL to the collector circuit, VCC – (IC + IB) RC – VCE = 0 VCE = VCC – (IC + IB) RC If there is a change in β due to piece to piece variation between transistors or if there is a change in β and ICO due to the change in temperature. So collector current tends to increase. As a result, voltage drop across RC increases. Due to reduction in VCE, IB reduces. The result is that the circuit tends to maintain a stable value of collector current, keeping the Q point fixed. In this circuit, RB appears directly across input and output. A part of output is feedback to the input. And increase in collector current decreases the base current. So negative feedback exists in the circuit. It is also called as voltage feedback bias circuit.

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1.10 Modified collector to base bias circuit:

To improve the level of stability, emitter resistance is connected in this circuit. Base circuit: Applying KVL to base circuit, VCC – (IC + IB) RC – IBRB – VBE – IERE = 0 VCC – VBE IB = __________________ RB + (1+β) (RC + RE) IB =

VCC – VBE __________________ RB + β (RC + RE) Only difference between the equation for IB and that obtained for the fixed bias configuration is the term β (RC + RE).So feedback path results in a reflection of the resistance RC back to the input circuit. In general, V’ IB = ________ RB + β R’ Where V’ = VCC - VBE R’ = 0 for fixed bias R’ = RE for emitter bias R’ = RC for collector to base bias R’ = RC + RE for collector to base bias with RE Collector circuit: Applying KVL to collector circuit, VCC – (IC+IB) RC – VCE – IERE = 0 VCE = VCC – IE (RC+RE) Stability factor S for collector to base bias circuit: VCC = IC RC – IB(RB+RC) + VBE When ICBO, IB and IC changes with no effect on VCC and VBE, the equation becomes,

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S=

1+β ______________ 1+β (RC/ (RC+RB)) Collector to base bias circuit is having lesser stability factor than for fixed bias circuit. So this circuit provides better stability than fixed bias circuit. Problem 1: Locate the operating point of the given circuit with VCC = 15V, hfe = 200.

Solution: IBQ = VCC - VBE ___________ RB+ (1+β) (RC+RE) = 15-0.7 ________________________ 630*103 + (1+200) (4.7*103+680) ICQ = β IBQ = 200*8.356*10-6 = 1.6712mA IEQ = ICQ + IBQ = 1.6712*10-3 + 8.356*10-6 = 1.68mA VCEQ = VCC – IE (RC+RE) = 15-1.68*10-3 (4.7*103 + 680) = 5.96V

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1.11 Voltage divider bias circuit:

Figure shows the voltage divider bias circuit. In this, biasing is provided by three resistors R1, R2 and RE. The resistors R1 & R2 act as a potential divider giving a fixed voltage to base. If collector current increases due to change in temperature or change in β, emitter current IE also increases and voltage drop across RE increases thus reducing the voltage difference between base and emitter. Due to reduction in base emitter voltage, base current and collector current reduces. So we can say that negative feedback exists in emitter bias circuit. This reduction in collector current compensates for the original change in IC. Circuit analysis: Base circuit:

Fig. Base circuit Let us consider the base circuit as shown in above figure. Voltage across R2 is base voltage VB. Applying voltage divider rule to find VB,

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VB =

R2 (I) ______________ * VCC R1 (I+IB) +R2 (I) = R2 with I>>IB _______________ * VCC R1+R2 Collector circuit:

Fig. Divider biased Let us consider the collector circuit as shown in above figure. Voltage across RE can be obtained as, VE = IERE = VB - VBE IE = VB-VBE ______ RE Apply KVL to collector circuit, VCE = VCC – ICRC - IERE Simplified circuit of voltage divider bias:

Fig. Thevenin’s equivalent circuit for voltage divider bias From above figure, R1 and R2 are replaced by RB and VT. Where RB is the parallel combination of R=1 and R2 VT is the thevenin’s voltage

Apply KVL,

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Problem 1: For the given circuit β=100 for silicon transistor. Calculate VCE and IC.

Solution:

Problem 2: For the given figure find Q point with VCC = 15V, VBE = 0.7V and β = 100.

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Solution:

Stability factor for voltage divider bias: Stability factor S:

Fig. Thevenin’s equivalent circuit for voltage divider bias For determining stability factor S for voltage divider bias, consider the equivalent circuit. Thevenin’s voltage is given by,

R1, R2 are replaced by RB which is the parallel combination of R1 and R2.

Apply KVL to base circuit, Differentiating with respect to IC and considering VBE to be independent of IC,

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Stability factor S is given by,

From above equation, the following points are observed. 1. The ratio RB/RE controls value of stability factor S. If RB/RE << 1 then it is reduced to S = (1+β). 1/ (1+β) = 1 Practically RB/RE not equal to zero. But to have better stability factor S , we have to keep ratio RB/RE as small as possible. 2. To keep RB/RE small, it is necessary to keep RB small. Due to small value of R1 and R2, potential divider circuit will draw more current from VCC reducing the life of the battery. Another important aspect is that reducing RB will reduce input impedance of the circuit, since RB comes in parallel with the input. This reduction of input impedance in amplifier circuit is not desirable and hence RB cannot be made very small. 3. Emitter resistance RE is another parameter, it is used to decrease the ratio RB/RE. Drop across RC will reduce. This shifts the operating point Q which is not desirable and hence there is limit for increasing RE. While designing voltage divider bias circuit, the following conditions are to be satisfied, S – Small RB - Reasonably small RE - Not very large 4. If ratio RB/RE is fixed, S increases with β. So stability decreases with increasing β. 5. Stability factor S is essentially independent of β for small value of S. Substituting the differentiation value of IB/IC,

Dividing each term by RE,

Problem 1: For the given circuit, VCC = 20V, RC = 2KΩ, β = 50, VBE = 0.2V, R1 = 100KΩ, RE = 100Ω. Calculate IB, VCE, IC and stability factor S.

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Solution: R2 is not given. So assume R2 = 10KΩ

RB = R1*R2 ______ = 9.09KΩ R1+R2 IB = VT-VBE _____________ = 114µA RB+ (1+β)RE IC = βIB = 5.7Ma VCE = VCC – ICRC – (1+β)IBRE = 8V S = 1+β __________________ 1+β (RE / (RE+RB)) S = 33 1.12 Compensation technique: It refers to the use of temperature sensitive devices such as diodes, transistors, thermistors which provide compensating voltage and current to maintain Q point stable.

1.12.1 Diode Compensation Techniques Compensation for VBE: a) Diode in Emitter Circuit Diagram shows the voltage divider bias with bias compensation technique.Here, separate supply VDD is used to keep diode in forward If biased condition. If the diode used in the circuit is of same material and type as the transistor, the voltage across the diode will have the same temperature coefficient as the base to emitter voltage VBE . So when VBE changes by with change in temperature, VD changes by

VBE

VD and

, the changes tend to cancel each other. Apply*g KVL to the base circuit of Fig. ,we have SCE

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Figure: Stabilization by means of voltage divider bias and diode Compensation Technique

As VD tracks VBE with respect to temperature it is clear that IC will be insensitive to variations in VBE.

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Diode in voltage divider circuit

•

• •

Diode is connected in series with resistance R2 in the voltage divider circuit and it is forward biased condition. For voltage divider bias,

When VBE changes with temperature, IC also changes To cancel the changes in IC , one diode is used in the circuit for compensation The voltage at the base VB is give as Substituting this value in equation IC, we get,

The changes cancel each other , so the collector current is given as

The changes in VBE. Due to temperature are compensated by changes in the diode voltage which keeps IC stable at Q point. Compensation for ICO * In germanium transistor changes in ICO with temperature plays an important role collector current stability * The diode is kept at reverse bias condition ,so only leakage current flows * Io increases then ICO also increases

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As I is constant , IC also remains constant. We can say that changes by ICO with temperature are compensated by diode and collector current remains constant 1.12.2 Thermistor Compensation

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With increase of temperature ,RT decreases. Hence the voltage drop across it also decreases. That is VBE decreases which reduces IB . this will offset the increased collector current with temperature. The equation shows if there is increase in ICO and decrease in IB almost constant.

keeps IC

Fig (b) shows another thermistor compensation technique . Here, thermistor is connected between emitter and Vcc to minimize the increase in collector current due to changes in ICO, VBE, or beta with temperature .IC increases with temperature and RT decreases with increase in temperature. Therefore, current flowing through RE increases, which increases the voltage drop across it. E - B junction is forward biased. But due to increase in voltage drop across RE, emitter is made more positive, which reduces the forward bias voltage VBE. Hence, bias current reduces.

As Ico increases with temperature, IB decreases and hence. IC remains constant Sensistor Compensation technique

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This method of transistor compensation uses temperature sensitive resistive element, sensistors rather than diodes or transistors. It has a positive temperature coefficient, its resistance increases exponentially with increasing temperature as shown in the Fig Slope of this curve = is the temperature coefficient for thermistor and the slope is positive So we can say that sensistor has positive temperature coefficient of resistance (PTC). Fig. shows sensistor compensation R1 is replaced by sensistor RT in self bias circuit. Now, RT and R2 resistors of the potential divider. As temperature increases, RT increases which decreases the current flowing through it. Hence current through R2 decreases which reduces the voltages drop across it. Voltage drop across R2 is the voltage between base and ground. So VBE reduces which decreases 16. It means, when ICBO increases with increase in temperature, IB reduces due to reduction in VBE, maintaining IC fairly constant. 1.13 FET Biasing

•

The Parameters of FET is temperature dependent .When temperature increases drain resistance also increases, thus reducing the drain current.

• •

Unlike BJTs, thermal runaway does not occur with FETs

•

However, the wide differences in maximum and minimum transfer characteristics make ID levels unpredictable with simple fixed-gate bias voltage.

Different biasing circuits of FET are 1) Fixed bias circuits 2) Self bias circuits 3) Voltage bias circuits Fixed bias circuits DC bias of a FET device needs setting of gate-source voltage VGS to give desired drain current ID . For a JFET drain current is limited by the saturation current IDS. Since the FET has such a high input impedance that no gate current flows and the dc voltage of the gate set by a voltage divider or a fixed battery voltage is not affected or loaded by the FET.

Fixed dc bias is obtained using a battery VQG. This battery ensures that the gate is always negative with respect to source and no current flows through resistor

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RG and gate terminal that is IG =0. The battery provides a voltage VGS to bias the N-channel JFET, but no resulting current is drawn from the battery VGG. Resistor RG is included to allow any ac signal applied through capacitor C to develop across RG. While any ac signal will develop across RG, the dc voltage drop across RG is equal to IG RG i.e. 0 volt. Calculate VGS For DC analysis IG =0., applying KVL to the input circuits VGS+ VGG=0 VGS= - VGG As VGS is a fixed dc supply, hence the name fixed bias circuit Calculate IDQ IDQ= IDss(1- VGS/VGp)2 Calculate VDS This current IDQ then causes a voltage drop across the drain resistor RD and is given as VDSQ = VDD – ID RD Disadvantage The fixed bias circuit of FET requires two power supplies. Self-Bias circuits Self-Bias circuits is the most common method for biasing a JFET. Self-bias circuit for N-channel JFET is shown in figure

• •

The gate source junction of JFET must be always in reverse biased condition .No gate current flows through the reverse-biased gate-source, the gate current IG = 0 and, therefore,vG = iG RG = 0

With a drain current ID the voltage at the S is Vs= ID Rs 1)The gate-source voltage is then VGS = VG - Vs = 0 – ID RS = – ID RS So voltage drop across resistance Rs provides the biasing voltage VGg and no external source is required for biasing and this is the reason that it is called self-biasing. 2)Calculate IDQ SCE

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ID= IDSS(1- VGS/ VP)2 Substituting the value of VGS ID= IDSS (1+ID RS / VP)2 3)The operating point (that is zero signal ID and VDS) can easily be determined from equation given below : VDS = VDD – ID (RD + RS) Self biasing of a JFET stabilizes its quiescent operating point against any change in its parameters like transconductance. Any increase in voltage drop across RS, therefore, gate-source voltage, VGS becomes more negative and thus increase in drain current is reduced. Voltage -Divider Bias circuits

The resistors RGl and RG2 form a potential divider across drain supply VDD. The voltage V2 across RG2 provides the necessary bias. The additional gate resistor RGl from gate to supply voltage facilitates in larger adjustment of the dc bias point and permits use of larger valued RS. The coupling capacitors are assumed to be open circuit for DC analysis 1) The gate is reverse biased so that IG = 0 and gate voltage VG =V2 = (VDD/R G1 + R G2 ) *RG2 2) Applying KVL to the input circuit we get VGS = VG – VS = VG - ID RS 3) IDQ= IDSS(1- VGS/ VP)2 4) VDS = VDD – ID (RD + RS) The operating point of a JFET amplifier using the Voltage -Divider Bias is determined by IDQ= IDSS(1- VGS/ VP)2 VDSQ = VDD – ID (RD + RS) VGSQ = VG – ID RS Example Problems 1)Determine IDQ, VGSQ, VD, VS, VDS, and VDG

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Solution

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Example for Practice:

*Example 4

Example Problem

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1.14 Biasing of MOSFET *N-channel enhancement mode MOSFET circuit shows the source terminal at ground potential and is common to both the input and output sides of the circuit. *The coupling capacitor acts as an open circuit to d.c. but it allows the signal voltage to be coupled to the gate of the MOSFET.

As Ig = 0 in VG is given as,

Assume VG > VT , MOSFET is biased in the saturation region, the drain current is,

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If VDS > VDS(sat) Biased in the nonsaturation region, and the drain current is given by, ID Example problem-1

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Load Line and Modes of Operation The load line gives a graphical picture showing the region in whichthe MOSFET is biased. Consider the common-source circuit shown in Fig. (a). Writing Kirchhoff's voltage law around the drain-source loop results VDs = VDD -IDRD, which is the load line equation. It shows a linear relationship between the drain current and drain-to-source voltage. Fig. (b) shows the VDS(sat) characteristic for the MOSFET

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The load line is given by

The two end points of the load line are determine in the usual manner. If the drain current = 0, then VDS= 10 v; if VDS = 0, then drain current = 10/40 = 0.25 mA. The Qpoint of the MOSFET is given by the d.c. drain current (ID) and drain-to-source voltage (VDS) and it is always on the load line, as shown in the Fig. b). If the gate-to-source voltage is less than V1, the drain current is zero and the MOSFET is in cut-off. As the gate-to-source voltage becomes just greater than the threshold voltage, the MOSFET turns ON and is biased in the saturation region. As V GS increases, the Q-point moves up the load line. The transition point is the boundary between the saturation and non-saturation regions. It is the point where,

Common Source circuit for EMOSFET with source resistor

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Voltage Divider Bias As

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Because ID = IS Biasing Circuit for D MOSFET Biasing circuits for depletion type MOSFET are quite similar to the circuits used for JFET biasing. The primary difference between the two is the fact that depletion type MOSFETs also permit operating points with positive value of V6s for n-channel and negative values of V6s for p-channel MOSFET. To have positive value of V GS for n-channel and negative value of V6s for p-channel self bias circuit is unsuitable. Example problem-1

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Example – 2

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Example-3

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Example-4

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QUESTIONS 2 MARK 1. What is DC load line? Draw the DC load line of the circuit shown in fig.

2. Find the collector and base current of circuit diagram given in fig, having hfe = 100, VBE(on) = 0.7V

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3. Why do we choose Q point at the center of the load line? 4. What is operating point? 5. Distinguish between dc and ac load line with suitable diagram. 6. Name the two techniques used in the stability of the q point .explain. 7. Define the stability factor. 8. Define three stability factors. 9. List out the different types of biasing. 10. What is the need for the biasing the transistor amplifier? 11. What is the requirements for biasing circuits? 12. Define the term biasing. 13. Draw the fixed bias single stage transistor circuit. 14. Derive the stability factor S for a fixed bias circuit. 15. What are the advantages of fixed bias circuit? 16. Draw a single stage self biased circuit using pnp transistor. 17. What are the factors against which an amplifier needs to be stabilized? 18. What is thermal runway? How it can be avoided. 19. Why the transistor is called a current controlled device? 20. Define current amplification factor? 21. What is the necessary of the coupling capacitor? 22. Draw the any two biasing circuit for a JFET. 23. Draw any one biasing circuit for depletion type MOSFET. 24. Draw the any two biasing circuit for an enhancement type MOSFET. 25. Explain how an FET is used as a voltage variable resistor. 16 MARK 1. Explain the voltage divider bias method & derive an expression for stability factors. 2. Why biasing is necessary in BJT amplifier? Explain the concept of DC & AC load line with neat diagram. 3. How will you select the operating point, explain it using CE amplifier characteristics? 4. Explain the collector feedback bias amplifier & derive an expression for stability factors. 5. Explain the fixed bias method & derive an expression for stability factors. 6. Derive an expression for all stability factors & CE configuration S equation. 7. Explain about common source self- bias & voltage divider bias for FET. 8. Explain in details about biasing MOSFET. 9. Discuss the various types of bias compensation. 10. Explain constant current biasing used in JFET amplifier. (May,06) 11. Draw and explain voltage divider bias using FET and derive for its stability factors. Also mention its advantages. (May,11) 12. How is a JFET used as a voltage variable resistance? Explain. (Nov,07) (May,07) 13. Explain the bias circuit for enhancement MOSFET and explain its operation. (Nov,14; Nov,13) 14. With circuit diagram explain biasing of FET and MOSFET. (Nov,07) 15. Discuss the various techniques of stabilization of Q- point in a transistor. (Nov,09; May,13)

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16. The fixed bias circuit as shown in figure is subjected to an increase in junction temperature from 25oC to 75oC. If β is 125 at 75oC, determine the percentage change in Q point values (VCE, IC) over temperature change. Neglect any change in VBE. 17. A self bias circuit has RE=1 kΩ, R1=130 kΩ, R2=10 kΩ. If VCC and RC are adjusted to give IC=1mA at 10oC. Calculate the variation in Ic over temperature change of 10oC to 100oC. The transistor used has the parameters given below,

18. Design a collector to base bias circuit to have operating point (10v, 4mA). The circuit is supplied with 20v and uses a silicon transistor of hfe is 250. 19. Design a voltage divider bias circuit for the specified conditions. VCC=12v, VCE=6v, IC=1mA, S=20, β=100 and VE=1v. 20. The parameters for each transistor in the circuit in figure, are hfe = 100, and VBE(on) = 0.7V. Determine the Q-point values of base collector and emitter currents in Q1 and Q2 (8)[AU, MAY,2015]

21. Determine the change in collector current produced in each bias referred to in fig 1 and 2, when the circuit temperature raised from 25oC to 105oC and ICBO = 15nA @ 25oC (8)[AU, MAY,2015]

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22. Determine the quiescent current and voltage values in a P-Channel JFET circuit shown in fig. (8)[AU, MAY,2015]

23. The circuit shown in Fig, let hfe = 100, (1). Find VTH and RTH for the base circuit. (2). (8)[AU, MAY,2015] Determine ICEQ and VCEQ. (3). Draw the DC load line.

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Electronic Circuits I UNIT II BJT AMPLIFIERS

2.1 Introduction An amplifier is used to increase the signal level. It is used to get a larger signal output from a small signal input. Assume a sinusoidal signal at the input of the amplifier. At the output, signal must remain sinusoidal in waveform with frequency same as that of input. To make the transistor work as an amplifier, it is to be biased to operate in active region. It means base-emitter junction is forward biased and base-collector junction is reverse biased. Let us consider the common emitter amplifier circuit using voltage divider bias.

In the absence of input signal, only D.C. voltage is present in the circuit. It is known as zero signal or no signal condition or quiescent condition. D.C. collector-emitter voltage VCE, D.C. collector current IC and base current IB is the quiescent operating point for the amplifier. Due to this base current varies sinusoidaly as shown in the below figure. Fig. IBQ is quiescent DC base current If the transistor is biased to operate in active region, output is linearly proportional to the input. The collector current is β times larger than the input base current in CE configuration. The collector current will also vary sinusoidally about its quiescent value ICQ. The output voltage will also vary sinusoidally as shown in the below figure.

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Variations in the collector current and voltage between collector and emitter due to change in base current are shown graphically with the help of load line in the above figure. 2.2 Common Emitter Amplifier Circuit

Fig. Practical common-emitter amplifier circuit From above circuit, it consists of different circuit components. The functions of these components are as follows: 1. Biasing Circuit: Resistors R1, R2 and RE forms the voltage divider biasing circuit for CE amplifier and it sets the proper operating point for CE amplifier. 2. Input Capacitor C1: C1 couples the signal to base of the transistor. It blocks any D.C. component present in the signal and passes only A.C. signal for amplification. 3. Emitter Bypass Capacitor CE: CE is connected in parallel with emitter resistance RE to provide a low reactance path to the amplified A.C. This will reduce the output voltage and reducing the gain value. 4. Output Coupling Capacitor C2: C2 couples the output of the amplifier to the load or to the next stage of the amplifier. It blocks D.C. and passes only A.C. part of the amplified signal. Need for C1, C2, and CE: The impedance of the capacitor is given by, XC = 1/ (2∏fc) Phase reversal: The phase relationship between the input and output voltages can be determined by considering the effect of positive and negative half cycle separately. The collector current is β times the base current, so the collector current will also increases. This increases the voltage drop across RC. VC = VCC - ICRC

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Increase in IC results in a drop in collector voltage VC, as VCC is constant. Vi increases in a positive direction, Vo goes in negative direction and negative half cycle of output voltage can be obtained for positive half cycle at the input. In negative half cycle of input, A.C. and D.C. voltage will oppose each other. This will reduce the base current. Accordingly collector current and drop across RC both will reduce and it increases the output voltage. So positive half cycle at the output for negative half cycle at the input can be obtained. So there is a phase shift of 180º between input and output voltages for a common emitter amplifier. 2.3 Common Collector Amplifier Circuit:

From above circuit, D.C. biasing is provided by R1, R2 and RE. The load resistance is capacitor coupled to the emitter terminal of the transistor. When a signal is applied to base of the transistor, VB is increased and decreased as the signal goes positive and negative respectively. From figure, VE = VB - VBE Consider VBE is constant, so the variation in VB appears at emitter and emitter voltage VE will vary same as base voltage VB. In common collector circuit, emitter terminal follows the signal voltage applied to the base. It is also known as emitter follower. 2.4 Common Base Amplifier Circuit:

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From above circuit, the signal source is coupled to the emitter of the transistor through C1. The load resistance RL is coupled to the collector of the transistor through C2. The positive going pulse of input source increases the emitter voltage. As base voltage is constant, forward bias of emitter-base junction reduces. This reduces Ib, Ic and drop across Rc. Vo = VCC - ICRC Reduction in IC results in an increase in Vo. Positive going input produces positive going output and vice versa. So there is no phase shift between input and output in common base amplifier. 2.5 Small Signal Low Frequency h-parameter Model: Let us consider the transistor amplifier as a block box.

Where, Ii – input current to the amplifier Vi - input voltage to the amplifier Io – output current of the amplifier Vo – output voltage of the amplifier Input current is an independent variable. Input voltage and output current are dependent variables. Input current and output voltage are independent variables.

This can be written in the equation form as,

The above equation can also be written using alphabetic notations,

Definitions of h-parameter: The parameters in the above equations are defined as follows:

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h11 – input resistance with output short-circuited in ohms h12 – fraction of output voltage at input with input open circuited, it is unitless h21 – forward current transfer ratio or current gain with output short circuited, it is unitless h22 – output admittance with input open circuited in mhos Benefits of h-parameters: 1. Real numbers at audio frequencies 2. Easy to measure 3. Can be obtained from the transistor static characteristic curve 4. Convenient to use in circuit analysis and design 5. Most of the transistor manufacturers specify the h-parameters

2.6 h-Parameters for all three configurations: Transistor can be represented as two port network by making anyone terminal common between input and output. There are three possible configurations in which a transistor can be used, there is a change in terminal voltage and current for different transistor configurations. To designate the type of configuration another subscript is added to h-parameters. hie = h11e– input resistance in CE configuration hfb = h21b – short circuit current gain in CB configuration Table: Summarizes h-parameters for all three configurations

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The basic circuit of hybrid model is same for all three configurations, only parameters are different.

The circuit and equations are valid for either NPN or PNP transistor and are independent of the type of load or method of biasing. Determination of h-parameters from characteristics: Consider CE configuration, its functional relationship can be defined from the following equations:

The input characteristic curve gives the relationship between input voltage VBE and input current IB for different values of output voltage VCE. The following figure shows the typical input characteristic curve for CE configuration. SCE

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Determination of hie and hre from characteristic curve: Parameter hie:

Parameter hre:

The output characteristic curve gives the relationship between output current IC and output voltage VCE for different values of input current IB.

Determination of hfe and hoe from output characteristic curve: Parameter hfe:

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Parameter hoe:

hoe =

2.7 Midband analysis of BJT Single Stage Amplifiers: Consider the basic amplifier circuit. To form a transistor amplifier only is is necessary to connect an external load and signal source along with proper biasing.

We can replace the transistor circuit as shown in the following figure.

Let us analyze the hybrid model to find current gain, input resistance, voltage gain and output resistance. Current gain (Ai): It is defined as the ratio of output to input current. It is given by,

Here IL and I2 are equal in magnitude but opposite in sign. IL = -I2 From above circuit,

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Substituting V2 = -I2RL in the equation, then equation become,

Current gain (AIS): It is given by,

From above figure, using current divider rule,

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Input Impedance (Zi): Ri is the input resistance looking into the amplifier input terminals ( 1, 1’). It is given by,

From the input circuit,

Substituting V2 = -I2RL = Ai I1 RL in the above equation,

Substituting

Then we get,

Dividing numerator and denominator by RL we get,

From this equation, note that the input impedance is a function offload impedance. Voltage gain (Av): It is the ratio of output voltage to input voltage. It is given by,

By substituting V2 = -I2RL = Ai I1 RL

Since

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Voltage gain (Avs): It is voltage gain including the source. It is given by,

From above figure, applying potential divider rule, then we get,

Substituting the value of V1/Vs in the equation of

We get,

Output Admittance (Yo): It is the ratio of output current to output voltage. It is given by,

From equation, Dividing above equation by V2, We get, SCE

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From transistor amplifier in h-parameter model circuit, with Vs = 0, RsI1 + hiI1 +hrV2 = 0 (Rs + hi) I1 = -hr V2

Substituting the value of I1/V2 from above equation in the equation of Yo. We obtain,

From this equation, note that the output admittance is a function of source resistance. Power gain (Ap): It is the ratio of average power delivered to the load to the input power. Output power is given as, Since the input power is P1 = V1I1 The operating power gain Ap of the transistor is given as,

Relation between Avs and AIS: From equation,

Avs =

and

We have,

& Taking ratio of above two equations we get,

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Table: Summarizes small signal analysis of a transistor amplifier

Method for analysis of a transistor circuit: The analysis of transistor circuits for small signal behaviour can be made by following simple guidelines. These guidelines are, 1. 2. 3. 4.

Draw the actual circuit diagram Replace coupling capacitors and emitter bypass capacitor by short circuit Replace D.C. source by a short circuit Mark the points B, E, C on the circuit diagram and locate these points as the start of the equivalent circuit 5. Replace the transistor by its h-parameter model Problem 1: For the common base circuit shown in figure, transistor parameters are hib = 22Ω, hfb = -0.98, hob = 0.49µA/V, hrb = 2.9*10-4. Calculate the values of input resistance, output resistance, current gain and voltage gain for the given circuit.

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Solution: Change the given figure into h-parameter equivalent model.

a) Current gain

b) Input Resistance

c) Voltage gain

d) Overall voltage gain

e) Overall current gain SCE

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f) Output Resistance

Ro’ = Ro || RL’ = 1.21M || 5.45K = 5.425KΩ Problem 2: Consider a single stage CE amplifier with Rs = 1KΩ, RL = 1.2KΩ. Calculate Ai, Ri, Av, Ais, power gain and Ro if hie = 1.1k, hre = 2.5*10-4, hfe = 50 and hoe = 25µA/V. Solution:

Ai =

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Ri =

Av = Avs =

Ais =

Yo =

Ro = Problem 3: Consider a single stage CE amplifier with Rs = 1k, R1 = 50k, R2 = 2k, Rc = 2k, RL = 2K, hie = 1.1k, hoe = 25µA/V, hfe = 50 and hre = 2.5*10-4 as shown in the figure. Find Ai, Ri, Av, Ai, Avs and Ro.

Solution: Since hoe RL’ = 25*10-6*(2K || 2K) = 0.25, which is less than 0.1, so use approximate analysis. Consider the simplified hybrid model for the given circuit.

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a) Current gain

b) Input Impedance

c) Voltage gain

d) Output Impedance

e) Overall voltage gain

f) Overall current gain

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From above figure,

Comparison of Transistor Configurations:

2.8 Introduction of Differential Amplifier A device which accepts an input signal and produces an output signal proportional to the input, is called an amplifier. An amplifier which amplifies the difference between. the two input signals is called differential amplifier. The differential amplifier configuration is used in variety of analog circuits. The. differential amplifier is an essential and basic building block in modern IC amplifier .The Integrated Circuit (IC)

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technology is well known now a days, due to which the design of complex circuits become very simple. The IC version of operational amplifier is inexpensive, takes up less space and consumes less power. The. differential amplifier is the basic building block of such IC operational amplifier. Basics of Differential Amplifier The Differential Amplifier amplifies the difference between two input voltage signal. Hence it is also called as difference amplifier. Consider an ideal differential amplifier shown in the Fig. A

V1 and V2 are the two input signals while Vo is the output. Each signal is measured with respect to the ground. In an ideal differential amplifier, the output voltage Vo is proportional to the difference between the two input signals. Hence we can write,

From Equation 1 we can write,

where AD is the constant of proportionality. The AD is the gain with which differential amplifier amplifies the difference between two input signals. Thus it is called differential gain of the differential amplifier. Thus, Ad = Differential gain The difference between the two inputs (V1 - V2) is generally called difference voltage and denoted as Vd. ...(3) Hence the differential gain can be expressed as, ...(4) Generally the differential gain is expressed in its decibel (dB) value as, ...(5)

Common Mode Gain Ac If we apply two input voltages which are equal in all the respects to the differential amplifier i.e. V1 = Vz then ideally the output voltage Vo = (V1 - V2) Ad, must be zero.But the output voltage of the practical differential amplifier not only SCE

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depends on thedifference voltage but also depends on the average common level of the two inputs. Such an average level of the two input signals is called common mode signal denoted as VC ...(6) Practically, the differential amplifier produces the output voltage proportional to such common mode signal, also. The gain with which it amplifies the common mode signal to produce the output is called common mode gain of the differential amplifier AC.\ ..(7) Thus there exists some finite output for V1 = V2 due to such common mode gain AC, in case of practical differential amplifiers. So the total output of any differential amplifier can be expressed as, ..(8) For an ideal differential amplifier, the differential gain Ad, must be infinite while the common mode gain must be zero. But due to mismatch in the internal circuitry, there is some output available for V1 = V2 and gain AC is not practically zero. The value of such common mode gain AC very small while the value of the differential gain Ad is always very large. Common Mode Rejection Ratio (CMRR) When the same voltage is applied to both the inputs, the differential amplifier is said to be operated in a common mode configuration. Many disturbance signals, noise signal appear as a common input signal to both the input terminals of the differential amplifier. Such a common signal should be rejected by the differential amplifier. The ability of a differential amplifier to reject a common mode signal is expressed by a ratio called common mode rejection ratio denoted as CMRR. It is defined as the ratio of the differential voltage gain Ad to common mode voltage gain AC ….(9) …..(10)

2.9 Transistorised Differential Amplifier The transistorised differential amplifier basically uses the emitter biased circuits which are identical in characteristics. Such two identical emitter biased circuits are

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The two transistors Q1 and Q2 have exactly matched characteristics. The two collector Resistors R C1 and R C2 are equal while the two emitter resistances R E1 and R E2 are equal.

The magnitudes of + Vcc and – V EE are also same. The differential amplifier can be obtained by using such two emitter biased circuits. This is achieved by connecting emitter E1 of Q1 to the emitter E2 of Q2. Due to this, R E1 appears in parallel with R E2 and the combination can be replaced by a single resistance denoted as R E. The base B1 of Q1 is connected to the input 1 which is V S1 while the base B 2 of Q2 is connected to the input 2 which is Vs2. The supply voltages are measured with respect to ground. The balanced output is taken between the collector C1 of Q1 and the collector C2 of Q 2. Such an amplifier is called emitter coupled differential amplifier. The two collector resistances are same hence can be denoted as R C.. The output can be taken between two collectors or in between one of the two collectors and the ground. When the output is taken between the two collectors, none of them is grounded then it is called balanced output, double ended output or floating output. When the output is taken between any of the collectors and the ground, it is called unbalanced output or single ended output. The complete circuit diagram of such a basic dual input, balanced output differential amplifier is shown in the Fig.

As the output is taken between two output terminals, none of them is grounded, it is called balanced output differential amplifier.

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Let us study the circuit operation in the two modes namely • Differential mode operation • Common mode operation

2.9.1 Differential Mode Operation In the differential mode, the two input signals are different from each other. Consider the two input signals which are same in magnitude but 180" out of phase. These signals, with opposite phase can be obtained from the center tap transformer. The circuit used in differential mode operation is shown in the Fig..

Assume that the sine wave on the base of Q 1is positive going while on the base of Q 2 is negative going. With a positive going signal on the base of Q 1, m amplified negative going signal develops on the collector of Q1. Due to positive going signal, current through R E also increases and hence a positive going wave is developed across R E. Due to negative going signal on the base of Q2, an amplified positive going signal develops on the collector of Q 2. And a negative going signal develops across R E, because of emitter follower action of Q 2. So signal voltages across R E, due to the effect of Q1 and Q2 are equal in magnitude and 180o out of phase, due to matched pair of transistors. Hence these two signals cancel each other and there is no signal across the emitter resistance. Hence there is no a.c. signal current flowing through the emitter resistance. Hence R E in this case does not introduce negative feedback. While Vo is the output taken across collector of Q1 and collector of Q 2. The two outputs on collector L and 2 are equal in magnitude but opposite in polarity. And Vo is the difference between these two signals, e.g. +10 - (-10) = + 20. Hence the difference output Vo is twice as large as the signal voltage from either collector to ground

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2.9.2 Common Mode Operation In this mode, the signals applied to the base of Q1 and Q2 are derived from the same source. So the two signals are equal in magnitude as well as in phase. The circuit diagram is shown in the Fig. In phase signal voltages at the bases of Q1 and Q2 causes in phase signal voltages to appear across R E, which add together. Hence R E carries a signal current and provides a negative feedback. This feedback reduces the common mode gain of differential amplifier.

While the two signals causes in phase signal voltages of equal magnitude to appear across the two collectors of Q 1 and Q2. Now the output voltage is the difference between the two collector voltages, which are equal and also same in phase, Eg. (20) - (20) = 0. Thus the difference output Vo is almost zero, negligibly small. ideally it should be zero. 2.10 Configurations of Differential Amplifier The differential amplifier, in the difference amplifier stage in the op-amp, can be used in four configurations : • Dual input balanced output differential amplifier. • Dual input, unbalanced output differential amplifier. • Single input, balanced output differential amplifier. • Single input, unbalanced output differential amplifier. The differential amplifier uses two transistors in common emitter configuration. If output is taken between the two collectors it is called balanced output or double ended output. While if the output is taken between one collector with respect to ground it is called unbalanced output or single ended output. If the signal is given to both the input terminals it is called dual input, while if the signal is given to only one input terminal and other terminal is grounded it is called single input or single ended input. Out of these four configurations the dual input, balanced output is the basic differential amplifier configuration. This is shown in the Fig. (a). The dual input, unbalanced output differential amplifier is shown in the Fig.(b). The single input, balanced output

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differential amplifier is shown in the Fig (c) and the single input, unbalanced output differential amplifier is shown in the Fig. (d).

2.11 D.C. Analysis of Differential Amplifier The d.c. analysis means to obtain the operating point values i.e. I Cq and V CEQ for the transistors used. The supply voltages are d.c. while the input signals are a.c., so d.c equivalent circuit can be obtained simply by reducing the input a.c. signals to zero. The d.c. equivalent circuit thus obtained is shown in the Fig.. Assuming Rs 1 = R S2, the source resistance is simply denoted by Rs ,

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. The transistors Q1 and Q 2 are matched transistors and hence for such a matched pair we can assume : i) Both the transistors have the same characteristics. ii) R E1 = R E2 hence R E= R E1 ll R E2. iii) R C1 = R c 2 hence denoted as R C. iv) lV CCI = lV EE I and both are measured with respect to ground. As the two transistors are matched and circuit is symmetrical, it is enough to find out operating point I CQ and V CEQ, for any one of the two transistors. The same is applicable for the other transistor. Apply-g KVL to base-emitter loop of the transistor Q1, ….(1)

….(2)

….(3)

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2.12 A.C. Analysis of Differential Amplifier using h-Parameters In the a.c. analysis, we will calculate the differential gain A d, common mode gain A C, input resistance Ri and the output resistance R 0 of the differential amplifier circuit, using the h-parameters. 1. Differential Gain (A d) For the differential gain calculation, the two input signals must be different from each other. Let the two a.c. input signals be equal in magnitude but having 180" phase difference in between them. The magnitude of each a.c. input voltage V S1 and V S2 beVs /2. The two a.c. emitter currents I e1 and I e2 are equal in magnitude and 180' out of phase. Hence they cancel each other to get resultant a.c. current through the emitter as zero. For the a.c. purposes emitter terminal can be grounded. The a.c. small signal differential amplifier circuit with grounded emitter terminal is shown in the Fig1 As the two transistors are matched, the a.c. equivalent circuit for the other transistor is identical to the one shown in the Fig..1. Thus the circuit can be analyzed by considering only one transistor. This is called as half circuit concept of analysis. The approximate hybrid model for the above circuit can be shown as in the Fig.2, neglecting hoe,

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The negative sign indicates the phase difference between input and output. Now two input signal magnitudes are VS /2 but they are opposite in polarity, as 180" out of phase.

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the expression for A d with balanced output changes as

This is the differential gain for balanced output dual input differential amplifier circuit. 2. Common Mode Gain (A C) Let the magnitude of both the a.c. input signals be VS and are in phase with each other. Hence the differential input Vd = 0 while the common mode input Vc is the average value of the two.

But now both the emitter currents flows through R E in the Same direction. Hence the total current flowing through R E is 2I e. considering only one transistor, as in the Fig

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The emitter resistance is shown 2 RE in the Fig

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2.13 Common Mode rejection Ratio (CMRR) Once the differential and common mode gains are obtained, the expression for the CMRR can be obtained as,

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2.14 Techniques of Improving Input Impedance Among three configurations (CB, CC and CE), common collector or emitter follower circuit has high input impedance. Typically it is 200 KΩ to 300 KΩ. A single stage emitter follower circuit can give input impedance upto 500 KΩ. However, the input impedance considering biasing resistors is Figure shows the direct coupling of two stages of emitter follower significantly less. Because Ri’ = R1 ll R2 ll Ri The input impedance of the circuit can be improved by direct coupling of two stages of emitter follower amplifier. The input impedance can be increased using two techniques : • Using direct coupling (Darlington connection) • Using Bootstrap technique 2.14.1 Darlington Transistors Figure shows the direct coupling of two stages of emitter follower amplifier. This cascaded connection of two emitter followers is called the Darlington connection.

Assume that the load resistance RL is such that RL hoe < 0.1, therefore we can use approximate analysis method for analyzing second stage.

Figure shows approximate h-parameter (AC) equivalent circuit for common emitter configuration. The same circuit can be redrawn by making collector common to have approximate h-parameter equivalent circuit for common collector configuration. SCE

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Analysis of second stage :

Analysis of first stage : Load resistance of the first stage is the input resistance of the second stage i.e. Ri2. As Ri2 is high, usually it does not meet the requirement hoe Ri2 < 0.1, and hence we have to use the exact analysis method for analysis of the first stage. Figure shows the h-parameter equivalent circuit for common emitter configuration.

The same circuit can be redrawn by making collector common to have h-parameter equivalent circuit for common collector for configuration.

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Overall current gain(Ai)

From table, we can say that Darlington connection improves input impedance as well as current gain of the circuit Overall Voltage gain

We know that

By subtracting 1 on both sides we get

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We know that the overall voltage gain in multistage amplifier is a product of individual voltage gain

As we know, input resistance Ri1 >> Ri2 we can neglect term 3 and term 4 in the above equation.

Output Impedance (Ro2) :

From equation, Yo of the transistor is given as

Since

And

Looking at Figure we can see that the Ri1 of the first stage is the source resistance for second stage, i.e. RS2= RO1

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Key Point: • In above analysis we have assumed that the h-parameter of T1 and T2 are identical, • From the above analysis we have seen that Darlington connection of two transistorimproves current gain and input resistance of the circuit.

2.14.2 Bootstrap Emitter Follower

In emitter follower, the input resistance of the amplifier is reduced because of the shunting effect of the biasing resistors. To overcome this problem the emitter follower circuit is modified, as shown in the Figure. Here, two additional components are used, resistance R, and capacitor C .The capacitor, is connected between the emitter and the junction of R1,R2 and R3. For d.c. signal, capacitor C acts as a open circuit and therefore resistance R1,R2 and R3 provides necessary biasing to keep the transistor in active region. For ac signal, the capacitor acts as a short circuit. Its value is chosen such that it provides very low reactance nearly short circuit at lowest operating frequency. Hence for ac, the bottom of R3 is effectively connected to the output(the emitter), whereas the top of R3 is at the -input. (the base). In other words, R3 is connected between input node and output node. For such connection effective input resistance is given by Miller's theorem. The two components are

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R3 is the impedance between output voltage and input voltage and K is the voltage gain.

These are

Since, for an emitter follower, Av, approaches unity, then RM2 becomes extremely large.

The above effect, when Av tends to unity is called bootstrapping. The name arises from the fact that, if one end of the resistor R3 changes in voltage, the other end of R3 moves through the same potential difference; it is as if R3 is pulling itself up by its bootstraps.

The effective load on the emitter follower can be given as

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Because of the capacitor, biasing resistances R1 and R2, come on output side shunting effective load resistance. The resistance RM2 is very large and hence it is often neglected.

Problem 1. For the circuit shown in Figure calculate RLeff , Ri, and Ri’

2. Analyze the following circuit for the following values of resistors and h-parameters

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Solution Analysis of second stage

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Multistage Amplifiers In practice, we need amplifier which can amplify a signal from a very weak source such as a microphone, to a level which is suitable for the operation of another transducer such as loudspeaker . This is achieved by cascading number of amplifier stages, known as multistage amplifier Need for Cascading For faithful amplification amplifier should have desired voltage gain, current gain and it should match its input impedance with the source and output impedance with the load. Many times these primary requirements of the amplifier can not be achieved with single stage amplifier, because of the limitation of the transistor/FET parameters. In such situations more than one amplifier stages are cascaded such that input and output stages provide impedance matching requirements with some amplification and remaining middle stages provide most of the amplification. We can say that, SCE

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• •

When the amplification of a single stage amplifier is not sufficient, or, When the input or output impedance is not of the correct magnitude, for a particular application two or more amplifier stages are connected, in cascade. Such amplifier,with two or more stages is also known as multistage amplifier. Two Stage Cascaded Amplifier

Vi1 is the input of the first stage and Vo2 is the output of second stage. So,Vo2/Vi1 is the overall voltage gain of two stage amplifier.

n-Stage Cascaded Amplifier

Voltage gain : The resultant voltage gain of the multistage amplifier is the product of voltage gains of the various stages. Av = Avl Av2 ... Avn Gain in Decibels In many situations it is found very convenient to compare two powers on logarithmic scale rather than on a linear scale. The unit of this logarithmic scale is called decibel (abbreviated dB). The number N decibels by which a power P2 exceeds the power P1 is defined by

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Decibel, dB denotes power ratio. Negative values of number of dB means that the power P2 is less than the reference power P1 and positive value of number of dB means the power P2 is greater than the reference power P1. For an amplifier, P1 may represent input power, and P2 may represent output power. Both can be given as

Where Ri and Ro are the input and output impedances of the amplifier respectively.Then,

If the input and output impedances of the amplifier are equal i.e. Ri = Ro= R, then

Gain of Multistage Amplifier in dB The gain of a multistage amplifier can be easily calculated if the gain of the individual stages are known in dB, as shown below 20 log10 Av = 20 log10 Avl + 20 log10Av2 +… + 20 log10 Avn Thus, the overall voltage gain in dB of a multistage amplifier is the decibel voltage gains of the individual stages. It can be given as AvdB = AvldB + Av2dB + ... + AvndB Advantages of Representation of Gain in Decibels Logarithmic scale is preferred over linear scale to represent voltage and power gains because of the following reasons : • In multistage amplifiers, it permits to add individual gains of the stages to calculate overall gain. • It allows us to denote, both very small as well as very large quantities of linear, scale by considerably small figures. For example, voltage gain of 0.0000001 can be represented as -140 dB and voltage gain of 1,00,000 can be represented as 100 dB. • Many times output of the amplifier is fed to loudspeakers to produce sound which is received by the human ear. It is important to note that the ear responds to the sound intensities on a proportional or logarithmic scale rather than linear scale. Thus use of dB unit is more appropriate for representation of amplifier gains. Methods of coupling Multistage Amplifiers In multistage amplifier, the output signal of preceding stage is to be coupled to the input circuit of succeeding stage. For this interstage coupling, different types of coupling elements can be employed. These are : 1. RC coupling 2. Transformer coupling 3. Direct coupling RC coupling Figure shows RC coupled amplifier using transistors. The output signal of first stage is coupled to the input of the next stage through coupling capacitor and resistive load at the output terminal of first stage

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The coupling does not affect the quiescent point of the next stage since the coupling capacitor Cc blocks the d.c. voltage of the first stage from reaching the base of the second stage. The RC network is broadband in nature. Therefore, it gives a wideband frequency response without peak at any frequency and hence used to cover a complete A.F amplifier bands. However its frequency response drops off at very low frequencies due to coupling capacitors and also at high frequencies due to shunt capacitors such as stray capacitance.

Transformer Coupling Figure shows transformer coupled amplifier using transistors. The output signal of first stage is coupled to the input of the next stage through an impedance matching transformer

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This type of coupling is used to match the impedance between output and input cascaded stage. Usually, it is used to match the larger output resistance of AF power amplifier to a low impedance load like loudspeaker. As we know, transformer blocks d.c, providing d.c. isolation between the two stages. Therefore, transformer coupling does not affect the quiescent point of the next stage. Frequency response of transformer coupled amplifier is poor in comparison with that an RC coupled amplifier. Its leakage inductance and inter winding capacitances does not allow amplifier to amplify the signals of different frequencies equally well. Inter winding capacitance of the transformer coupled may give rise resonance at certain frequency which makes amplifier to give very high gain at that frequency. By putting shunting capacitors across each winding of the transformer, we can get resonance at any desired RF frequency. Such amplifiers are called tuned voltage amplifiers. These provide high gain at the desired of frequency, i.e. they amplify selective frequencies. For this reason, the transformer-coupled amplifiers are used in radio and TV receivers for amplifying RF signals. As d.c. resistance of the transformer winding is very low, almost all d.c. voltage applied by Vcc is available at the collector. Due to the absence of collector resistance it eliminates unnecessary power loss in the resistor.

Direct Coupling Figure shows direct coupled amplifier using transistors. The output signal of first stage is directly connected to the input of the next stage. This direct coupling allows the quiescent d.c. collector current of first stage to pass through base of the next stage, affecting its biasing conditions.

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Due to absence of RC components, frequency response is good but at higher frequencies shunting capacitors such as stray capacitances reduce gain of the amplifier. The transistor parameters such as VBE and β change with temperature causing the collector current and voltage to change. Because of direct coupling these changes appear at the base of next stage, and hence in the output. Such an unwanted change in the output is called drift and it is serious problem in the direct coupled amplifiers.

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QUESTIONS 2 MARKS 1. What are the advantages of Darlington amplifier? 2. Explain Miller’s theorem. (May/jun 2103) 3. What are the limitations of h parameters? What are practical limitations in selecting very high R E? 4. 5. Define i) Differential gain ii) Common mode gain 6. State Miller’s Theorem. (May,15) 7. How can a DC equivalent circuit of an amplifier be obtained? 8. Draw the Darlington emitter follower circuit. (May,14,13) 9. What does bootstrapping mean? Why bootstrapping is done in a buffer amplifier? 10. Define Common Mode Rejection Ratio. (Nov,09) 11. What is the coupling schemes used in multistage amplifiers? (May,10) 12. What are the advantages of Representation of Gain in Decibels. 13. What is the typical value of CMRR? How the constant current circuit is used to improve the CMRR? (Nov,14) 14. Find the value of αdc when Ic=8.2mA and Ie=8.7mA. 15. What are the advantages of h-parameters? (Nov,14) 16. What is the role of coupling network in multistage amplifiers? 17. Define voltage & current gain of an emitter follower. 18. Why CE amplifier better than CC & CB amplifiers? 19. What is the difference between cascade and cascode amplifier? 20. Mention two importance characteristics of CC circuit. 21. State Bisection Theorem. (Nov,12) 22. Draw the small signal equivalent circuit of CE amplifier. 23. If CMMR of amplifier is 100dB, calculate CM gain if difference gain is1000. 24. Two identical amplifiers are cascaded, having 10dBgain each other. Calculate output voltage if the input of 1mv

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16 MARKS 1. Draw a CE amplifier & its small signal equivalent. Derive its Avs, Ai, Rin, Ro. 2. For the CC amplifier circuit, Find the expressions for input impedance and voltage gain. Assume suitable model for transistor. 3. Explain with circuit diagram of Darlington connection and derive the expression for Ai, Av, Ri &Ro. 4. Explain the emitter coupled differential amplifier with neat diagram & Derive expression for CMRR. 5. Discuss transfer characteristics of differential amplifier. Explain the methods used to improve CMRR. 6. Derive the expressions for the common mode and differential mode gains of a differential amplifier in terms of h-parameters. 7. Compare CE, CB, CC amplifiers. 8. Derive the expressions for the voltage gain, current gain, input and output impedance of emitter follower amplifier. 9. Derive expression for voltage gain of CS & CD amplifier under small signal low frequency condition. 10. Draw a two stage RC coupled amplifier and explain. Compare cascade and cascode amplifier? 11. Consider a single stage CE amplifier with Rs=1kΩ, R1=50KΩ, R2=2KΩ, RC=2KΩ, RL=2KΩ, hfe=50, hie=1.1 KΩ, hoe=25µmho, hre=2.5×10-4. Find Ai,Ri,Av,Ais,Avs and R0. 12. The Darlington amplifier has the following parameters, Rs=3kΩ, RE=3kΩ, hie=1.1 KΩ, hfe=50, hre=2.5×10-4, hoe=25µmho. Then calculate Ai, Ri, Av and R0. 13. The dual input balanced output differential amplifier having Rs=100Ω, RC=4.7KΩ, RE=6.8KΩ, hfe=100, Vcc=+15v and VEE=-15v. Calculate operating point values, differential & common mode gain, CMRR, and output if VS1= 70mV(p-p) at 1 KHz & VS2= 40mV(p-p) at 1 KHz

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3.1 JFET Amplifiers It provides an excellent voltage gain with high input impedance. Due to these characteristics, it is often preferred over BJT. Three basic FET configurations Common source, common drain and common gate 3.2 JFET low frequency a.c Equivalent circuit Figure shows the small signal low frequency a.c Equivalent circuit for n-channel JFET.

Fig3.1 small signal model of JFET 3.3 Common Source Amplifier With Fixed Bias Figure shows Common Source Amplifier With Fixed Bias. The coupling capacitor C1 and C2 which are used to isolate the d.c biasing from the applied ac signal act as short circuits for ac analysis.

Fig3.2 Common source circuit of JFET The following figure shows the low frequency equivalent model for Common Source Amplifier With Fixed Bias. It is drawn by replacing • All capacitors and d.c supply voltages with short circuit • JFET with its low frequency a.c Equivalent circuit

Fig3.3 small signal model of CS JFET amplifier Input Impedance Zi

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Zi = RG Output Impedance Zo

Fig3.4 Equivalent circuit model of JFET for output It is the impedance measured looking from the output side with input voltage Vi equal to Zero. As Vi=0,Vgs =0 and hence gmVgs =0 . And it allows current source to be replaced by an open circuit. So, If the resistance rd is sufficiently large compared to RD, then

3.4 Common source amplifier with self bias (Bypassed Rs)

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Figure shows Common Source Amplifier With self Bias. The coupling capacitor C1 and C2 which are used to isolate the d.c biasing from the applied ac signal act as short circuits for ac analysis. Bypass capacitor Cs also acts as a short circuits for low frequency analysis.

Fig3.5 Common source amplifier model of JFET The following figure shows the low frequency equivalent model for Common Source Amplifier With self Bias.

Fig3.6 Small signal model for Common source amplifier model of JFET

The negative sign in the voltage gain indicates there is a 180o phase shift between input and output voltages.

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3.5 Common source amplifier with self bias (unbypassed Rs)

Fig3.7 Common source amplifier model of JFET Now Rs will be the part of low frequency equivalent model as shown in figure.

Fig3.8 Small signal model for Common source amplifier model of JFET Input Impedance Zi Zi = RG Output Impedance Zo It is given by

Voltage gain (Av) It is given by

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3.6 Common source amplifier with Voltage divider bias (Bypassed Rs) Figure shows Common Source Amplifier With voltage divider Bias. The coupling capacitor C1 and C2 which are used to isolate the d.c biasing from the applied ac signal act as short circuits for ac analysis. Bypass capacitor Cs also acts as a short circuits for low frequency analysis.

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Fig3.9 Common source amplifier with Voltage divider bias(Bypassed Rs) The following figure shows the low frequency equivalent model for Common Source Amplifier With voltage divider Bias

Fig3.10 small model of Common source amplifier with Voltage divider bias(Bypassed Rs) The parameters are given by

The negative sign in the voltage gain indicates there is a 180o phase shift between input and output voltages.

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3.7 Common source amplifier with Voltage divider bias (unbypassed Rs)

Fig3.11 small model of Common source amplifier with Voltage divider bias(without Bypassed Rs) Now Rs will be the part of low frequency equivalent model as shown in figure.

3.8 Common Drain Amplifier In this circuit, input is applied between gate and source and output is taken between source and drain.

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Fig3.12 Circuit of Common Drain amplifier In this circuit, the source voltage is Vs = VG+VGS When a signal is applied to the JFET gate via C1 ,VG varies with the signal. As VGS is fairly constant and Vs = VG+VGS, Vs varies with Vi. The following figure shows the low frequency equivalent model for common drain circuit.

Fig3.13 small model of Common Drain amplifier Input Impedance Zi

Fig3.13 Simplified small model of Common Drain amplifier Zi = RG Output Impedance Zo It is given by

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But Vgs = Vo, so

Voltage gain (Av) It is given by

But

Substitute the value Vo and Vi. Then

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Common drain circuit does not provide voltage gain.& there is no phase shift between input and output voltages. Table summarizes the performance of common drain amplifier

3.9 Common Gate Amplifier In this circuit, input is applied between source and gate and output is taken between drain and gate.

Fig3.14 Circuit diagram of Common gate amplifier In CG Configuration, gate potential is at constant potential. so, increase in input voltage Vi in positive direction increase the negative gate source voltage. Due to ID reduces, reduces, reducing the drop IDRD. Since VD= VDD-IDRD, the reduction in ID results in an increase in output voltage.

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Fig3.15 small signal model for Common gate amplifier 1. Input Impedance (Zi) It is given by

And

After substituting and simplification,

And

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2. Output Impedance Zo

It is given by

3. Voltage gain (Av) It is given by

Using KVL to the outer loop, after simplification

Table summarizes the performance of common gate amplifier

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3.10 Multistage Amplifiers In practice, we need amplifier which can amplify a signal from a very weak source such as a microphone, to a level which is suitable for the operation of another transducer such as loudspeaker . This is achieved by cascading number of amplifier stages, known as multistage amplifier 1. Need for Cascading For faithful amplification amplifier should have desired voltage gain, current gain and it should match its input impedance with the source and output impedance with the load. Many times these primary requirements of the amplifier can not be achieved with single stage amplifier, because of the limitation of the transistor/FET parameters. In such situations more than one amplifier stages are cascaded such that input and output stages provide impedance matching requirements with some amplification and remaining middle stages provide most of the amplification. We can say that, • When the amplification of a single stage amplifier is not sufficient, or, • When the input or output impedance is not of the correct magnitude, for a particular application two or more amplifier stages are connected, in cascade. Such amplifier, with two or more stages is also known as multistage amplifier.

2. Two Stage Cascaded Amplifier

Fig3.16 Cascaded amplifier Vi1 is the input of the first stage and Vo2 is the output of second stage. So,Vo2/Vi1 is the overall voltage gain of two stage amplifier.

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3. n-Stage Cascaded Amplifier

Fig3.17 Multistage amplifier Voltage gain : The resultant voltage gain of the multistage amplifier is the product of voltage gains of the various stages. Av = Avl Av2 ... Avn Gain in Decibels In many situations it is found very convenient to compare two powers on logarithmic scale rather than on a linear scale. The unit of this logarithmic scale is called decibel (abbreviated dB). The number N decibels by which a power P2 exceeds the power P1 is defined by

Decibel, dB denotes power ratio. Negative values of number of dB means that the power P2 is less than the reference power P1 and positive value of number of dB means the power P2 is greater than the reference power P1. For an amplifier, P1 may represent input power, and P2 may represent output power. Both can be given as

Where Ri and Ro are the input and output impedances of the amplifier respectively.Then,

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If the input and output impedances of the amplifier are equal i.e. Ri = Ro= R, then

4. Gain of Multistage Amplifier in dB The gain of a multistage amplifier can be easily calculated if the gain of the individual stages are known in dB, as shown below 20 log10 Av = 20 log10 Avl + 20 log10Av2 +… + 20 log10 Avn Thus, the overall voltage gain in dB of a multistage amplifier is the decibel voltage gains of the individual stages. It can be given as AvdB = AvldB + Av2dB + ... + AvndB Advantages of Representation of Gain in Decibels Logarithmic scale is preferred over linear scale to represent voltage and power gains because of the following reasons : • In multistage amplifiers, it permits to add individual gains of the stages to calculate overall gain. • It allows us to denote, both very small as well as very large quantities of linear, scale by considerably small figures. For example, voltage gain of 0.0000001 can be represented as -140 dB and voltage gain of 1,00,000 can be represented as 100 dB. • Many times output of the amplifier is fed to loudspeakers to produce sound which is received by the human ear. It is important to note that the ear responds to the sound intensities on a proportional or logarithmic scale rather than linear scale. Thus use of dB unit is more appropriate for representation of amplifier gains. 3.11 Small signal Analysis of MOSFET Common-Source Configuration

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Fig3.18 small signal model of Common-Source Configuration of MOSFET

This configuration serves as the gain stage. The disadvantage is high output impedance. Capacitor CS is included such that the stage is connected to a current source for biasing Common-Gate Configuration

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Fig3.18 Common-gate Configuration of MOSFET

Fig3.18 small signal model of Common-gate Configuration of MOSFET

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This amplifier provides gain and is useful when a specific (low) Rin is required. This is, e.g., the case when the impedance needs to be matched, as with transmission lines (e.g. to 50 Ω). Another application of the CG configuration is that it acts as a current buffer (current gain close to unity, small Rin, large Rout). Source Follower (Common-Drain Configuration)

Fig3.19 Common-drain Configuration of MOSFET

Fig3.20 small signal model of Common-drain Configuration of MOSFET

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This configuration acts as a voltage buffer. It provides no gain, but has low output impedance. It is typically the last stage in a multi-stage amplifier.

3.12 Cascaded Amplifiers

Fig3.21 Cascaded amplifier Configuration of MOSFET

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By grouping the different factors in this expression, we can find a physical interpretation for the cascading. This physical interpretation can be used to guide simulation or analysis of the different stages separately, before combining them into a cascaded amplifier.

QUESTIONS 2 MARKS 1. What is meant by small signal? 2. What is the physical meaning of small signal parameter ro? 3. Write the equation for small signal condition that must be satisfied for linear amplifiers. 4. Draw the small signal equivalent circuit common source NMOS. 5. What is another name for common drain amplifier? 6. Draw the source follower amplifier circuit. 7. List the applications of MOSFET amplifiers. 8. Compare the characteristics of three MOSFET amplifier configurations. 9. Draw the small signal equivalent JFET common source circuit. 10. How does a transistor width-to-length ratio affect the small signal voltage gain of a common source amplifier? 11. How a MOSFET can be used to amplify a time varying voltage? 12. How does body effect change the small signal equivalent of the MOSFET? 13. Why in general the magnitude of the voltage gain of a common source amplifier relatively small? 14. What is voltage swing limitation? 15. What is the general condition under which a common gate amplifier would be used?

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16. State the general advantage of using transistors in place of resistors in integrated circuits. 17. Give one reason why a JFET might be used as an input device in a circuit as proposed to a MOSFET. 18. What are features of cascode amplifiers? 19. What are the applications of BiCMOS? 20. Discuss one advantage of BiCMOS circuit. 16 MARKS 1. Describe the operation and analyze the basic JFET amplifier circuits. 2. Derive the small signal analysis of common source amplifier. 3. Develop a small signal model of JFET device and analyze basic JFET amplifiers. 4. Explain graphically the amplification process in a simple MOSFET amplifier circuit. 5. Describe the small signal equivalent circuit of the MOSFET and determine the values of small signal parameters? 6. Sketch the small signal high frequency circuit of a common source amplifier & derive the expression for a voltage gain, input & output admittance and input capacitance. 7. Sketch a simple source-follower amplifier circuit and discuss the general ac circuit characteristics. 8. Characterize the voltage gain and output resistance of a common-gate amplifier. 9. Apply the MOSFET small signal equivalent circuit in the analysis of multistage amplifier circuits. 10. Explain common source amplifier with source resistor and source bypass capacitor. 11. Write short notes Voltage swing limitations, general conditions under which a source follower amplifier would be used. 12. Describe the characteristics of and analyze BiCMOS circuits.

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UNIT IV FREQUENCY ANALYSIS OF BJT AND MOSFET AMPLIFIERS 4.1 General shape of frequency response of amplifiers An audio frequency amplifier which operates over audio frequency range extending from 20 Hz to 20 kHz. Audio frequency amplifiers are used in radio receivers, large public meeting and various announcements to be made for the passengers on railway platforms. Over the range of frequencies at which it is to be used an amplifier should ideally provide the same amplification for all frequencies. The degree to which this is done is usually indicated by the curve known as frequency response curve of the amplifier.

To plot this curve, input voltage to the amplifier is kept constant and frequency of input signal is continuously varied. The output voltage at each frequency of input signal is noted and the gain of the amplifier is calculated. For an audio frequency amplifier, the frequency range is quite large from 20 Hz to 20 kHz. In this frequency response, the gain of the amplifier remains constant in mid-frequency while the gain varies with frequency in low and high frequency regions of the curve. Only at low and high frequency ends, gain deviates from ideal characteristics. The decrease in voltage gain with frequency is called roll-off. 4.2 Definition of cut-off frequencies and bandwidth: The range of frequencies can be specified over which the gain does not deviate more than 70.7% of the maximum gain at some reference mid-frequency.

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From above figure, the frequencies f1 & f2 are called lower cut-off and upper cut-off frequencies. Bandwidth of the amplifier is defined as the difference between f2 & f1. Bandwidth of the amplifier = f2 - f1 The frequency f2 lies in high frequency region while frequency f1 lies in low frequency region. These two frequencies are also called as half-power frequencies since gain or output voltage drops to 70.7% of maximum value and this represents a power level of one half the power at the reference frequency in mid-frequency region. 4.3 Low frequency analysis of amplifier to obtain lower cut-off frequency: 4.3.1 Decibel Unit: The decibel is a logarithmic measurement of the ratio of one power to another or one voltage to another. Voltage gain of the amplifier is represented in decibels (dBs). It is given by, Voltage gain in dB = 20 log Av Power gain in decibels is given by, Power gain in dB = 10 log Ap Where Av is greater than one, gain is positive and when Av is less than one, gain is negative. The positive and negative gain indicates that the amplification and attenuation respectively. Usually the maximum gain is called mid frequency range gain is assigned a 0 db value. Any value of gain below mid frequency range can be referred as 0 db and expressed as a negative db value. Example: Assume that mid frequency gain of a certain amplifier is 100. Then, Voltage gain = 20 log 100 = 40 db At f1 and f2 Av = 100/√2 = 70.7 Voltage gain at f1 = Voltage gain at f2 = 20 log 70.7 = 37 db

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Fig. Normalized voltage gain vs frequency From above figure, it shows that the voltage gain at f1 and f2 is less than 3db of the maximum voltage gain. Due to this the frequencies f1 and f2 are also called as 3 db frequencies. At f1 & f2 power gain drops by 3 db. For all frequencies within the bandwidth, amplifier power gain is at least half of the maximum power gain. This bandwidth is also referred to as 3 db bandwidth. 4.3.2 Significance of octaves and decades: The octaves and decades are the measures of change in frequency. A ten times change in frequency is called a decade. Otherwise, an octave corresponds to a doubling or halving of the frequency. Example: An increase in frequency from 100 Hz to 200 Hz is an octave. A decrease in frequency from 100 kHz to 50 kHz is also an octave.

Fig. Frequency response showing significance of decade and octave At lower and higher frequencies the decrease in the gain of amplifiers is often indicated in terms of db/decades or db/octaves. If the attenuation in gain is 20 db for each decade, then it is indicated by line having slope of 20 db/decade. A rate of -20 db/decade is

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approximately equivalent to -6db/octave. A rate of -40 db/decade is approximately equivalent to -12db/octave. 4.3.3 Midband gain: It is defined as the band of frequencies between 10 f1 and 0.1 f2. It is denoted as midband gain or Amid. The voltage gain of the amplifier outside the midband is approximately given as,

In midband, Midband: Below the midband, As a result, the equation becomes, Below midband:

Above midband, As a result, the equation becomes, Above midband:

Problem: For an amplifier, midband gain = 100 and lower cutoff frequency is 1 kHz. Find the gain of an amplifier at frequency 20 Hz. Solution: Below midband:

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4.4 Effect of various capacitors on frequency response: 4.4.1 Effect of coupling capacitors: The reactance of the capacitor is Xc = 1/2∏fc At medium and high frequencies, the factor f makes Xc very small, so that all coupling capacitors behave as short circuits. At low frequencies, Xc increases. This increase in Xc drops the signal voltage across the capacitor and reduces the circuit gain. As signal frequencies decrease, capacitor reactance increase and gain continues to fall, reducing the output voltage. 4.4.2 Effect of Bypass capacitors: At lower frequencies, bypass capacitor CE is not a short. So emitter is not at ac ground. Xc in parallel with RE creates an impedance. The signal voltage drops across this impedance reducing the circuit gain. 4.4.3 Effect of internal transistor capacitances: At high frequencies, coupling and bypass capacitors act as short circuit and do not affect the amplifier frequency response. At high frequencies, internal capacitances, commonly known as junction capacitances. The following figure shows the junction capacitances for both BJT and FET. Incase of BJT, Cbe is the base emitter junction capacitance and Cbc is the base collector junction capacitance. Incase of FET, Cgs is the internal capacitance between gate and source and Cgd is the internal capacitance between gate and drain.

Fig. Internal transistor capacitances 4.5 Miller Theorem: In transistor amplifiers, it is necessary to split the capacitance between input and output. It can be achieved by using miller’s theorem. In the following figure, Av

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represents absolute voltage gain of the amplifier at midrange frequencies and C represents either Cbc (incase of BJT) or Cgd (incase of FET).

Fig. Splitting of capacitor using Miller’s theorem 4.6 Low frequency analysis of BJT:

Fig. Typical RC coupled common emitter amplifier From above figure, it has three RC networks that affect its gain as the frequency is reduces below midrange. These are, 1. RC network formed by the input coupling capacitor C1 and input impedance of the amplifier. 2. RC network formed by the output coupling capacitor C2, resistance looking in at the collector and load resistance. 3. RC network formed by the emitter bypass capacitor CE and resistance looking in at the emitter. Input RC network: The following figure shows the input RC network formed by C1 and the input impedance of the amplifier. The resistance value is Rin = R1 || R2 || Rin(base)

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Applying voltage divider rule,

A critical point in the amplifier response is generally accepted to occur when the output voltage is 70.7 % of the input. At critical point,

At this condition, Rin = Xc1 Overall gain is reduced due to attenuation provided by the input RC network. The reduction in overall gain is given by,

The frequency fc at this condition is called lower critical frequency and it is given by,

If the resistance of input source is taken into account the above equation becomes,

The phase angle in an input RC circuit is expressed as

Output RC network:

The above figure shows the output RC network formed by C2, resistance looking in at the collector and load resistance.

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The critical frequency for this RC network is given by,

The phase angle in output RC network is given as,

Bypass network:

From above figure,

is the resistance looking in at the emitter. It is derived as follows, R= (Vb / βIb) + hie / β

Where RTH = R1 || R2 || Rs. It is the thevenin’s equivalent resistance looking from the base of the transistor towards the input. The critical frequency for the bypass network is

Problem: Determine the low frequency response of the amplifier circuit shown in the figure.

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Solution: It is necessary to analyze each network to determine the critical frequency of the amplifier.

The above analysis shows that the input network produces the dominant lower critical frequency. Then the low frequency response of the given amplifier is shown in the following figure.

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4.7 Low frequency analysis of FET amplifier:

From above figure, it has two RC networks that affect its gain as the frequency is reduced below midrange. These are, 1. RC network formed by the input coupling capacitor C1 and input impedance of the amplifier. 2. RC network formed by the output coupling capacitor and the output impedance looking in at the drain. `Input RC network: Lower critical frequency of this network is given as,

The value of Rin(gate) can be determined from the data sheet as follows:

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The phase shift in low frequency input RC circuit is θ = tan-1 (XC1 / Rin ) Output RC network: Lower critical frequency of this network is given as,

The phase shift in low frequency output RC circuit is θ = tan-1 (XC2 / RD + RL) 4.8 Hybrid - π equivalent circuits of BJTs: At low frequencies, we can analyze the transistor using h-parameters. But for high frequency, analysis of h-parameter model is not suitable for following reasons. 1. The values of h-parameters are not constant at high frequencies. So it is necessary to analyze transistor at each and every frequency which is impractical. 2. At high frequency h-parameters become complex in nature. Due to the above reasons, modified T model and hybrid ∏ models are used for high frequency analysis of the transistor. These models give a reasonable compromise between accuracy and simplicity to do high frequency analysis of the transistor. 4.4.1 Hybrid - π common emitter transistor model: Common emitter circuit is most important practical configuration and this is useful for the analysis of transistor using hybrid - ∏ model. The following figure shows the hybrid - ∏ model for a transistor in CE configuration. For this model, all parameters are assumed to be independent of frequency. But they may vary with the quiescent operating point.

Fig. Hybrid - ∏ model for a transistor in CE configuration 4.8.1 Elements in hybrid – π model: Cb’e and Cb’c : Forward biased PN junction exhibits a capacitive effect called diffusion capacitance. This capacitive effect of normally forward biased base-emitter junction of the transistor is represented by Cb’e or Ce. The diffusion capacitance is connected between b’ and e represents the excess minority carrier storage in the base. The reverse bias PN junction exhibits a capacitive effect called transition capacitance. This capacitive effect of normally reverse biased collector base junction of the transistor is represented by Cb’c or Cc.

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rbb’: The internal node b’ is physically not accessible bulk node b represents external base terminal. rb’e: It is the portion of the base emitter which may be thought of as being in series with the collector junction. This establishes a virtual base b’ for junction capacitances to be connected instead of b. rb’c: Due to early effect, varying voltages across collector to emitter junction results in base-width modulation. A change in the effective base-width causes the emitter current to change. This feedback effect between output and input is taken into account by connecting gb’c or rb’c between b’ and c. gm: Due to small changes in voltage Vb’e across emitter junction, there is excess minority carrier concentration injected into the base which is proportional to Vb’e. So resulting small signal collector current with collector shorted to the emitter is also proportional to Vb’e. gm is also called as transconductance and it is given as,

rce: It is the output resistance. It is also the result of early effect. 4.4.1.2 Hybrid – π parameter values: The following table shows the typical values for hybrid - π parameters at room temperature and for Ic = 1.3mA. Parameter Meaning Value gm rbb’ rb’e or gb’e rb’c or gb’c

rce or gce Ce Cc

Mutual conductance Base spreading resistance Resistance between b’ and e Conductance between b’ and e Resistance of reverse biased PN junction between base and collector Conductance of reverse biased PN junction between base and collector Output resistance between c and e Conductance between c and e Junction capacitance between b and e Junction capacitance between base and collector

50mA/V 100Ω 1kΩ 1m mho 4MΩ 0.25*10-6 mho 80kΩ 12.5*10-6 mho 100pF 3pF

4.8.2 Hybrid – π conductances: 4.8.2.1 Transistor Transconductance gm:

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Let us consider a p-n-p transistor in CE configuration with Vcc bias in the collector circuit as shown in the above figure. Transconductance gm is given as,

The collector current in active region is given as,

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For Ic = 1.3mA, gm = 0.05mho or 50 mA/V. For Ic = 7.8mA, gm = 0.3mho or 300mA/V. These values are much larger than the transconductances obtained with FETs. 4.8.2.2 Input Conductance gb’e:

First consider h-parameter model for CE configuration. Applying KCL to output circuit,

Making Vce = 0, the short circuit current gain hfe is defined as,

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Substituting the value of IC / Ib,

4.8.2.3 Feedback Conductance gb’c: Let us consider h-parameter model for CE configuration with input open circuit (Ib = 0), Vi is given as,

Fig. Hybrid –π model for CE configuration With Ib = 0, Vce is given as,

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Vce =

I1 = Voltage between b’ and e, Vb’e can be given as, Vb’e =

With Ib = 0, Vi = Vb’e

Substituting the value of Vi,

hreVce =

rb’c =

Substituting the value of rb’e,

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4.8.2.4.Base Spreading Resistance rbb’:

Substituting the value of rb’e,

4.8.2.5 Output Resistance gce: Using h-parameters output conductance is given as,

Applying KCL to the output circuit,

1/rce = gce = Relation between hybrid-π and h-parameters:

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4.4.3 Hybrid – π capacitances:

Ce = gm -------2πft 4.4.4 CE short circuit current gain using hybrid- π model:

Fig. Hybrid- π model for a single transistor with a resistive load RL

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The current gain for the circuit is,

Fig. Frequency vs current gain

fβ (Cutoff frequency):

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It is the frequency at which the transistor short circuit CE current gain drops by 3dB or 1/√√2 times from its value at low frequency. It is given as,

fα (Cut-off frequency): It is the frequency at which the transistor short circuit CB current gain drops by 3dB or 1/√√2 times from its value at low frequency. The current gain for CB configuration is given as,

Parameter fT: It is the frequency at which short circuit CE current gain becomes unity. At f = fT,

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The ratio of fT / fβ is quite large compared to 1. fT = gm / 2πCe Problem: Short circuit CE current gain of transistor is 25 at a frequency of 2MHz if fβ = 200 kHz. Calculate (i) fT (ii) hfe (iii) Find |Ai| at a frequency of 10 MHz and 100 MHz. Solution:

4.4.5 Current gain with resistive load:

For further simplification, At output circuit value of Cc can be calculated as,

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Fig. Simplified hybrid – π model for CE with RL Z = Vb’e ------Ib

Ai =

fH is the frequency at which the transistor gain drops by 3dB or 1/√2 times from its value at low frequency. It is given as, 143 Visit : www.EasyEngineeering.net

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4.8.6 Current gain including source resistance:

Ais at low frequency =

= - hfe RS _______ Rs + hie 144 Visit : www.EasyEngineeering.net

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4.8.7 Voltage gain including source resistance:

4.8.8 Cutoff frequency including source resistance:

For RL = 0,

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4.8.9 Gain Bandwidth Product: 4.8.9.1 Gain Bandwidth Product for Voltage:

= RL fT -------- * -------Rs + rbb’ 1 + 2πfTCCRL 4.8.9.2 Gain Bandwidth Product for current:

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4.9 High frequency analysis of FET 4.9.1 Common source amplifier at high frequencies:

Voltage gain:

Input Admittance:

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Input capacitance (Miller Effect):

This increase in input capacitance Ci over the capacitance from gate to source is called Miller effect. This input capacitance affects the gain at high frequencies in the operation of cascaded amplifiers. In cascaded amplifiers, the output from one stage is used as the input to a second amplifier. The input impedance of a second stage acts as a shunt across output of the first stage and Rd is shunted by the capacitance Ci. Output Admittance: From above figure, the output impedance is obtained by looking into the drain with the input voltage set equal to zero. If Vi = 0 in figure, rd , Cds and Cgd in parallel. Hence the output admittance with RL considered external to the amplifier is given by, 4.9.2 Common Drain Amplifier at High Frequencies:

Fig. Common Drain Amplifier Circuit & Small signal equivalent circuit at high frequencies Voltage gain: The output voltage Vo can be found from the product of the short circuit and the impedance between terminals S and N. Voltage gain is given by,

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Input Admittance: It is given by,

Input Admittance Yi can be obtained by applying Miller’s theorem to Cgs.

Output Admittance: given by,

Output Admittance Yo with Rs considered external to the amplifier, it is

At low frequencies, output resistance Ro is given by,

4.9.3 Frequency Response of Common Source Amplifier:

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Let us consider a typical common source amplifier as shown in the above figure.

From above figure, it shows the high frequency equivalent circuit for the given amplifier circuit. It shows that at high frequencies coupling and bypass capacitors act as short circuits and do not affect the amplifier high frequency response. The equivalent circuit shows internal capacitances which affect the high frequency response. Using Miller theorem, this high frequency equivalent circuit can be further simplified as follows: The internal capacitance Cgd can be splitted into Cin(miller) and Cout(miller) as shown in the following figure.

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Where

From simplified high frequency equivalent circuit, it has two RC networks which affect the high frequency response of the amplifier. These are, 1. Input RC network 2. Output RC network Input RC network:

Fig. Input RC network From above figure,

This network is further reduced as follows since Rs << RG

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Fig. Reduced input RC network The critical frequency for the reduced input RC network is,

Output RC network:

Fig. Output RC network The critical frequency for the above circuit is,

fc = It is not necessary that these frequencies should be equal. The network which has lower critical frequency than other network is called dominant network.

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The phase shift in high frequency is Problem: Determine the high frequency response of the amplifier circuit shown in the following figure.

Solution: Before calculating critical frequencies it is necessary to calculate mid frequency gain of the given amplifier circuit. This is required to calculate Cin(miller) and Cout(miller). Av = -gmRD Here RD should be replaced by RD || RL Av=

Cin(miller)=

Cout(miller)=

Cgs = Ciss – Crss = 4pF Now analyze the input and output network for critical frequency,

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fc(input)

=

The above analysis shows that the output network produces the dominant higher critical frequency. High frequency response of the given amplifier is shown in the following figure.

Fig. High frequency response of the amplifier 4.10 Frequency Response of Multistage Amplifiers: The bandwidth of multistage amplifier is always less than that of the bandwidth of single stage amplifier. 4.10.1 Overall Lower Cut-off Frequency of Multistage Amplifier:

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Let us consider the lower 3dB frequency of n identical cascaded stages as fL (n). It is the frequency for which the overall gain falls to 1/√2 (3dB) of its midband value.

Squaring on both the sides &

Taking square root on both the sides,

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4.10.2 Overall Higher Cut-off Frequency of Multistage Amplifier: Let us consider the upper 3dB frequency of n identical cascaded stages as fH(n). It is the frequency for which the overall gain falls to 1/√2 (3dB) of its midband value.

Squaring both the sides,

Taking nth root on both the sides, 21/n = 1 + [ fH(n)/fH ]2 21/n -1 = [ fH(n)/fH ]2 Taking square root on both the sides, √21/n -1 = fH(n)/fH fH(n) = fH √21/n -1 In multistage amplifier fL(n) is always greater than fL and fH(n) is always less than fH. So the bandwidth of multistage amplifier is always less than single stage amplifier.

4.11 Rise time and its Relation to Upper Cut-off Frequency: 4.11.1 Upper 3 dB Frequency:

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When a step input is applied, amplifier high frequency RC network prevent the output from responding immediately to the step input. The output voltage starts from zero and rises towards the steady state value V, with a time constant R2C2 as shown in the above figure. The output voltage is given by, The time required for Vo to reach one-tenth of its final value is calculated as,

The difference between these two values is called as rise time tr of the circuit. The rise time is given as,

The Upper 3dB frequency is given as, Upper 3dB frequency in terms of rise time is given as,

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From above equation, it shows that upper 3dB frequency is inversely proportional to the rise time tr. 4.12 Relation between Bandwidth and Rise time: The frequency range from fL to fH is called bandwidth of the amplifier. Usually fL << fH. So we can approximate the equation for bandwidth as follows,

The relation between rise time with upper frequency as,

So we can relate bandwidth with rise time as follows,

Problem: If the rise time of BJT is 35ns, what is the bandwidth that can be obtained using this BJT. Solution: tr = 0.35 / f2 = 0.35 / BW BW = 0.35 / tr = 0.35 / (35 * 10-9) = 10MHz 4.9 Sag and its Relation to Lower Cut-off Frequency: The amplifier low frequency RC network consists of coupling and bypass capacitors make amplifier output to decrease with large time constant. As a result, the output voltage has sag or tilt associated with it as shown in the following figure.

The tilt or sag in time t1 is given by,

The lower 3 dB frequency can be determined from the output response by carefully measuring the tilt. The lower 3 dB frequency is given as,

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So, the lower 3 dB frequency can be represented in terms of tilt is measured from the following figure.

= πfL / f * 100 fL = Pf ____ 100π Problem 1: For a circuit shown in the following figure, calculate percentage tilt. Assume approximate h-parameter circuit for the transistor.

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Equivalent h-parameter circuit for the given circuit is,

Here R1 = RC + RL = 4K + 2K = 6KΩ

fL =

fL = We know that, P = (∏fL / f) * 100 Assuming f = 200 Hz P = (∏ * 2.65 / 200) * 100 P = 4.1%

QUESTIONS 2 MARKS 1. Draw the frequency response curve of an amplifier. 2. What is the bandwidth of an amplifier? 3. Define rise time. 4. What kind of techniques required increasing the input impedance? 5. Give relation between rise time and bandwidth. 6. Give the main reason for the drop in gain at the low frequency region & high frequency region. 7. If the rise time of BJT is 35nS, what is the bandwidth that can be obtained using this BJT? 8. For an amplifier, mid band gain is 100 & lower cutoff frequency is 20KHz. Find the gain of an amplifier at frequency 20Hz. 9. For an amplifier, 3dB gain is 200 & higher cutoff frequency is 20KHz. Find the gain of an amplifier at frequency 100KHz. 10. Why common base amplifier is preferred for high frequency signal when compared to CE amplifier? 11. Draw the hybrid π equivalent circuit of BJTs. 12. What is the difference between small signal equivalent & hybrid π equivalent circuit. 160 Visit : www.EasyEngineeering.net

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13. What is high frequency effect? 14. What are the causes for occurrence of upper cutoff frequency in BJT? 15. What is Miller’s effect? What is gain bandwidth product? 16. Give equation of overall lower and upper cutoff frequency of multistage amplifier. 17. What is significance of octaves and decades in frequency response? 18. What are the causes for occurrence of upper cutoff frequency in BJT? 19. What is the major contribution to the Miller capacitance in a MOSFET? 20. Define cut off frequency for a MOSFET. 16 MARKS 1. With neat sketch explain hybrid π CE transistor model. Derive the expression for various components in terms of ‘h’ parameters. 2. Discuss the frequency response of multistage amplifiers. Calculate the overall upper & lower cutoff frequencies. 3. Discuss the low frequency response & the high frequency response of an amplifier. Derive its cutoff frequencies. 4. Discuss the terms rise time and sag. 5. Write short notes on high frequency amplifier. 6. Derive the gain bandwidth for high frequency FET amplifiers. 7. Derive the expression for the CE short circuit current gain of transistor at high frequency 8. What is the effect of Cb’e on the input circuit of a BJT amplifier at High frequencies? Derive the equation for gm which gives the relation between gm, Ic and temperature. 9. Explain the high frequency analysis of JFET with necessary circuit diagram & gain bandwidth product. 10. Discuss the frequency response of MOSFET CS amplifier. 11. Determine the bandwidth of CE amplifier with the following specifications. R1=100kΩ, R2=10kΩ, RC=9kΩ, RE=2kΩ, C1= C2=25µF, CE=50µF, rbb’=100Ω, rb’e=1.1KΩ, hfe=225, Cb’e=3pF and Cb’c=100pF. 12. At Ic=1mA & VCE=10v, a certain transistor data shows Cc=Cb’c=3pF, hfe=200, & ωT=-500M rad/sec. Calculate gm, rb’e, Ce=Cb’e & ωβ.

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UNIT -V IC MOSFET AMPLIFIERS 5.1 Integrated Circuit Amplifier An integrated circuit amplifier is a compactly packaged collection of active and passive devices that may boost the voltage or current level of a signal. The active components are transistors, three-terminal semiconductor devices that are capable of current gain, wherein a small change in current produces a pro-rated change in the integrated circuit amplifier output. 5.1.1 IC Design Philosophy Integrated circuits More and more electronics circuits are integrated in a single chip More complicated functions Smaller size and lower cost Suitable for mass-production Implementation cost depends on device area rather than device count Large/moderate-value resistors should be avoided Larger/moderate-value capacitors should be avoided Preferable to use transistors due to chip-area consideration Design Philosophy The design philosophy for ICs is different from that of discrete-component circuits Realize as many of functions as possible by using transistors only Rely on device matching or size ratios for circuit design Active loads are typically used for amplifier designs 5.2 IC Biasing - Basic MOSFET current source Using the transistors geometries (W/L)1and (W/L)2as design parameters, we want to create a DC current Io, as long as transistor Q2is in Saturation Mode The Drain of transistor Q2is connected to a load circuit, not necessarily a resistor. The load circuit typically involves one or more additional MOSFET transistors. Depending on the load, transistor Q2may be in any of three modes: Saturation, Triode or Cutoff. Of course, only when it is in Saturation it will work as originally planned (DC current source) The current Io always goes away from the load circuit and into Q2. Such a DC current source is said to be a sink. • MOSFET current mirror is widely used for ICs with good device matching. • Q1 and Q2 are identical and in saturation:

Fig5.8: MOSFET Current Source

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Current gain or current transfer ratio:

Effect of VO on IO Current mismatch due to channel-length modulation

Fig5.8: VI characteristics of NMOS current source 5.4 MOS current-steering circuits A current mirror may consist of many MOSFET current sources This circuit is particularly useful in integrated circuit design, where one resistor R is used to make multiple current sources the current mirror simply ensures that the gate to source voltages of each transistor is equal to the gate to source voltage of the reference • Current sink: pulls a dc current from a circuit • Current source: pushes a dc current into a circuit • All transistors should be operated in saturation • Current mismatch exists for a finite VA (channel-length modulation)

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Fig5.8: MOS current-steering circuits

VGSref = VGS 1 =VGS 2 =VGS 3 = " ref Therefore, if each transistor is identical (i.e., K ref = K1 = " , andVt =Vt 1 =Vt 2 = " ) then:

Iref = Kref (VGSref −Vt ref )

2

= Kn (VGSn −Vtn ) = IDn 2

if the MOSFETS are not identical. Specifically, consider the case where

Vtn = Vt ref ).

we know that VGSn

=VGSref

now be:

still, even when Kn

≠ K ref .

Kn ≠ K ref

Thus, the drain current

IDn

(but

will

IDn = Kn (VGSn −Vtn )

2

(

= Kn VGSref −Vt ref ⎛I = Kn ⎜ ref ⎜K ⎝ ref ⎛ K =⎜ n ⎜K ⎝ ref

)

2

⎞ ⎟⎟ ⎠

⎞ ⎟⎟ Iref ⎠

I ref (i.e., K1 = 2 K ref ), then ID 1 will be twice as large as

The drain current is a scaled value of

I ref

if K1 is twice that of K ref (i.e.,

I1 = 2 I ref ).

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From the standpoint of integrated circuit design, we can change the value of K by modifying the MOSFET channel width-to-length ratio (W/L) for each transistor.

( ) ( )

1 k′ W Kn 2 L = 1 k′W Kref 2 L

n

ref

W ) ( L = (W L )

n

ref

5.5 NMOS Current Sources and Sinks Characteristics of Current Sources • A well controlled output current • Supplied current does not depend on output voltage and has High Norton Resistance • Connect a voltage source to the gate of another MOSFET:

Fig5.9:NMOS current Source

Hence, IREF depends on the supply voltage VDD. If the supply is a battery or similar device, then this will change over time, causing the reference current to also vary with time. IOUT scales with IREF by W/L ratios of two MOSFETs SCE                                                                       165                                                           Dept of ECE Visit : www.EasyEngineeering.net

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Fig5.10:I-V characteristics of NMOS current source 5.6 PMOS Current Source • NMOS current source sinks current to ground • PMOS current source sources current from positive supply

Fig5.11 :PMOS Current Mirror: Same operation and characteristics as NMOS voltage source. PMOS needs to be larger to attain the same Rout. 5.7 MOSFET Differential amplifier

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Problem 1.Find the CMRR for the circuit with given data.

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2 MARKS 1. What are the basic processes in integrated circuit fabrication? 2. Define common mode rejection ration? What is the ideal value? 3. Sketch the DC transfer characteristics of a MOSFET differential amplifier. 4. What are the advantages of an active load? 5. What is the impedance seen looking into a simple active load? 6. How the reference portion of the circuit can be designed with MOSFETs only. 7. How should a MOSFET be biased so as to operate as a stable current source? 8. Draw the circuit of MOSFET differential amplifier with active load. 9. What is the need for MOSFET differential amplifier with cascode active load? 10. What is meant by matched transistors? 11. Define common mode and differential mode input resistance and voltages. 12. What are the limiting factors for the maximum current in MOSFET? 13. Define enhancement and depletion mode of MOSFET. 14. Define saturation and non- saturation bias regions. 15. How do you prove that a MOSFET is biased in the saturation region? 16. Draw MOSFET cascode current source circuit. 17. What is another name of two transistor current source? 18. Draw the two transistor MOSFET current source. 19. What is Widlar current source 20. What is cascode current mirror? SCE                                                                       171                                                           Dept of ECE Visit : www.EasyEngineeering.net

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16 MARKS 1. Describe the operation of an NMOS amplifier with either an enhancement load, a depletion load, or a PMOS load. 2. Explain the basic MOSFET two transistor current circuits and discuss its operation. 3. Draw the MOSFET cascode current source circuit, explain and discuss the advantage of this design. 4. Sketch and describe the advantages of a MOSFET cascode current source used with a MOSFET differential amplifier. 5. Explain CMOS differential amplifier and derive CMRR. 7. Draw a Widlar current source and explain the operation. 8. Describe the operation of a PMOS amplifier with an enhancement load, a depletion load. 9. Explain the CMOS common source and source follower with neat diagram. 10. Explain the large signal behavior of MOSFETs and compare the operating regions of Bipolar and MOS transistors. 11. Discuss the operation of active load and discuss the advantages of MOSFET cascode current circuit. 12. Explain in detail about CMOS common source and source follower with neat diagram.

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