ECS Trans. 34 (1), 1017 (2011) Electrical Quality of III-V/Oxide Interfaces: Good Enough for MOSFET Devices? G. Brammertza, A. Aliana, H. C. Lina, L. Nynsa, S. Sionckea, C. Mercklinga, W.-E Wanga, M. Caymaxa, T. Y. Hoffmanna a

imec, Kapeldreef 75, 3001 Leuven, Belgium

We will present the defect density at In0.53Ga0.47As and InP interfaces with ALD Al2O3 derived by use of the conductance method and from simulation of low frequency CV-curves. Consequences of the interface state distribution for MOS transistor device operation will be highlighted through 1-dimensional electrostatic simulations. The simulation results will be compared as much as possible to different state-of-the-art transistor results presented in literature. Introduction 40 Dit from electrostatic simulations

Dit (1012/eVcm 2)

35

Dit from conductance method

30 25 20 15 10 5 0

0

0.2

0.4

0.6

0.8

1

E-Ev (eV)

Figure 1. Interface state density at the In0.53Ga0.47As-Al2O3 interface as a function of energy in the bandgap as measured with admittance spectroscopy at various temperatures (red circles, for details see (7)) and as derived from electrostatic simulations of lowfrequency CV-curves (blue line, for details see (8)). Zero on the energy axis corresponds to the In0.53Ga0.47As valence band maximum, the In0.53Ga0.47As conduction band minimum is represented by the vertical black line. Interface states in resonance with the conduction band (at energies inside the conduction band) can be derived from the electrostatic simulations. High electron mobility materials like III-V semiconductors are currently being studied because of their potential to improve Metal-Oxide-Semiconductor (MOS) transistor performance at scaled drive voltages (close to 0.5 V), as compared to more traditional Si MOS transistors at similar drive voltages (1). Transistors based on In0.53Ga0.47As channels have until now shown promising device properties and are therefore being widely studied in the community (2-6). As a possible interfacial passivation layer, InP has been used in MOS transistor devices and much increased drive currents have been measured for

otherwise same device geometry and processing (3). In the following, we will present the interface state density distribution of In0.53Ga0.47As and InP interfaces with atomic layer deposited (ALD) high-k dielectrics such as Al2O3, HfO2, LaAlO3 and GdAlO3 as measured by admittance spectroscopy and as derived from low frequency CV-simulations. We will use these interface state density distributions in order to derive the surface potential movement of III-V MOS transistor devices and to verify the effect of the interface state density on the sub-threshold slope (SS) of MOS transistors. Discussion Figure 1 shows the interface state density of In0.53Ga0.47As/Al2O3 interfaces as derived from admittance spectroscopy measurements (7) and from electrostatic simulations of low frequency CV-measurements (8). The 10 nm Al2O3 high-k dielectric presents a k-value of 9 and was deposited by ALD at 300°C with trimethylaluminum (TMA) and H2O precursors. Prior to ALD deposition the In0.53Ga0.47As surface was cleaned with a 5 min 26% (NH4)2S clean followed by 5 min DI water rinse.

Figure 2. Normalized experimental conductance Gp/Aωq of an In0.53Ga0.47As-Al2O3 pMOS capacitor as a function of measurement frequency for five different bias voltages going from depletion (Vg=0.1 V) to the onset of inversion (Vg = 0.5 eV) (a). The multifrequency (100 Hz - 1MHz) CV-curves corresponding to the conductance measurements are shown in the upper right hand side corner (b). Schematic band diagrams for Vg = 0.1 V and Vg = 0.5 V with schematic drawings of the density of donor-like interface state charges are shown as well (c). The agreement between the interface state density derived from admittance spectroscopy and the one derived from the electrostatic simulations is quite good within the estimated errors of the methods. It can be seen that mainly close to the conduction band minimum the interface state density is low. As this is the energy range in which the surface potential moves for nMOS device operation, to first order it can be estimated that the surface potential movement will not be too much hindered by this interface state density. The density of interface states inside the conduction band can also be derived from the electrostatic simulations. With the conductance method these defect states

cannot be assessed, as they are in resonance with the conduction band and present time constants in excess of 10 MHz, which is the usual maximum frequency accessible for AC-conductance measurements. Also important to know is that the interface state density inside the whole InGaAs bandgap is donor-like, even for the defect states in the upper half of the bandgap. Figure 2 shows the experimental normalized conductance Gp/Aωq as a function of measurement frequency measured for five different bias voltages on a ptype In0.53Ga0.47As-Al2O3 MOS capacitor. As can be seen on the left hand side figure, the full width at half maximum (FWHM) of the conductance peaks decreases as the Fermi level approaches the conduction band minimum. The FWHM of the conductance peak can be directly linked to the band bending fluctuations, which are generally assumed to increase as the amount of interface state charge increases. From figure 2(a) it can be seen that the FWHM of the conductance peaks decreases as the surface Fermi level moves up inside the bandgap. This would therefore imply that the interface states neutralize as the Fermi level moves upwards in energy, which is only the case for donor-like interface states. When the surface Fermi level is close to the conduction band minimum, the extrabroadening due to band bending fluctuations σs is close to zero, which would imply that at this energy the total charge at the semiconductor/oxide interface is close to zero. The Fermi level stabilization energy of In0.53Ga0.47As interfaces is therefore close to the conduction band minimum energy. No large flat-band voltage shifts of n-type In0.53Ga0.47As MOS devices are therefore expected as well as a free flat-band voltage modulation with gate metal.

Figure 3. AC-measurements of four n-type In0.53Ga0.47As MOS capacitors with different 10 nm ALD-deposited high-k dielectrics. 15 different frequencies varying logarithmically from 100 Hz to 1 MHz are shown. Presently, in all measured cases, the In0.53Ga0.47As/high-k oxide interface state density does not vary fundamentally when the nature or the processing condition of the high-k dielectric is varied. Although some minor differences can be seen between different high-k dielectrics, the overall interface state distribution is in all investigated cases similar to figure 1. To illustrate this statement, figure 3 shows CV-curves of n-type In0.53Ga0.47As MOS capacitors with four different 10 nm thick ALD-deposited high-k dielectrics. Prior to ALD deposition all the In0.53Ga0.47As surfaces received a 5 min 1:10 HCl:H2O clean followed by 5 min DI water rinse. Although the k-values of the oxides

differ depending on the material, the overall CV-curve shape is similar in all cases, which implies an interface state distribution that is quite similar in all four cases. The InP/high-k oxide interface seems to present quite similar interface state properties with low interface state density close to the conduction band minimum and increasing donor-like interface state density towards the valence band maximum side. Figure 4 shows the interface state density derived from room-temperature and low temperature CV-measurements on n-type InP MOS capacitors (9).

Figure 4. Interface state distribution at the InP-Al2O3 interface as derived from variable temperature admittance spectroscopy measurements (for details see (9)).

Figure 5. Band diagrams of III-V quantum well MOSFET devices. The buffer layer consists of undoped In0.52Al0.48As, whereas the channel layer consists of 10 nm undoped In0.53Ga0.47As. The left hand side figures correspond to the situation with the high-k dielectric (not shown in the figure) deposited straight on the channel layer, whereas the right hand side figures correspond to the situation with a thin InP layer in between the channel and the high-k dielectric. The top figures show the band structures when the devices are in the ON-state, with 3 1012 cm-2 electrons in the channel, whereas the bottom two figures show the band structures when the devices are in the OFF state, with 106 cm-2 electrons in the channel.

Knowing the interface state distributions of In0.53Ga0.47As and InP interfaces with high-k dielectrics, we can easily simulate the effect that the interface state charges have on the SS of the devices. We therefore simulate the Poisson equation for a typical quantum-well MOSHEMT structure consisting of a thick undoped In0.52Al0.48As buffer layer covered by a 10 nm thick undoped In0.53Ga0.47As channel layer. We will investigate the case where the high-k dielectric is deposited directly on top of the In0.53Ga0.47As channel layer as well as the case where a 2 nm thick InP cap layer is deposited on top of the In0.53Ga0.47As channel, such that the interface with the high-k dielectric is on top of the InP cap layer. Figure 5 shows the band diagrams of the two previously described quantum-well MOSFET devices. From the band diagrams we can see that in the case of the devices without InP cap layer, the surface Fermi level moves from about 0.3 eV below the In0.53Ga0.47As conduction band minimum to about 0.3 eV above the In0.53Ga0.47As conduction band minimum, when the device switches from the OFF-state to the ON-state. In the case of the device with the InP cap, the surface Fermi level moves from about 0.5 eV below the InP conduction band minimum to about 0.1 eV above the InP conduction band minimum, when the device switches from the OFF-state to the ONstate. These are therefore the regions of interest for our interface state density analysis.

Figure 6. Surface potential and channel electron charge as a function of gate bias voltage for a device with a 4 nm EOT oxide deposited directly on the InGaAs channel. The gate metal work function was chosen as being 4.7 eV. The two lower curves show the amount of charged interface states in the ON- and OFF-state of the transistor. Calculations correspond well to experimental data in (10). Using the interface state density from figures 1 and 4, we can calculate the amount of charge at the semiconductor-oxide interface due to interface states in the ON- and OFFstate of the devices, as well as the effect that these charges have on the SS of the devices. Figure 6 shows the results of such a simple first order analysis for the case of a device with a 4 nm EOT gate dielectric deposited directly on top of the channel layer. Such a device corresponds to the device presented in ref (10). The same analysis applied to a

device with a 1 nm EOT gate dielectric deposited on top of a 2 nm thick InP cap layer is shown in figure 7. Such a device corresponds to the device presented in reference (11). In both cases it can be seen that the effect of the interface states on the SS of the devices is relatively limited, though not completely absent, as measured experimentally on the devices. In order to reach close to 70 mV/dec SS, a further reduction of the interface state density at the In0.53Ga0.47As and InP interfaces with high-k dielectrics is desirable.

Figure 7. Surface potential and channel electron charge as a function of gate bias voltage for a device with a 1 nm EOT oxide deposited on a 2 nm InP cap layer on the InGaAs channel. The gate metal work function was chosen as being 4.9 eV. The two lower curves show the amount of charged interface states in the ON- and OFF-state of the transistor. Calculations correspond well to experimental data in (11). References 1. G. Dewey, M. K. Hudait, K. Lee, R. Pillarisetty, W. Rachmady, M. Radosavljevic, T. Rakshit, R. Chau, IEEE Electron Dev. Lett., 29, 1094 (2009). 2. N. Goel et al., IEDM Tech. Dig., 363 (2008). 3. H. Zhao, Y.T. Chen, J. H. Yum, Y. Wang,1 N. Goel, J.C. Lee, Appl. Phys. Lett., 94, 193502 (2009). 4. H. D. Trinh, E.Y. Chang, et al., Appl. Phys. Lett., 97, 042903 (2010). 5. H. C. Lin, W. E. Wang, G. Brammertz, M. Meuris, M. Heyns, Microelectronic Eng. 86, 1554 (2009). 6. R. J. W. Hill, R. Droopad, et al. Electronics Lett. 44, 498 (2008) and 44, 1283 (2008). 7. G. Brammertz, H.C. Lin, K. Martens, D. Mercier, C. Merckling, J. Penaud, C. Adelmann, S. Sioncke, W.E. Wang, M. Caymax, M. Meuris, M. Heyns, ECS Trans., 16, 507 (2008). 8. G. Brammertz, H.C. Lin, M. Caymax, M. Meuris, M. Heyns, M. Passlack, Appl. Phys. Lett., 95, 202109 (2009). 9. H.C. Lin, G. Brammertz, S. Sioncke, L. Nyns, A. Alian, W.E. Wang, M. Heyns, M. Caymax, T.Y. Hoffmann, ECS Trans., this volume.

10. A. Alian, C. Merckling, G. Brammertz, M. Meuris, K. De Meyer, M. Heyns, as discussed at the 2010 IEEE SISC, San Diego, CA. (2010). 11. M. Radosavljevic, B. Chu-Kung, et al., IEEE IEDM Tech. Digest, 319 (2009).

ECS Trans. 34 (1), 1017 (2011)

High electron mobility materials like III-V semiconductors are currently being ... state density distribution of In0.53Ga0.47As and InP interfaces with atomic layer.

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