Agni College of Technology Embedded Systems Question Bank Year : III Department : Electrical and Electronics Engineering Faculty Incharge :Dr.N.V.S.SreeRathna Lakshmi

Part A

1. Define Linear model. The Linear or Waterfall models executes all phases of the EDLC in sequence ,one after the another.It is best suited method for the product development, where the requirement are fixed. 2. Define Prototyping model. It is a variation to the Interative model in which a refined protypeos produced at the end of each iteration.It is best suited model for developing embedded products whose requirements are not fully available at the time of starting the project and are subject to change. 3. Name the important terms of RTOS? Task State Scheduler Shared data Reentrancy 4. Define process. Process is a computational unit that processes on a CPU under the control of a scheduling kernel of an OS. It has a process structure, called Process control block. A process defines a sequentially executing program and its state. 5. What is shared data problem? If a variable is used in two different processes and another task if interrupts before the operation on that data is completed then the value of the variable may differ from the one expected if the earlier operation had been completed .This ids known as shared data problem.

6. What is smart card? Smart card stores and process information through electronicscircuits embedded in the silicon in a plastic substrate body.It is portable and tamper resistant computer .It carries both processing power and information.

7. What are the bits in I2C corresponding to? It has seven fields for start,7 bit address, defining a read or a write, defining byte as acknowledging byte, data byte, NACK and end

8. Define device driver. A device driver is software for controlling, receiving and sending byte or a stream of bytes fromor to a device.

9. Define software timer. This is software that executes and increases or decreases a count variable on an interrupt from a timer output or form a real time clock interrupt. A software timer can also generate interrupt on overflow of count value or on finishing value of the count variable. 10. What is USB? USB (Universal Serial Bus) is a standard for serial bus communication between the system and devices like scanner, keyboard, printer and mouse. There is a root-hub and all nodes have a tree like structure. 11. What are the different modes of DMA transfer? Which one is suitable for embedded system?   

Single transfer at a time and then release of the hold on the system bus. Burst transfer at a time and then release of the hold on the system bus. A burst may be of a few kB. Bulk transfer and then release of the hold on the system bus after the transfer is completed.

12. List the evaluation metrics of Embedded Systems. Five metrics for the evaluation of the efficiency of an embedded system: • Power consumption • Code-size • Run-time efficiency • Weight • Cost

13. Define Spiral model. Spiral model is the EDLC model combining linear and prototyping model to give the best possible risk minimisation in product development. 14. Compare the Data flow model and the State machine model. Both the Data flow model and the stste machine model are the models of computation.The data flow model of computation is used in signal processing design and modelling of DSP algorithms. On the other hand FSMs have been developed to solve a different class of problems, namesly sequential control.FSMs are an appropriate modelling approach for control- dominant applications.Mixing data flow with FSMs is a good solution for representing a system which requires both signal processing and control.The integrated method is very useful to eradicate the drawbacks. 15. What is a thread? Thread is a concept in Java and UNIX and it is a light weight sub process or process in an application program. It is controlled by the OS kernel. It has a process structure, called thread stack, at the memory. It has a unique ID .It have states in the system as follows: stating, running, blocked and finished. 16. Define Inter process communication. An output from one task passed to another task through the scheduler and use of signals, exception, semaphore, queues, mailbox, pipes, sockets, and RPC. 17. Define Semaphore. Semaphore provides a mechanism to let a task wait till another finishes. It is a way of synchronizing concurrent processing operations. When a semaphore is taken by a task then that task has access to the necessary resources. When given the resources unlock. Semaphore can be used as an event flag or as a resource key. 18. Draw the data frame format of CAN? Start

1

Arbitration Control

Data

field

field

field

12

6

0-64

CRC field

16

Acknowledgement End frame Field 2

7

19. Define ROM image. Final stage software is also called as ROM image .The final implement able software for a product embeds in the ROM as an image at a frame. Bytes at each address must be defined for creating the image.

of

20. What is Timer and counting devices? A time gets the inputs from the internal clock with the processor or system clock. Counting device is a unit for getting the count-inputs on the occurrence of events that may be at irregular intervals. 21. Define Target Hardware Debugging. A target system differs from a final system. It interfaces with the computer as well works as a standalone system. There might be repeated downloading of the codes into it during the development phase. The target system copies simply, work later as the embedded system. 22. Define Real Time Clock (RTC)? Real time clock is a clock which once the system starts does not stop and can’t be reset and its count value can’t be reloaded. It generates system interrupts periodically for the schedulers, real time programs and saving of periodic date and time. 23. List the important considerations when selecting a processor.       

Little Endian and Big Endian Mode Performance Memory I/O Address Space Atomic Operations Energy Conservation Clock frequency

24. What are the additional structural units in advanced embedded processor? Additional structural units in advanced embedded processor which may be used are FLPU (Floating point processor Unit), MMU (Memory Management Unit), PFCU (Prefetch control Unit) etc. It also includes instruction pipelining unit, which improves performance by processing instruction in multiple stages and RISC architecture which executes most instructions in single cycle

PART B 1. Describe the structural units of embedded systems.

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MAR – Memory Address Register It holds the address of the byte or word to be fetched from external memories MDR – Memory Data Register It holds the byte or word to be fetched from external memory or I/O address Internal Bus – Internally connects all the structural units inside the processor. Its width can be of 8,16,32,64 bits Address Bus – It is an external bus that carries the address from the MAR to the memory as well as to I/O devices and the other units. Data Bus – It is an external bus that carries the data from or to the address determined by MAR Control Bus – It is an external bus that carries , control signals to or between the processor and memory BIU – Bus Interface Unit – It is the interface unit between the processors internal units with the external unit buses IR – Instruction Register – It takes sequentially the instruction codes to the execution unit of the processor ID- Instruction Decoder- It decodes the instruction opcode received at the IR and passes it to the processor CU. CU – Control Unit – It controls all the bus activities and unit functions needed for processing

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2.

ALU – Arithmetic Logic Unit – It is the unit to execute the arithmetic and logic instructions according to the current instruction present at the IR. PC – Program Counter – It generates the instruction cycle to fetch the address of next instruction to be executed. SP – Stack Pointer – It is a pointer for an address which corresponds to a stack top in memory. ARS – Application Register set – It is a set of on-chip registers used during processing of instructions of the application program. I- Cache (Instruction Cache) – It Sequentially stores, like an instruction queue, the instructions in FIFO mode. BT Cache ( Branch Target Cache)- It facilitates the ready availability of the next instruction set, when a branch instruction like call, jump, loop is encountered. D- Cache ( Data Cache) – It stores the pre fetched data from the external memory. PFCU (Prefetch Control Unit) – It is a unit that controls the fetching of data into the ICache and D-Cache in advance from the memory unit. The instructions and data are delivered when needed to the processor’s execution units. MMU – Memory management Unit – It manages the memories such that the instruction and data are readily available for processing FLPU – Floating point processing unit – A separate unit from ALU for floating point processing, which is essential for processing mathematical functions. FRS – Floating point register set – A register set dedicated for storing floating point numbers in a standard format. Advanced Processing Unit – These are units used for multistage pipeline processing, to obtain processing speeds higher than one instruction per cycle. AOU – Atomic Operation Unit – It manages to complete the broken process before the interrupt of the processor occurs.

Explain in detail about the CAN Bus.  Developed by Bosch . In the past , automotive manufacturers connected electronic devices in vehicles using point to point wiring systems. Manufacturers began to use more and more electronics in vehicles, which results in bulky wire harnesses that were heavy and expensive. 

A number of devices are located and are distributed in a Vehicular Control Network (VCN). An automobile uses a number of distributed embedded controllers. The controllers provide the controls for brakes, engines, electric power , lamps , temperature, air conditioning, car gate , front panel display, meters display panels and cruising. CAN Benefits

o Low cost, Light Weight Network : An advantage to tis is that electronic control units can have single CAN interface for both analog and digital. So the overall cost and size is less. o Broadcast Communication : Each of the devices on the network has a CAN controller chip and is therefore intelligent. All devices on the network see all the transmitted messages. Each device can decide if a message is relevant or if it should be filtered. o Priority : Every message has a priority , so if two nodes try to send messages simultaneously , the one with higher priority gets transmitted and the one with the lower priority gets postponed. This arbitration is nondestructive and results in non-interrupted transmission of the highest priority message. o Error Capabilities : The CAN specification includes a Cyclic Redundancy Code (CRC) to perform error checking on each frame’s content.

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SOF (start-of-frame) bit – indicates the beginning of a message with a dominant (logic 0) bit.

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Arbitration ID – identifies the message and indicates the message's priority. Frames come in two formats -- standard, which uses an 11-bit arbitration ID, and extended, which uses a 29-bit arbitration ID.

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IDE (identifier extension) bit – allows differentiation between standard and extended frames.

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RTR (remote transmission request) bit – serves to differentiate a remote frame from a data frame. A dominant (logic 0) RTR bit indicates a data frame. A recessive (logic 1) RTR bit indicates a remote frame. Generally data transmission is performed on an autonomous basis with the data source node sending out a Data frame. Sometimes the destination also requests by sending a remote frame.

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DLC (data length code) – indicates the number of bytes the data field contains.

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Data Field – contains 0 to 8 bytes of data.

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CRC (cyclic redundancy check) – contains 15-bit cyclic redundancy check code and a recessive delimiter bit. The CRC field is used for error detection.

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ACK (ACKnowledgement) slot – any CAN controller that correctly receives the message sends an ACK bit at the end of the message.

Explain about Serial Peripheral Interface Bus and I2C Bus in detail.

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The Serial Peripheral Interface (SPI) bus is a synchronous serial communication interface , used for short distance communication, in embedded system. The interface was developed by Motorola. SPI devices communicate in full duplex mode using a master – slave architecture with single master. Master slave devices are supported through selection with individual slave select (SS) lines. Serial Peripheral Interface with single master and single slave

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Serial Peripheral Interface with single master and Multiple Interface It has four signals SCLK : Serial Clock ( Output from master) MOSI: Master Output, Slave Input (Output from master) MISO: Master Input, Slave Output (Output from slave) SS : Slave Select (active low, Output from master) During communicating, the master device initiates a transaction by generating a clock and selecting a device using the slave select signal. Data is then transferred in both the directions on the MOSI and MISO lines. Because data is transferred in both the directions of M, it is upto the device to know , whether incoming data is meaningful and whether the transaction is read, write or both. Data Transmission To begin communication, the bus master configures the clock, using a frequency supported by the slave device, typically up to a few MHz. The master then selects the slave device with a logic level 0 on the select line. If a waiting period is required, such as for analog-to-digital conversion, the master must wait for at least that period of time before issuing clock cycles.

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During each SPI clock cycle, a full duplex data transmission occurs. The master sends a bit on the MOSI line and the slave reads it, while the slave sends a bit on the MISO line and the master reads it. This sequence is maintained even when only onedirectional data transfer is intended.

I2C Bus Distributed Systems (ICs) on I Distributed Systems (ICs) on I2C Bus using C Bus using serial data line and clock serial data line and clock

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It has two lines that carry its signals.

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One line for the clock and other for data.

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I2c is a serial bus for interconnecting Ics. It has start bit and stop bit.

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It was originally developed at Philips semiconductors.

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There are 3 I2c bus standards.

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100 kbps I2c ,SM i2C and 400 kbps I2C.

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Master is a source device, one that transmits the clock pulses for synchronization at the destination.

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Master can address 127 other slaves at an instance. Each slave can also optionally have I2C bus controller or a processing element.

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First field of 1 bit

Start bit

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Second field of 7 bits

Address field, which defines slave address , which is being sent the data frame by the master using SDA (Serial Data) and SCL (Serial Clock

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Third field of 1 bit

)

Control field , which defines whether read or write cycle

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Fourth field of 1 bit

Control field, whether the present data is acknowledgement.

Fifth field of 8 bit •

Sixth field of 1 bit

Data field for I2C device data byte NACK (Negative Acknowledgement) field in data frame, if active then acknowledgement not needed from slave, else expected from slave.

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Seventh field of 1 bit

STOP bit

First Byte in Data Transfer on the I2C Bus MSB

LSB

R / Wr 7 – Bit Slave Address R/Wr 0 – Slave written to by Master 1 – Slave read by Master ACK – Generated by the slave whose address has been output.

ACK

Data Formats

Applications  There are some specific applications for certain types of I2C devices such as TV or radio tuners, but in most cases a general purpose I2C device can be used in many different applications because of its simple construction.

4.

Elucidate all the memory management methods in embedded systems •

Memory Allocation : When a process is created , the memory manager allocates the memory addresses to it by mapping the process address space.

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Memory Management : The memory manager of the OS has to be secure , robust and well protected. There must not be errors arising out of memory leaks and buffer overflows.

Memory manager manages •

Use of memory address space by a process.

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Specific mechanism to share the memory space.

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Specific mechanisms to restrict sharing of a given memory space.

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Optimization of access periods of a memory by using hierarchy of memories [ Caches ,primary memory, external secondary and optical memories].

Memory Managing Strategy

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Fixed Allocation : Memory address is divided into blocks with processes having small address space getting small number of blocks and processes with big address space getting a larger number of blocks.

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Dynamic block Allocation : Memory address space is divided into blocks with process having small address spaces getting a larger number of blocks to start with. The memory manager later allocates variable size blocks dynamically allocated from a free list of memory blocks description table at the different computation phases of a process.

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Dynamic Page Allocation : Memory has fixed sized blocks called pages and the memory manager allocates the pages dynamically with a page descriptor table.

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Dynamic Data Memory Allocation : The manager allocates memory dynamically to different data structures like nodes of a list , queues and stacks.

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Multiprocessor memory allocation : The manager adopts an allocation strategy either the memory is shared with tight coupling between two or more processors or shared with loose coupling or there is a multi – segmented.

5.

What is meant by process? What are the various process state and transition?. Explain about preemptive and non –preemptive Scheduling. •

Multitasking involves the execution switching among the different tasks. Determining which tasks/process is to be executed at a given point of time is known as task/process scheduling.

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The scheduling policies are implemented in an algorithm and it is run by the kernel as a service. The kernel service/application, which implements the scheduling algorithm, is known as ‘scheduler’.

Process states and state transition •

The process traverses through a series of states during its transition from the newly created to the terminated state. The cycle through which a process changes its state from ‘newly created’ to execution completed is called as ‘process Life cycle’.

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Created state : The state at which a process is being created is referred to as ‘Created State’.

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Ready State : The state where a process is incepted into the memory and awaiting the processor time for execution, is known as ‘Ready state’.

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Running State: The state where in the source code instructions corresponding to process is being executed is called ‘Running State’.

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Blocked/Wait State : A state where a running process is temporarily suspended from execution and does not have immediate access to resources. Completed State : A state where the process completes its execution is known as ‘Completed state’. Transition State : The transition of process from one state to another is known as Transition State.

Process states Non- Preemptive Scheduling In this scheduling type, the currently executing task/process is allowed to run until it terminates or enters the ‘wait’ state waiting for an I/O or system resource. The various types of non –preemptive scheduling adopted in task/process scheduling are

1. 2. 3. 4.

First Come First Served(FCFS). Last Come First Served (LCFS). Shortest Job First (SJF). Priority Based Scheduling. Preemptive Scheduling In preemptive scheduling every process in ready state gets a chance to execute. – – – –

Task execution is preempted and resumed later Preemption occurs to execute higher priority task. Offers higher schedulability Involves higher scheduling overhead due to context switching

1. Round Robin scheduling. 2. Priority scheduling.

6.

Explain the various issues in hardware and software codesign.

System Description Modeling

HW/SW Partitioning

Software synthesis

Interface synthesis

System integration

Unified representation

Hardware synthesis

Instruction set level HW/SW evaluation

Specification • List the functions of a system that describe the behavior of an abstraction clearly with out ambiguity. Modeling: • Process of conceptualizing and refining the specifications, and producing a hardware and software model.

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HW-SW system involves specification modeling design space exploration and partitioning synthesis and optimization validation implementation

Validation: Process of achieving a reasonable level of confidence that the system will work as designed. Takes different flavors per application domain: cosimulation for performance and correctness Implementation: Physical realization of the hardware (through synthesis) and of executable software (through compilation).

Partitioning and Scheduling (where and when)

7.

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A hardware/software partitioning represents a physical partition of system functionality into application-specific hardware and software.

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Scheduling is to assign an execution start time to each task in a set, where tasks are linked by some relations.

Give the case study of an embedded system for a smart card.

Smart card is one of the most used embedded system today. It is used for credit, debit bank card, ewallet card, identification card, medical card (for history and diagnosis details) and card for a number of new innovative application.

EMBEDDED HARDWARE COMPONEBTS   

Microcontroller or ASIP RAM for temporary variables and Stack OTP ROM for application codes and RTOS codes for scheduling the tasks

   



Flash for storing user data, user address, user identification codes, card number and expiry date Timer and interrupt controller A carrier frequency generating circuit and ASK modulator Interfacing circuit for the IOs. Charge pumps for delivering power to the antenna for transmission and for the system circuits.

EMBEDDED SOFTWARE COMPONENTS        

Boot-up, initialization and OS program Smart card secure file system Connection establishment and termination Communication with the host Cryptography algorithm Host authentication Card authentication Saving addition parameters or recent new data sent by the host(ex- balance receipt)

Smart card hardware  Aplastic card in ISO standard dimensions, 85.60 mm x 53.98 x 0.80mm. It is an embedded SoC (System-On-Chip). [ISO standards - ISO7816 (1 to 4) for host-machine contact based card and ISO14443 (Part A or B) for the contactless cards.]  Microcontroller C68HC11D0 or PIC16C84 or a smart card processor Philips Smart XA or an ASIP Processor.  Needs 8 kB+ internal RAM and 32 kB EPROM and 2/3 wire protected memory.  CPU special features, for example, a security lock

Tasks and their synchronization model