EKT422 – COMPUTER ARCHITECTURE

SW ER S

TEST 1 (1 HOUR)

Name: _____________________________________________________________ Student ID: _________________________________________________________

A

N

Program: ___________________________________________________________

Part A – Multiple Choice. Answer all questions. [20 marks] 1. How are data and instructions stored in the Von Neumann architecture? A. In separate memories B. Dual ported memory C. Unified read-write memory D. None of the above 2. Which of the following depicts an embedded system? A. Multi-core processor unit. B. Application specific Core C. Hardware Software Combination to perform specific application D. All of the above 3. The performance of a processor can be measured using A. Clock period B. Cycles per Instruction C. Throughput D. All of the above 4. The Memory Address register stores the address of the word stored in which part of the architecture? A. I/O B. Program Counter C. Memory Buffer Register D. None of the above 5. What are the parts of an instruction cycle ? A. Fetch and Execute Cycle B. Fetch, decode and execute cycles C. Decode and Store cycle D. Fetch, decode, execute and store. 6. Which of the following is not a state of the instruction cycle? A. Operand address calculation B. Data write back C. Instruction fetch D. None of the above. 7. Which of the following approach is used to handle multiple interrupts? A. Parallel interrupt processing B. Disable interrupts and priority assignment C. Interrupt wait D. None of the above. 8. What are the interconnection wires not in the bus structure? A. Data lines B. Instruction lines C. Address lines D. Control lines 9. In which type of timing does the clock act as a reference? A. Interrupt timing B. Asynchronous timing C. Synchronous timing D. Sequential timing 10. Which of the following is a bus arbitration scheme? A. Round-robin B. Priority C. First come first serve D. All of the above

11. Performance of the memory is decided by which of the following parameters A. Transfer rate B. Latency C. Cycle time D. All of the above 12. When is a cache block is written into the main memory A. Valid bit is not set B. Every cycle C. Dirty bit is set D. None of the above 13. An important attribute of RAM memories is A. Random access & non-volatile B. Volatile C. Sequential access D. None of the above 14. How often/how is data written into the ROM A. Anytime/when required B. Before use – by microprogramming C. During manufacturing D. All of the above 15. Redundancy is a built-in feature here A. Magnetic disks B. RAID C. Serial I/O tapes D. Optical disks 16. RAID level 0 is primarily used in applications where A. Cost is a priority B. Reliability is a priority C. Area is a priority D. All of the above 17. Bit density is more in which device A. Compact disk B. Magnetic tape C. DVD D. Magnetic disk 18. Which of the following is a example for a communication I/O? A. Monitor B. Mouse C. Modem D. USB 19. This technique for data transfer does not involve the processor A. Direct Memory access B. Programmed I/O C. Memory-mapped I/O D. All the above 20. What part of the OS stores utilities or frequently accessed functions? A. Memory B. Registers C. Kernel D. None of the above

Part B – Discussion and Problem Solving. Answer all questions. [80 marks] Q1) Discuss the definitions for computer architecture and computer organization based on what is presented in this course. Describe how these terms relate to the job of a hardware design engineer and an operating systems developer. [20 marks] Computer Architecture - attributes of a system that is visible to a programmer or that have a direct impact on the logical executions a program - e.g. instruction set, data size&representations, I/O mechanisms Computer Organization - operational units and the interconnections to realize the architectural specifications - e.g. control signals, ALU, peripheral interfaces and memory technology A hardware design engineer is responsible to implement the architectural specifications given along with performance specifications, which defines the organizational aspects of the system. An operating systems developer need to write a kernel that provides a systems interface that can fully utilize the architectural specifications given based on knowledge of available hardware. **NOTE** The definition may vary since this is an open topic for discussion – some text may define it differently. This course encourage the students to define these terms as they see fit based on their field of study/interest. Open 20 marks as long as you don't go astray.

Q2) Four benchmark programs are executed on three computers with the following results: Computer A

Computer B

Computer C

Program 1

1

10

100

Program 2

500

100

20

Program 3

500

1000

50

Program 4

100

800

50

The table shows the execution time in seconds, with 100,000,000 instructions executed in each of the four programs. Calculate the MIPS values for each computer for each program. Then calculate the arithmetic and harmonic means assuming equal weights for the four programs, and rank the computers based on each averaging methods. Show your calculations and fill in the tables below. [40 marks] Computer A

Computer B

Computer C

Program 1

100

10

1

Program 2

0.2

1

5

Program 3

0.2

0.1

2

Program 4

1

0.125

2

Arithmetic Mean

Rank

Computer A

25.35

1

Computer B

2.80625

2

Computer C

2.5

3

Harmonic Mean

Rank

Computer A

0.3633

2

Computer B

0.2094

3

Computer C

1.8182

1

MIPS rate given as

MIPS=

Ic T ×106 m

Arithmetic mean is Harmonic mean is

1 ∑R . m i=1 i m RH= m ∑ R1 . i =1 i RA=

.

Q3) Assume that one 16-bit and two 8-bit microprocessors are to be interfaced to a single system bus. Given the following details: • • • • •

All microprocessors have the hardware features required for any type of data transfer: programmed I/O, interrupt driven I/O and DMA. All microprocessors have 16-bit address bus. Two memory boards with 64Kb capacity each are interfaced to the bus. The system bus supports a maximum of 4 interrupt lines and one DMA line. A DMA controller and a generic I/O device controller (with 4 interrupt lines) also needs to be on the bus.

Make all the necessary assumptions and draw a block diagram of the multiprocessor system and label all signal lines (with size). Focus on the bus lines. [20marks] **Note that this is an open question – you may make any assumptions to create the system. Assumptions for this solution: – The 64KB memory modules have an 8-bit interface – No bus control necessary – simple arbitration logic decides which processor gets bus time – when DMA uses the bus, ALL processor will be on HOLD state – Bus interrupt controller needs to be interfaced to the processor (select one or create logic for more) – this is for interrupt I/O