IV Semester B.E. (E&C) Degree Examination, January 2013 (2K6 Scheme) EC- 401 : ELECTRONIC COMPONENT AND CMOS TECHNOLOGY Time : 3 Hours
Max. Marks : 100
Instructions : 1) Assume missing data suitably. 2) Answer five questions selecting at least two from each Part. PART – A 1. a) With neat sketches, explain the fabrication of different types of integrated resistors.
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b) What is epitaxy ? Distinguish between vapour phase epitaxy and liquid phase epitaxy.
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2. a) With neat sketches, explain the step-by-step procedure of fabrication of NMOS/ PMOS devices using twin-well process. 15 b) Discuss packaging design considerations.
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3. a) Discuss the issues related to thin films and their deposition.
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b) Explain with sketches, PVD and CVD methods of thin films deposition.
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4. a) Discuss packaging fabrication technologies.
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b) Explain the following : i) Resistor colour codes ii) Capacitor colour codes.
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PART – B 5. a) Derive the expression for maximum depletion region depth of MOS structure. b) Explain the operation of NMOS and PMOS transistor’s in different regions.
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P.T.O.
*EJ776*
EJ – 776
6. a) Derive the expression for dynamic power dissipation of CMOS inverter. b) Derive the expression for CPHL of CMOS inverter. 7. a) For the CMOS inverter circuit shown in fig. 7(a) with VDD = 3.3V, the IV characteristics of the NMOS transistor are specified as follows.
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When VGS = 3.3V, the drain current reaches its saturation level Isat = 2mA for VDS > 2.5V. Assume that the input signal applied to the gate is a step pulse that switches instantaneously from OV to 3.3V. Using the data above, calculate the delay time necessary for the output to fall from its initial value of 3.3V to 1.65V, assuming an output load capacitance of 100fF.
Fig. 7(a) b) With a neat circuit diagrams, explain the operation of CMOS SR latch based on NOR gates. 10 8. a) With a neat circuit diagram, explain the operation of CMOS based D-latch. b) Explain : i) Compensation of opamps ii) Current amplifiers. ————————
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