47.1

Electronics Beyond Nano-scale CMOS Shekhar Borkar

Microprocessor Technology Lab, JF2-04, 2111 NE 25h Ave, Hillsboro, OR 97124. [email protected] ABSTRACT

This paper presents nano-scale CMOS outlook, discusses the three tenets that have made electronics successful in the past, and using these tenets conclude that there is nothing on the horizon yet that has promise to replace CMOS. Therefore, we will make CMOS work for a foreseeable work for a foreseeable future.

High Volume

ManufactuiNng

65

45

32

22

16

11

8

Integration

4

8

16

32

64

128

256

Delay= scaling CV/I

-0.7

>0.7

(nm)

Capacity (BT) future.

2006 2008 2010 2012 2014 2016 2018

Technology Node

Energy/Logic Op >0.5 >0.5 scaling____

Categories and Subject Descriptors

B.7.1 Microprocessors and microcomputers, VLSI.

Variability

General Terms

CMOS, Design, Variations, Performance, Reliability. Keywords: CMOS, Power, Nano, Variability.

Medium

Delay scaling will slow down Energy scaling will slow down _____________ High

Table 1

subthreshold leakage power has become

1. Introduction

Electronics has evolved tremendously in the last century. In the early days, switches and electro-magnetic relays were used as primitive logic gates for control. They were much faster and reliable than mechanical devices. Since then, the evolution has been relentless: relays replaced by vacuum tubes, and subsequently by discrete bipolar transistors. The advent of of compactness and integrated circuits added ..another . . .dimension . .................... reliability. MOS transistors were electronically inferior compared to their bipolar counterparts, but were integration friendly, and hence became the comer-stone of Moore's Law (doubling of transistors every two years). CMOS was on the horizon then, but was considered exotic and expensive, offered low power but lower performance too; it found use mostly in battery operated devices such as watches. But later it replaced plain (N and P) MOS due to

excessive,

Very High

and therefore

expect supply voltage and threshold voltage scaling to slow down in the future, resulting in lower energy, power, and delay reduction. Random dopant fluctuations and sub-wavelengh lithogaph will result in static variations, supply voltage and temperature reutmhigher variations will cause dynamic variations, and the variability in general will continue to become worse [2]. Higher electric fields will worsen transistor reliability and degradation. Total transistors ~~on a chip will continue to double every two years; however, due to variability and degradation, design will be challenging, shifting to . . a

improved circuit robustness and reduced power, and it has lasted

higr.ty

How far will this continue, and what comes after nano-scale CMOS? To answer this question, let's look at why electronics evolution in the past was successful.

3. The Three Tenets

for a long time (thirty years!). CMOS has now scaled down into nano-scale regime. Where is CMOS going, and what comes after it? To address these questions, first let's look at where CMOS iS headed.

Electronics evolution was successful because it followed the three tenets: .() (3) Scalability. 1l Gain (2) (2) Signal gn to noise and (3) ty Evaluate electronic components, both past and present, against these three tenets and notice that all of them followed these tenets, without

2. CMOS Outlook

Gain: Even an electro-magnetic relay has current gain; it switches higher current than the current flowing through the coil. Vacuum tubes, bipolar transistors, -and MOS all exhibit voltage or current

exception.

Table 1 shows CMOS technology outlook extrapolated from the trends that we see today. Notice that today's nano-scale CMOS is at 65nm node, where the transistor channel lengths are even smaller, of the order of 35nm. As the technology scales every two years, the transistor integration capacity doubles (Moore's Law), gate delay reduces by 30%, energy per logic operation reduces by 65%, and power consumption reduces by 50% [1].

gain. Signal to noise: Electronic circuits built with relays, vacuum tubes, bipolar transistors, and MOS all create signals that are higher than the noise floor. That is, you don't have to hunt for a signal in the noise at the operating temperature.

Scalability: Scalability in some shape or form is essential. It does not mean Fdimension scaling MOS tran or relays alone aledas ininsietheancasee of frOm s scaled size largetres to small,vac ut s,

Transistor threshold voltages have reduced to the extent that

Pennission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. To copy otherwise, or

. .'

.

. .

bipolar transistor, and MOS integrated circuits all exhibit scaling

republish, to post on servers or to redistribute to lists, requires prior specific perisionan/ora ee DAC 2006, July 24-28, 2006, San Francisco, California, U.S.A. Cprgt2006 ACM 1-59593-381-6/06/0007 .............. $5.00. Copyright

807

property.

Gain allows you to build circuits with increasing signal strength, and makes logic fan out possible. A single logic gate must drive

more logic gates to realize a logic function, and voltage or current

is essential. Without gain it may be possible to build memory ~~~~~~~~~~~~~~gain (storage) circuits, but not logic.

Signals must have sufficient energy to distinguish from background noise, otherwise you will have to hunt for signal in the noise, spending more energy. Scalability allows you to pack more electronics, provides higher performance, lower energy and power, all at lower cost. Thus providing more and move value with each generation for reduced cost.

vacuum tubes to today's CMOS. Gate delay has reduced from mili-seconds to now pico-seconds, improving performance by

orders of magnitude. Figure 3 shows how energy per logic operation has scaled down to keep power dissipation within limit. Notice that throughout electronic evolution in the last century the three tenets were followed, consequently the integration capacity increased, performance improved, and energy (power) reduced, thus continually providing more end user value with lower cost.

4. Evaluation Let us evaluate how electronics has adhered to these three tenets and provided the value that we enjoy today.

5. What is after CMOS?

1.E+05

V Tubes

I.E+03

1.E+01

2 I.E-01

cost. Is there anything in sight that meets these tenets? Carbon Nano-Tubes and compound semiconductors look somewhat promising to replace today's silicon based CMOS. These technologies may meet some of the tenets, and some of

Bol

1.E-03 *r) 1.E-05 n 1.E-07

Any technology that will replace CMOS must follow the three tenets and continue to provide higher end user value with lower

NMOS

-

1 E-09

I.E-I13 1930

, 1950

1970

them have potential. After all, these technologies will replace

CMOS _.E-Il 1990

silicon with some still be CMOS.

We also hear a lot of reports regarding advances in Quantum, Optical, Biological, and Chemical devices as a potential solution beyond nano-scale CMOS [4]. In some cases these technologies have been demonstrated at a much smaller level, such as a logic gate or a single bit memory. To realize these technologies in practice, however, they must follow the three tenets, have to mature, and still retain the benefit. So far, we have not seen any technologies that follow these tenets; let alone waiting for them to mature. All of these technologies show no gain, operate at cryogenic temperatures with poor signal to noise ratio, hence impractical to build electronic circuits which work and replace

2010

Figure 1 shows scaling of size over the years. Vacuum tubes, bipolar transistors, and MOS transistors followed dimension scaling, improving density, and thus reducing cost.

I.E-02 1.E-03

V Tubes

1.E-04 1.E-0s

0

1.E-07 I .E-08

.

NMOS

1.E-09

I.E-10 I.E-11 1930

CMOS. Therefore, CMOS is here to stay,

Bipolar

rI.E-06

1950

1970

* CMOS

1990

even beyond nano-scale [5]. It still have a lot of room left for further advancement beyond \will the nano-regime. This will not be easy, it will be faced with challenges [2], but they are not insurmountable.

6. Conclusion in We presented outlook nano-regime, history of with CMOS in the electronics three tenets that madetheelectronics successful past, and using these tenets concluded that there is nothing on the horizon that has promise to replace CMOS at least in the next ten to fifteen years. Therefore, we will make CMOS work until then.

2010

Figure 2: Delay scaling Figure 2 shows scaling of gate delay over time, starting from 1.E+01

1.E-01 1.E-03

I.E-05

@ 1.E-07 o 1.E-09 1.EI.-11 1.E-1 3

I.E-1

* I.E-117 1930

other material in the MOS transistor, but will

7. References

V Tubes

[I] Shekhar Borkar, "Design Challenges of Technology Scaling,

IEEE Micro", July-August 1999. [2] Shekhar Borkar et al, "Parameter Variations and Impact on Circuits and Microarchitecture", DAC 2003 [3] Shekhar Borkar, "Designig Reliable Systems from Unreliable Bipolar* Components: The Challenges of Transistor Variability and \ IEEE Micro, November-December 2005. Degradation", NMOS _ \ CMOs UNM[4] T. C. Chen, "Where Si-CMOS is going: Trendy Hype vs Real ''vsTechnology", ISSCC 2006. _ _ __ [5] George Sery, "Life Is CMOS: Why Chase the Life After?", DAC 2002. 1950 1970 2010 1990

Figure 3: Energy per logic operation

808

Electronics Beyond Nano-scale CMOS - IEEE Xplore

in the future, resulting in lower energy, power, and delay. Electronics has evolved tremendously in the last century. In the reduction. early days, switches and ...

944KB Sizes 8 Downloads 344 Views

Recommend Documents

Characterization of CMOS Metamaterial Transmission ... - IEEE Xplore
IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 62, NO. 9, SEPTEMBER 2015. Characterization of CMOS Metamaterial. Transmission Line by Compact.

Local Clustering 3-D Stacked CMOS Technology for ... - IEEE Xplore
is developed to closely pack devices in a number of standard cells to form local clusters. Based on the 3-D stacked CMOS technology, an analysis to extend the ...

Radiation effects in a CMOS active pixel sensor - IEEE Xplore
Abstract—A CMOS active pixel sensor has been evaluated with Co60, 10 MeV proton and heavy-ion irradiation. Perma- nent displacement damage effects were ...

Minimizing power consumption in digital CMOS circuits - IEEE Xplore
scaling strategy, which uses parallelism and pipelining, to tradeoff silicon area and power reduction. Since energy is only consumed when capacitance is being ...

Low-power cmos digital design with dual embedded ... - IEEE Xplore
by 57% without degrading circuit performance compared to a conventional CMOS design. Index Terms—Adaptive power-supply system, clustered voltage.

IEEE Photonics Technology - IEEE Xplore
Abstract—Due to the high beam divergence of standard laser diodes (LDs), these are not suitable for wavelength-selective feed- back without extra optical ...

wright layout - IEEE Xplore
tive specifications for voice over asynchronous transfer mode (VoATM) [2], voice over IP. (VoIP), and voice over frame relay (VoFR) [3]. Much has been written ...

Device Ensembles - IEEE Xplore
Dec 2, 2004 - time, the computer and consumer electronics indus- tries are defining ... tered on data synchronization between desktops and personal digital ...

wright layout - IEEE Xplore
ACCEPTED FROM OPEN CALL. INTRODUCTION. Two trends motivate this article: first, the growth of telecommunications industry interest in the implementation ...

Criterion for narrowband beamforming - Electronics Letters - IEEE Xplore
Introduction: When discussing adaptive array beamforming techni- ques, narrowband signal beamforming is different from wideband signal beamforming.

Evolutionary Computation, IEEE Transactions on - IEEE Xplore
search strategy to a great number of habitats and prey distributions. We propose to synthesize a similar search strategy for the massively multimodal problems of ...

I iJl! - IEEE Xplore
Email: [email protected]. Abstract: A ... consumptions are 8.3mA and 1.lmA for WCDMA mode .... 8.3mA from a 1.5V supply under WCDMA mode and.

Gigabit DSL - IEEE Xplore
(DSL) technology based on MIMO transmission methods finds that symmetric data rates of more than 1 Gbps are achievable over four twisted pairs (category 3) ...

IEEE CIS Social Media - IEEE Xplore
Feb 2, 2012 - interact (e.g., talk with microphones/ headsets, listen to presentations, ask questions, etc.) with other avatars virtu- ally located in the same ...

Grammatical evolution - Evolutionary Computation, IEEE ... - IEEE Xplore
definition are used in a genotype-to-phenotype mapping process to a program. ... evolutionary process on the actual programs, but rather on vari- able-length ...

SITAR - IEEE Xplore
SITAR: A Scalable Intrusion-Tolerant Architecture for Distributed Services. ∗. Feiyi Wang, Frank Jou. Advanced Network Research Group. MCNC. Research Triangle Park, NC. Email: {fwang2,jou}@mcnc.org. Fengmin Gong. Intrusion Detection Technology Divi

striegel layout - IEEE Xplore
tant events can occur: group dynamics, network dynamics ... network topology due to link/node failures/addi- ... article we examine various issues and solutions.

Digital Fabrication - IEEE Xplore
we use on a daily basis are created by professional design- ers, mass-produced at factories, and then transported, through a complex distribution network, to ...

Iv~~~~~~~~W - IEEE Xplore
P. Arena, L. Fortuna, G. Vagliasindi. DIEES - Dipartimento di Ingegneria Elettrica, Elettronica e dei Sistemi. Facolta di Ingegneria - Universita degli Studi di Catania. Viale A. Doria, 6. 95125 Catania, Italy [email protected]. ABSTRACT. The no

Device Ensembles - IEEE Xplore
Dec 2, 2004 - Device. Ensembles. Notebook computers, cell phones, PDAs, digital cameras, music players, handheld games, set-top boxes, camcorders, and.

Fountain codes - IEEE Xplore
7 Richardson, T., Shokrollahi, M.A., and Urbanke, R.: 'Design of capacity-approaching irregular low-density parity check codes', IEEE. Trans. Inf. Theory, 2001 ...

Multipath Matching Pursuit - IEEE Xplore
Abstract—In this paper, we propose an algorithm referred to as multipath matching pursuit (MMP) that investigates multiple promising candidates to recover ...

Privacy-Enhancing Technologies - IEEE Xplore
filling a disk with one big file as a san- ... “One Big File Is Not Enough” to ... analysis. The breadth of privacy- related topics covered at PET 2006 made it an ...

Binder MIMO Channels - IEEE Xplore
Abstract—This paper introduces a multiple-input multiple- output channel model for the characterization of a binder of telephone lines. This model is based on ...