RFIT2005 – IEEE International Workshop on Radio-Frequency Integration Technology, Nov 30–Dec 02, 2005 Singapore
Enabling Wireless Communications with
S7.2
State-of-the-Art RF CMOS and SiGe BiCMOS Technologies S. F. Chu, K. W. Chew, P. R. Verma, C. H. Ng, C. H. Cheng, N. G. Toledo, Y. K. Yoo W. B. Loh, K. C. Leong, S. Q. Zhang, B. G. Oon, Y. W. Poh, T. Zhou, K. K. Khu and S. F. Lim Device Technology Division, Chartered Semiconductor Manufacturing Ltd., 60 Wooodlands Industrial Park D, Street 2, Singapore 738406 well characterized and controlled RF parametric cells or pcells. The ability to quickly and accurately simulate device behavior of different configurations, include the process tolerances, account for parasitics in the wiring, substrate and the resulting noise influences in RF blocks will strongly influence the foundry of choice these days. This paper firstly reviews the comparison between advanced RF CMOS technologies and the more mature SiGe BiCMOS technologies. Thereafter the authors will discuss about the development of scalable and statistical models for first-pass RF designs. Following this, the broad menu of high performance passive devices will be described.
Abstract — The choice of technology for today’s mixedsignal/RF system-on-chip (SOC) designs has been driven by the performance enhancements and cost advantage derived from scaled CMOS technologies. This paper will discuss the performance improvements of RF transistors resulting from technology downscaling. Comparisons between scaled RF CMOS and SiGe BiCMOS technologies to highlight the benefits of employing SiGe HBT devices in certain applications will be made. Other technology enablements discussed include accurate, scalable models and statistical models to address the need for design flexibility and robust manufacturing. Thereafter the introduction of high Q inductors, high density capacitors and varactors as basic passive components for RF circuits will be discussed. Analog requirements such as mismatch, temperature linearity and voltage linearity will also be discussed. Index Terms — RF CMOS, SiGe BiCMOS, ft, fmax, scalable models, statistical models, inductors, MIM capacitors, VPP capacitors, MOS varactors, mismatch, linearity.
II. RF CMOS vs SiGe BiCMOS The aggressive scaling of CMOS technologies has greatly enhanced the RF performance of multi-finger transistors. Table 1 tabulates the critical performance matrix for 5 generations of RF CMOS technologies. The key figures-of-merit to quantify the RF performance of a transistor are the unity current gain frequency, ft, the unity power gain frequency, fmax, and the minimum noise figure, NFmin. The unity current gain frequency, ft is defined as the frequency where the short-circuited current gain of the device is unity. It is often used to measure the speed of the device. It is can be expressed as
I. INTRODUCTION The rapidly growing wireless standards within the 0.8GHz to 10GHz frequency span has led to a need for foundries to offer leading edge RF CMOS and SiGe BiCMOS process technologies. In the recent years, the development of cognitive radio technology and RF spectrum multiplexing has allowed for increased spectral efficiency. The resultant complexity in RF integrated circuit (RFIC) designs has in turn put greater emphasis on foundries’ actives and passives RF performance, the need for accurate scalable models that include process variations, and a comprehensive modular process design kit (PDK). A fundamental difference between digital technology development and mixed-signal/RF CMOS technology development is the sensitivity of mixed-signal/RF circuits to manufacturing process variances, as well as test structure designs resulting in device performance tradeoffs. In fact, one of the main enablements for creating a robust RF CMOS process solution is to achieve high performance,
ft =
gm 2π (Cgs + Cgd + Cgb )
(1)
where gm is the device transconductance, Cgs is the gatesource overlap capacitance, Cgd is the gate-drain overlap capacitance and Cgb is the gate-bulk capacitance.
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Table1 Key RF CMOS Transistor Performance Matrix
It can be deduced from equation (1) that ft is proportional W gate to the inverse of Lgate since gm is ∝ . Table illustrates L gate that in fact ft scales as a function of Lgate-1.2. The unity power gain frequency, fmax is defined as the power gain delivered by a device when both the input and output ports are matched to the impedance of the source and load respectively. It provides a measure on how much power gain one can achieve from a device. It can be expressed as
f max =
ft
2 gds (Rg + Rs ) + 2πftRgCgd
(2)
where Rg is the gate resistance, Rs is the source contact resistance and gds is the output conductance. Table 1 illustrates that for each generation, the NMOS transistor’s fmax is higher than ft. Since ft is directly dependent on gm, it improves with technology downscaling. However fmax has a weaker bias dependence and is approximately proportional to gm0.5. In addition it is also dependent on gds, Rg and Rs. This implies that it will not necessarily increase with each new generation. In fact careful transistor layout optimization to minimize Rg and Rs is required in each generation to attain high fmax. The high frequency noise of a CMOS transistor is characterized by the minimum noise figure, NFmin. NFmin can only be achieved when the optimum noise resistance is equal to the driving source resistance, which is typically a 50 ohms resistive termination. The minimum noise figure can be approximated as
NFmin ≅ 1 + K
f γgm Rg + Rs ft
Tech Node (nm) /Parameter
350
250
180
130 G
90 LP
Core VDD (V)
3.3
2.5
1.8
1.2
1.2
LGATE (nm)
350
240
180
120
85
NMOS ft (GHz)
27
39
60
70
140
NMOS fmax (GHz)
35
44
80
90
150
NMOS NFmin (dB)
1.9
1.6
1.4
0.5
0.3
SId/Id2*WL*COX (F/Hz)
5.0×10-26
4.0×10-25
8.0×10-25
7.0×10-24
1.4×10-22
Metal, Dielectric
4LM Al, SiO2
5LM Al, SiO2
6LM Al, SiO2
8LM Cu, FSG
9LM Cu, Low k
transistor to produce higher 1/f noise. Hence designing analog and RF circuits with deep submicrometer technologies would become more challenging due to a twopronged constraint, i.e. the reduction of the voltage headroom due to a lower supply voltage and a higher floor noise, which reduces the usable dynamic range. The effect of technology downscaling on other RF transistor’s figures-of-merit, namely device linearity and gain efficiency have been discussed in our earlier paper [1]. After years of intensive research and development, more and more analog and RF functionalities have been implemented using low-cost CMOS technologies. However for portable wireless systems where higher data speed and lower power consumption are required, designers often resort to the use of bipolar transistors. In the recent years, SiGe BiCMOS technology is gaining dominance in the BiCMOS market place due to its lower cost as compared with GaAs HBT technology, and more importantly its ability to integrate the dense digital circuitries together with the RF transceiver for system-on-chip (SOC) implementation. Figs. 1(a) and 1(b) show the comparison of ft and fmax versus the operating/breakdown voltage for 5 generations of Chartered’s RF CMOS technologies and the 0.18µm SiGe BiCMOS node. It can be concluded that at a given operating/breakdown voltage point, SiGe HBT has better ac performance than RF NFETs. It is also well known that SiGe HBTs have lower 1/f noise as compared to CMOS transistors [2]. This makes SiGe BiCMOS HBTs well suited for implementing low phase noise VCOs and baseband amplifiers in direct-conversion transceivers.
(3)
where the parameter K is a fitting factor and is less than one, and γ is a bias-dependent parameter. Table 1 reveals that NFmin decreases with technology downscaling. Equation (3) indicates that NFmin decreases as a result of the increase of ft when gate length decreases. In addition equation (3) shows that the gate resistance is one of the key parameters affecting NFmin. Hence one method to minimize NFmin is to lower Rg via the use of doubly contacted polysilicon gate layout technique. Table 1 illustrates that the 1/f noise level increases with technology scaling from 0.35µm to 90nm LP node. This trend is evident when one takes into consideration the changeover to nitrided gate oxide from 0.25µm technology and below. The increasing nitrogen incorporation near the Si/SiO2 interface with technology scaling resulted in enhanced oxide trap density. These traps, in turn, cause the
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160
160
ft_RF NFETs ft_RF NFETs Lg = 90nm
ft_NPN with DT 120
f max (GHz)
100
f t (GHz)
ft_NPN without DT
ft_NPN with and without DT
120
80
Lg = 90nm
140
140
Lg = 0.13µm
60 Lg = 0.18µm
100
0.18µm SiGe HBT
80
Lg = 0.13µm Lg = 0.18µm
60
0.18µm SiGe HBT Lg = 0.25µm
40
40 Lg = 0.25µm
20
Lg = 0.35µm
20
Lg = 0.35µm
0 0
2
4
6
8
0
10
0
2
VDD or BVceo (V)
4
Fig. 1(a). Comparison of ft versus VDD or BVceo for RF CMOS NFETs against 0.18µm SiGe BiCMOS HBTs
8
10
Fig. 1(b). Comparison of fmax versus VDD or BVceo for RF CMOS NFETs against 0.18µm SiGe BiCMOS HBTs
III. PREDICTIVE MODELING One of the important enablements for creating RF technologies is having a comprehensive and accurate set of compact models for both active and passive devices. In order to reduce the layout variances that can potentially influence the parasitic impedances, Chartered’s RF PDK employs p-cells to control the degrees of freedom of a RF device layout to a few scalable parameters. The RF models have been built to accurately reflect the allowed variations of the p-cells. Fig. 2(a) shows an example of the NFET p-cell from Chartered’s 0.13µm G technology. It illustrates the unit cell approach to achieving RF FET model scalability. The scalable parameters are the gate length, the device width and the number of fingers within a cell. Fig. 2(b) shows the high frequency scalable subcircuit RF FET model with the input gate resistor modeling the first-order non-quasi-static (NQS) effect of the channel region and the substrate resistor network modeling the high frequency parasitics associated with the body of the transistor. Fig. 2(c) shows the fitting of the scalable RF NFET model to the measured data. A close agreement between model and data can be observed.
1.0E-02
Real(Y22) (log)
Nf = 4 Vgs = 1.2V Vds = 1.2V Lf = 0.13µm Wf = 2.0µm
1.0E-03
Lf = 0.13µm Wf = 0.9µm
1.0E-04 Lf = 1.0µm Wf = 5.0µm
1.0E-05 0.1
1
10x0.13 PMOS Idsat (µA/µm)
10x0.13 PMOS Vt (V)
10x0.13 NMOS Vt (V)
D R4
100
Fig. 2(c). Fitting of 0.13µm G scalable RF NFET model vs measured data
Rg S
10
Frequency (GHz)
G
R1
6
VDD or BVceo (V)
(a)
10x0.13 NMOS Idsat (µA/µm)
(b)
R5 R2
Fig. 3. Monte Carlo simulation versus PCM data for 0.13µm G nominal transistor. Red symbols refer to monte carlo simulation and blue symbols refer to PCM data. (a) PMOS vs NMOS Vt and (b) PMOS vs NMOS Idsat
R3
B
(a) (b) Fig. 2. (a) RF NFET p-cell illustrating the unit cell approach to model scalability and (b) schematic of a high frequency scalable subcircuit RF FET model
Besides model scalability, another important device model feature is the capability to reflect process variations. Foundry device model files typically include process corners. However having the ability to simulate statistical distribution as well as proximity mismatch variations via
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Monte Carlo allows circuit designers to assess the impact of process and mismatch variations on their circuit performance. Fig. 3 shows the Monte Carlo simulation versus process control monitor (PCM) data for Chartered’s 0.13µm G technology.
offerings. Our 0.13µm G process features MIM with a capacitance density of 2fF/µm2 and a Q-factor of 200 at 2.45 GHz for a 1pF capacitor. In the recent years, vertical parallel plate (VPP) capacitors have been gaining dominance due to the increased capacitance density associated with more metal layers and tighter pitch size resulting from technology downscaling. Furthermore it comes with no additional cost. Our 0.13µm G process features VPP with a maximum capacitance density of 2.155fF/µm2 and a Q-factor of 186 at 2.45 GHz for a 1pF capacitor.
IV. PASSIVE DEVICES Besides the actives, the availability of high performance passives is also crucial to achieving aggressive RF circuit designs.
Inductors The degradation of quality factor (Q-factor) performance for on-chip inductors are mainly due to skin-effect and magnetic-field-induced proximity losses of the metal coils, capacitive and/or magnetic coupling substrate losses. Thick top metal layers coupled with metal-strapped silicided polysilicon shield have been employed to build high Q-factor inductors. Grounded silicided polysilicon shield helps to terminate electrically induced conduction and displacement currents, hence minimizing the substrate losses. A Q-factor of 13 at 5 GHz has been achieved for a 2nH symmetric octagonal inductor with a grounded faraday shield. The inductor has been implemented using a 3 µm thick top metal in a 6 Cu layer CMOS process. Chartered offers scalable inductor RF models for spiral and symmetric inductors with and without centre taps. In addition we have recently added 4-port transformers to our inductor offering to facilitate on-chip impedance matching. Fig. 4 demonstrates the RF performance of a 1:1 stacked transformer implemented in the 0.13µm G process. 10
Varactors Both accumulation-mode MOS and junction diode can be used as RF varactors without extra processing cost. MOS varactors have been offered in both the core and I/O device oxide thicknesses to provide a high capacitance density, a large tuning range and a high Q-factor. Reverse-biased junction varactors are available for applications where fine tuning of the capacitance is required. A 0.25pF 3.3V MOS varactor with a Cmax/Cmin of 2 and a Q-factor of 35 at 2.45 GHz has been achieved using the 0.13µm G process. This device is well suited for application where a small form factor and a high Q-factor are required. Polysilicon Resistors Both the unsalicided p+ polysilicon and the optional 1K Ω/ p+ polysilicon resistors are typically offered in a RFCMOS process. These resistors have a mismatch coefficient of < 1.6 %-µm and a low TCR1 of < 50 ppm/K. The 1K Ω/ p+ polysilicon resistors will require 1 additional mask.
1.0
15
0.9 10
8
0
4 -5
2
0 0.01
0.7
-10
Q
Gmax
6
V. CONCLUSION
0.8
5
L (nH)
Q-Factor
L
0.6 0.5 0.4 0.3 0.2 0.1
0.1
1
Frequency (GHz)
(a)
10
-15 100
0.0 0.01
0.1
1
10
100
Frequency (GHz)
(b)
Chartered offers flexible RF technology solutions covering both the wireless and wired design space. Each technology node offers a broad menu of high performance RF actives and passives, supported by accurate, scalable and statistical models that correlate to the p-cells. Having well characterized and controlled RF p-cells is key to achieving first-pass success RF designs. REFERENCES
Fig. 4. 1:1 stacked transformer with a coupling factor of 0.9 implemented using the 0.13µm G 6LM process. (a) Isolated mode RF performance and (b) coupled mode RF performance
[1]
[2]
MIM and VPP Capacitors Parallel plate MIM capacitors requiring only 1 additional mask have been integrated into Chartered’s RF technology
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K. W. Chew, S. –F. Chu and C. C. C. Leung, “Driving CMOS into the wireless communications arena with technology scaling,” IEEE Custom Integrated Circuits Conference, 2001, pp. 571. J. S. Dunn et. al., “Foundation of RF CMOS and SiGe BiCMOS technologies,” IBM J. Res. & Dev., vol. 47, no. 2/3, pp. 101-138, Mar/May 2003.
