Unit No: 2 ARM Processor Prepared by: Pavan R Jaiswal
Unit 2 objectives ◦ To
understand
working
of
stand
alone
and
integrated processors ◦ To understand ARM processor architecture ◦ To learn and execute ARM instruction set ◦ To learn ARM 9 and Cortex M3 architecture
◦ To learn and use BeagleBone Black
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Processor basics
ARM architecture
Interrupt vector table
ARM programming
ARM 9
Cortex M3
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Stand-Alone Processors IBM 970FX Intel Pentium M Freescale MPC7448 Companion Chipsets
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The Pentium M is based on the popular x86 architecture and thus is widely supported by a large ecosystem of hardware and software vendors. It consumes less power than other x86 processors. Advanced power-management features enable lowpower operating modes and multiple sleep modes. Dynamic clock speed capability enhances batterypowered operations such as standby. On-chip thermal monitoring enables automatic transition to lower power modes to reduce power consumption in over temperature conditions. Multiple frequency and voltage operating points (dynamically selectable) are designed to maximize battery life in portable equipment.
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The Intel Atom™ has enjoyed success in Netbooks and a range of embedded systems. The Intel Atom™ family of processors features low power consumption and binary compatibility with older 32-bit Intel processors, enabling a wide range of off-the-shelf software solutions. Like the other stand-alone processors described in this section, the Atom™ is paired with companion chipset(s) to build a complete solution. The N270 and Z5xx series of processors have been widely used in low-power products. The author’s Dell Mini 10, on which portions of this second-edition manuscript were written, contains the Intel Atom™ Z530 processor.
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Processor/chipset relationship EOS, TE Computer, VIIT
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Dual data rate (DDR) DRAM, integrated memory controller Ethernet (the Tundra provides four Gigabit Ethernet ports) PCI Express (supports two PCI Express ports) PCI/X (PCI 2.3, PCI-X, and Compact PCI [cPCI]) Serial ports I2C Programmable interrupt controller Parallel port
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Several major processor architectures exist, which has an integrated SOCs. Power Architecture is a traditional leader in many networking- and telecommunicationsrelated embedded applications, and MIPS may have the market lead in lower-end consumer-grade equipment. ARM is used in many cellular phones. These architectures, IA32/64 represent the major architectures in widespread use in embedded Linux systems.
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Power Architecture is the modern term that refers to the family of technology and products conforming to the various versions of the Power Architecture Instruction Set Architecture. Power Architecture processors have found their way into embedded products of every description. From automotive, consumer, and networking applications to the largest data and telecommunications switches, Power Architecture is one of the most popular and successful architectures for embedded applications.
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Power Architecture processors have found their way into embedded products of every description. From automotive, consumer, and networking applications to the largest data and telecommunications switches, Power Architecture is one of the most popular and successful architectures for embedded applications.
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Freescale Semiconductor has a large range of Power Architecture processors with integrated peripherals. Freescale Power Architecture processors have enjoyed enormous success in the networking market segment. Freescale PowerQUICC I Freescale PowerQUICC II PowerQUICC II Pro Freescale PowerQUICC III Freescale QorIQ™ EOS, TE Computer, VIIT
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The 440EP is a popular integrated processor found in many networking and communications products. The following list highlights some of the features of the 440EP:
On-chip dual data rate (DDR) SDRAM controller Integrated NAND Flash controller PCI bus interface Dual 10/100Mbps Ethernet ports On-chip USB 2.0 interface Up to four user-configurable serial ports Dual I2C controllers Programmable Interrupt Controller Serial Peripheral Interface (SPI) controller Programmable timers JTAG interface for debugging
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The MIPS architecture was designed in 1981 by a Stanford University engineering team led by Dr. John Hennessey, who later went on to form MIPS Computer Systems, Inc. MIPS is a Reduced Instruction Set Computing (RISC) architecture with both 32-bit and 64-bit implementations shipping in many popular products. MIPS processors are found in a large variety of products, from high-end to consumer devices. It is public knowledge that MIPS processors power many popular, well-known consumer products, such as Sony high-definition television sets, Linksys wireless access points, and the popular Sony PlayStation game console. EOS, TE Computer, VIIT
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An "embedded system" is any computer system or computing device that performs a dedicated function or is designed for use with a specific embedded software application. Embedded systems may use a ROM-based operating system or they may use a disk-based system, like a PC. But an embedded system is not usable as a commercially viable substitute for general purpose computers or devices.
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Modular Scalable Configurable Small footprint CPU support Device drivers etc
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Wind River Systems ◦ VxWorks ◦ pSOS
QNX Software Systems ◦ QNX
Green Hills Software ◦ Integrity
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Mentor Graphics ◦ VRTX
Palm Computing ◦ PalmOS
Symbian ◦ SymbianOS
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Introduction to ARM Ltd Programmers Model Instruction Set System Design Development Tools
Founded in November 1990 ◦ Spun out of Acorn Computers
Designs the ARM range of RISC processor cores Licenses ARM core designs to semiconductor partners who fabricate and sell to their customers. ◦ ARM does not fabricate silicon itself
Also develop technologies to assist with the design-in of the ARM architecture
Licencees have the right to use hard or soft views of the IP
RTL and synthesis flows GDSII layout soft views include gate level netlists hard views are DSMs
OEMs must use hard views
to protect ARM IP
Introduction to ARM Ltd Programmers Model Instruction Sets System Design Development Tools
The ARM is a 32-bit architecture.
When used in relation to the ARM: ◦ Byte means 8 bits ◦ Halfword means 16 bits (two bytes) ◦ Word means 32 bits (four bytes)
Most ARM’s implement two instruction sets ◦ 32-bit ARM Instruction Set ◦ 16-bit Thumb Instruction Set
Jazelle cores can also execute Java bytecode
The ARM has seven basic operating modes: ◦ User : unprivileged mode under which most tasks run ◦ FIQ : entered when a high priority (fast) interrupt is raised ◦ IRQ : entered when a low priority (normal) interrupt is raised
◦ Supervisor : entered on reset and when a Software Interrupt instruction is executed ◦ Abort : used to handle memory access violations
◦ Undef : used to handle undefined instructions ◦ System : privileged mode using the same registers as user mode
Current Visible Registers Abort Mode SVC Undef Mode Mode IRQ FIQ User Mode Mode
ARM has 37 registers all of which are 32-bits long. ◦ ◦ ◦ ◦
1 dedicated program counter 1 dedicated current program status register 5 dedicated saved program status registers 30 general purpose registers
The current processor mode governs which of several banks is accessible. Each mode can access
◦ a particular set of r0-r12 registers ◦ a particular r13 (the stack pointer, sp) and r14 (the link register, lr) ◦ the program counter, r15 (pc) ◦ the current program status register, cpsr
Privileged modes (except System) can also access ◦ a particular spsr (saved program status register)
31
28 27
NZCVQ f
23
J
16 15
8
U n d e f i n e d s x
Condition code flags ◦ ◦ ◦ ◦
24
N = Negative result from ALU Z = Zero result from ALU C = ALU operation Carried out V = ALU operation oVerflowed
◦ Architecture 5TEJ only ◦ J = 1: Processor in Jazelle state
5
IFT
4
0
mode c
Interrupt Disable bits.
T Bit ◦ Architecture xT only ◦ T = 0: Processor in ARM state ◦ T = 1: Processor in Thumb state
Sticky Overflow flag - Q flag
J bit
6
◦ I = 1: Disables the IRQ. ◦ F = 1: Disables the FIQ.
◦ Architecture 5TE/J only ◦ Indicates if saturation has occurred
7
Mode bits ◦ Specify the processor mode
When the processor is executing in ARM state:
When the processor is executing in Thumb state:
When the processor is executing in Jazelle state:
◦ All instructions are 32 bits wide ◦ All instructions must be word aligned ◦ Therefore the pc value is stored in bits [31:2] with bits [1:0] undefined (as instruction cannot be halfword or byte aligned).
◦ All instructions are 16 bits wide ◦ All instructions must be halfword aligned ◦ Therefore the pc value is stored in bits [31:1] with bit [0] undefined (as instruction cannot be byte aligned).
◦ All instructions are 8 bits wide ◦ Processor performs a word access to read 4 instructions at once
When an exception occurs, the ARM: ◦ Copies CPSR into SPSR_ ◦ Sets appropriate CPSR bits
FIQ 0x1C Change to ARM state IRQ 0x18 Change to exception mode (Reserved) 0x14 Disable interrupts (if appropriate) 0x10 Data Abort ◦ Stores the return address in LR_ Prefetch Abort 0x0C Software Interrupt 0x08 ◦ Sets PC to vector address Undefined Instruction 0x04 To return, exception handler needs to: Reset 0x00
◦ Restore CPSR from SPSR_ ◦ Restore PC from LR_
This can only be done in ARM
Vector table Table can be at Vector 0xFFFF0000 on state. ARM720T and on ARM9/10 family devices
1 2
Halfword and signed halfword / byte support
System 3 mode Thumb instructi Early on set ARM ARM7TD architectu MI res ARM720T
Multi-processing V6 Memory architecture (VMSA) Unaligned data support
ARM1136E J-S
Introduction to ARM Ltd Programmers Model Instruction Sets System Design Development Tools
ARM instructions can be made to execute conditionally by postfixing them with the appropriate condition code field.
◦ This improves code density and performance by reducing the number of forward branch instructions. CMP BEQ ADD skip
r3,#0 skip r0,r1,r2
CMP r3,#0 ADDNE r0,r1,r2
By default, data processing instructions do not affect the condition code flags but the flags can be optionally set by using “S”. CMP does not need “S”. decrement r1 and set flags loop … SUBS r1,r1,#1 BNE loop
if Z flag clear then branch
The possible condition codes are listed below: Suffix Description Flags tested EQ NE CS/HS CC/LO MI PL VS VC HI LS GE LT GT LE AL
Equal Z=1 Not equal Z=0 Unsigned higher or same C=1 Unsigned lower C=0 Minus N=1 Positive or Zero N=0 Overflow V=1 No overflow V=0 Unsigned higher C=1 & Z=0 Unsigned lower or sameC=0 or Z=1 Greater or equal N=V Less than N!=V Greater than Z=0 & N=V Less than or equal Z=1 or N=!V Always
Use a sequence of several conditional instructions if (a==0) func(1);
CMP MOVEQ BLEQ
r0,#0 r0,#1 func
Set the flags, then use various condition codes if (a==0) x=0; if (a>0) x=1;
CMP MOVEQ MOVGT
r0,#0 r1,#0 r1,#1
Use conditional compare instructions if (a==4 || a==10) x=0;
CMP CMPNE MOVEQ
r0,#4 r0,#10 r1,#0
Branch : B{} label Branch with Link : BL{} subroutine_label 31
28 27
Cond
25 24 23
0
1 0 1 L
Offset
Link bit
0 = Branch 1 = Branch with link
Condition field
The processor core shifts the offset field left by 2 positions, sign-extends it and adds it to the PC ◦ ± 32 Mbyte range ◦ How to perform longer branches?
Consist of :
◦ Arithmetic: RSC
◦ Logical: ◦ Comparisons: ◦ Data movement:
AND CMP MOV
ADD
ADC
SUB
ORR CMN MVN
EOR TST
BIC TEQ
SBC
RSB
These instructions only work on registers, NOT memory.
Syntax: {}{S} Rd, Rn, Operand2
Comparisons set flags only - they do not specify Rd Data movement does not specify Rn
Second operand is sent to the ALU via barrel shifter.
LSL : Logical Left Shift CF
Destination
ASR: Arithmetic Right Shift 0
Multiplication by a power of 2 LSR : Logical Shift Right ...0
Destination
CF
Division by a power of 2
Destination
Division by a power of 2, preserving the sign bit ROR: Rotate Right Destination
CF
Bit rotate with wrap around from LSB to MSB
RRX: Rotate Right Extended Destination
CF
CF
Single bit rotate with wrap around from CF to MSB
Operand 1
Operand 2
Barrel Shifter
Register, optionally with shift operation
◦ Shift value can be either be: 5 bit unsigned integer Specified in bottom byte of another register.
◦ Used for multiplication by constant
Immediate value
◦ 8 bit number, with a range of 0-255.
ALU
Result
Rotated right through even number of positions
◦ Allows increased range of 32bit constants to be loaded directly into registers
No ARM instruction can contain a 32 bit immediate constant ◦ All ARM instructions are fixed as 32 bits long
The data processing instruction format has 12 bits available for operand2 11
8 7 rot
x2
0 immed_8
Shifter ROR
Quick Quiz:
0xe3a004ff MOV r0, #???
4 bit rotate value (0-15) is multiplied by two to give range 0-30 in steps of 2 Rule to remember is “8-bits shifted by an even number of bit positions”.
Examples: 31
ror #0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ror #30 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0
range 0-0xff000000 step 0x01000000 range 0-0x000003fc step 0x00000004
The assembler converts immediate values to the rotate form: ◦ ◦
range 0-0x000000ff step 0x00000001
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ror #8
0
MOV r0,#4096 ADD r1,r2,#0xFF0000
; uses 0x40 ror 26 ; uses 0xFF ror 16
The bitwise complements can also be formed using MVN: ◦
MOV r0, #0xFFFFFFFF
; assembles to MVN r0,#0
Values that cannot be generated in this way will cause an error.
To allow larger constants to be loaded, the assembler offers a pseudo-instruction: ◦ LDR rd, =const
This will either:
◦ Produce a MOV or MVN instruction to generate the value (if possible).
or
◦ Generate a LDR instruction with a PC-relative address to read the constant from a literal pool (Constant data area embedded in the code).
2-5 cycles on ARM7TDMI 1-3 cycles on StrongARM/XScale 2 cycles on ARM9E/ARM102xE
◦ +1 cycle for ARM9TDMI (over ARM7TDMI) ◦ +1 cycle for accumulate (not on 9E though result delay is one cycle longer) ◦ +1 cycle for “long”
Above are “general rules” - refer to the TRM for the core you are using for the exact details
LDR LDRB LDRH LDRSB LDRSH
STR STRB STRH
Word Byte Halfword Signed byte load Signed halfword load
Memory system must support all access sizes
Syntax:
◦ LDR{}{} Rd, ◦ STR{}{} Rd, e.g. LDREQB
Address accessed by LDR/STR is specified by a base register plus an offset For word and unsigned byte accesses, offset can be ◦ An unsigned 12-bit immediate value (ie 0 - 4095 bytes). LDR r0,[r1,#8]
◦ A register, optionally shifted by an immediate value LDR r0,[r1,r2] LDR r0,[r1,r2,LSL#2]
This can be either added or subtracted from the base register: LDR r0,[r1,#-8] LDR r0,[r1,-r2] LDR r0,[r1,-r2,LSL#2]
For halfword and signed halfword / byte, offset can be: ◦ An unsigned 8 bit immediate value (ie 0-255 bytes). ◦ A register (unshifted).
Choice of pre-indexed or post-indexed addressing
Pre-indexed:
STR r0,[r1,#12] r0
Offset 12
0x20c
0x5
0x5
Source Register for STR
r1 Base Register
0x200
0x200
Auto-update form: STR r0,[r1,#12]!
Post-indexed: STR r0,[r1],#12 Updated Base Register
Original Base Register
r1
Offset
0x20c
12
0x20c
r0 0x5
r1 0x200
0x200
0x5
Source Register for STR
Syntax:
{}
4 addressing modes: LDMIA LDMIB LDMDA LDMDB
/ / / /
STMIA STMIB STMDA STMDB
Rb{!},
increment after increment before decrement after decrement before
LDMxx r10, {r0,r1,r4} STMxx r10, {r0,r1,r4} Base Register (Rb) r10
IA r4 r1 r0
IB
DA
DB
r4 r1 r0 r4 r1 r0
Increasing Address
r4 r1 r0
31
28 27
Cond
0
24 23
1 1 1 1
SWI number (ignored by processor)
Condition Field
Causes an exception trap to the SWI hardware vector The SWI handler can examine the SWI number to decide what operation has been requested. By using the SWI mechanism, an operating system can implement a set of privileged operations which applications running in user mode can request. Syntax: ◦
SWI{}
31
28 27
NZCVQ f
24
J
23
16 15
8
U n d e f i n e d s x
7
6
5
4
IFT
0
mode c
MRS and MSR allow contents of CPSR / SPSR to be transferred to / from a general purpose register. Syntax: ◦ ◦
MRS{} Rd,
; Rd =
MSR{} ,Rm ; = Rm
where
◦ = CPSR or SPSR ◦ [_fields] = any combination of ‘fsxc’
Also an immediate form ◦
MSR{} ,#Immediate
In User Mode, all bits can be read but only the condition flags (_f) can be written.
integrated processors. ⦠To understand ARM processor architecture. ⦠To learn and execute ARM instruction set. ⦠To learn ARM 9 and Cortex M3 architecture.
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