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Journal of Circuits, Systems, and Computers Vol. 18, No. 4 (2009) 787–800 c World Scientific Publishing Company


EXPLORATION OF POWER-DELAY TRADE-OFFS WITH HETEROGENEOUS ADDERS BY INTEGER LINEAR PROGRAMMING

SANGHOON KWAK Department of Information and Communications, Gwangju Institute of Science and Technology, 1 Oryong-dong Buk-gu, Gwangju, 500-712, Republic of Korea [email protected] JEONG-GUN LEE Department of Computer Engineering, Hallym University, 39 Hallymdaehak-gil, Chuncheon, Gangwon-do, 200-702, Republic of Korea [email protected] EUN-GU JUNG The Attached Institute of ETRI, 909 Jeonmin-dong, Yuseong-gu, Daejeon, 305-390, Republic of Korea [email protected] DONGSOO HAR Department of Information and Communications, Gwangju Institute of Science and Technology, 1 Oryong-dong Buk-gu, Gwangju, 500-712, Republic of Korea [email protected] MILOS D. ERCEGOVAC Department of Computer Science, University of California Los Angeles, 473 Boelter Hall, Los Angeles, 90095, USA [email protected] JEONG-A LEE Department of Computer Engineering, Chosun University, 375 Seosuk-dong Dong-gu, Gwangju, 501-759, Republic of Korea [email protected] Revised 22 February 2009

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S. Kwak et al. The performance of arithmetic adders varies widely in their power consumption, delay, and area requirements. To acquire more fine-grained trade-offs in the power-delay tradeoff curve of a binary adder, the heterogeneous adder architecture is adopted. In heterogeneous adder architecture, a binary adder is decomposed into sub-adder blocks with different carry propagation schemes and bit-widths. Thus the method allows us to expand the original design space of a specific type of adder into the more fine-grained design space by mixing that of each sub-adder. In this paper, a design for heterogeneous adder through power optimization under delay constraints or delay optimization under power constraints was presented by determining the bit-width of each sub-adder. Also the effectiveness of the proposed method was demonstrated by showing the ratio of the power consumption of heterogeneous adder to that of conventional adder. Keywords: Heterogeneous adder; integer linear programming; power-delay trade-off.

1. Introduction The heterogeneous adder can be described as an adder in which various type of carry propagation adders, such as ripple carry adder (RCA), carry skip adder (CSKA) and carry look-ahead adder (CLA), are concatenated using the carry-in and carryout signals of these component adders.1, 2 Therefore, for an implementation of n-bit adder, each bit-width of component adders can be adjusted for optimum design. In this paper, an architecture of heterogeneous adders is extended, permitting design trade-offs with power and delay. The proposed method can also be used for area related design optimization. An integer linear programming (ILP) based methodology is applied to configure heterogeneous adders. The ILP provides the best type and bit-width of sub-adders for two applications; (i) power-constrained delay optimization and (ii) delay-constrained power optimization. Compared to previous works,3–5 the proposed approach provides a higher level view of arithmetic optimization without considering low-level circuit design issues such as fanout size and wiring complexity. Also, it facilitates a more systematic optimization method through mathematically modeled delay and power. Commercial CAD tools such as Synopsys Design Compiler perform an optimization for a conventional adder by selecting a specific type of adder from the design library6 and gate-level optimization is conducted to meet the given design constraints. However, the optimization of heterogeneous adders is performed in the mixed design space composed of heterogeneous bit level component adders, so it provides more flexibility by allowing us to acquire the power or the delay data from various sources such as gate-level design, layout design, and numerical estimation. This paper is organized as follows. The architecture of heterogeneous adders and their characteristics are explained in details in Sec. 2. In Sec. 3, we will explain the mathematical modeling and optimization of the heterogeneous adders. Experimental results are presented in Sec. 4 to show the efficiency of the proposed method. Finally, conclusions are drawn in Sec. 5. 2. Heterogeneous Adders The conventional adder implementation for a specified bit-width is done via a selection of a single type of adder in a given library. Consider Fig. 1 showing the delay

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(a)

(b) Fig. 1.

Variations of (a) delay and (b) power consumption with three different types of adders.

and the power of three different types of adders synthesized by Synopsys tools with 0.18 µm CMOS library.9 Delay variation for a given type of adder with a given bitwidth is due to synthesis or circuit optimization. It is seen that for a given bit-width the delay of RCA is the largest followed by those of CSKA and CLA, whereas the power consumption of RCA is the smallest following those of CSKA and CLA.

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n3 Cout

n3

n2

SA3 = Ripple Carry Cin Sub-adder

Cout

Cout

n2 SA2 = Carry Skip Sub-adder

n

n1

Cin

Cout

n1 SA1 = Carry Lookahead Sub-adder

n

n n

MSB

n

Cin Cin

n

D

CLA n1,c

LSB

CSKA

D n2,c

CLA

D n1,s

CSKA

RCA

D n2,s

D n3,c

RCA

D n3,s

time Carry propagation time Sum propagation time Fig. 2.

Delay modeling of a heterogeneous adder.

The implementation of a heterogeneous adder is done by combining different types of component sub-adders with various bit-widths. Figure 2 shows an example of an architecture for heterogeneous adders. The heterogeneous adder shown in Fig. 2 consists of CLA, CSKA, and RCA with variable bit-width for each sub-adder. Figure 2 suggests that the overall delay or power consumption be a combination of individual delay or power consumption of different type of sub-adder. For example, when bit-width = 96, the range of overall delay or power consumption with heterogeneous adders is determined by the individual bit-width allocation to each type of sub-adder. Let a S ub Adder SAi (ni ) be an ni -bit sub-adder whose carry propagating scheme is denoted by SAi . When the number of available sub-adders is I, an n-bit heterogeneous adder is defined as an n-bit adder which concatenates SAi (ni ) where 1 ≤ i ≤ I and 0 ≤ ni ≤ n. SAi (ni ) uses the carry-out signal of SAi−1 (ni−1 ) as its carry-in signal. The sum of ni for all SAi (i = 1, . . . , I) should be equal to n. The bit-level implementations of such heterogeneous adders enable extended design space exploration, allowing more fine-grained power-delay trade-offs.

3. Optimization by ILP 3.1. Introduction to ILP Many problems can be modeled as maximizing or minimizing an objective, with the given limited resources and forcing constraints. When the objective function can be defined as a linear function of integer variables, “integer linear programming”

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is acquired from the formulation. The standard form of integer linear programming is defined as follows.7 Definition 1. (Integer Linear Programming) maximize

cT x

subject to Ax ≤ b for x ≥ 0 for

(1)

In the above equations, A is an m × n matrix with its elements aij (1 ≤ i ≤ m, 1 ≤ j ≤ n), m-dimensional vector b = [bi ] (1 ≤ i ≤ m), n-dimensional vector c = [cj ] (1 ≤ j ≤ n), and n-dimensional vector x = [xj ] (1 ≤ j ≤ n; xj ∈ set of integers). In Eq. (1), cT x is the inner product of two vectors, cT and x. In Eq. (1), Ax is a matrix-vector product. ILP has a variety of applications especially in computer-aided design area such as scheduling, resource allocation, covering, and matching8 and numerous algorithms to solve ILP have been introduced already. Thus, once we succeed in formulating of a target problem in ILP form, the problem can be solved by available linear program solver such as “CPLEX”, “lp solve”, etc. Example 1. (Application of ILP to the knapsack problem) Let us consider a popular “knapsack problem” for ILP formulation. In Table 1, the object to be put in a knapsack, its value, and its capacity are represented. With the given capacity of the knapsack as 17, we want to maximize the total weight of objects to be placed in the knapsack. Finding the number of object to be put in the knapsack under the given condition can be formulated by ILP. From Definition 1, c = [5 3 2 2 1], A = [4 7 3 5 4], x = [x1 x2 x3 x4 x5 ], and b = 17. Here the variable xj indicates the number of object to be put in the knapsack and takes only integer value larger than 0. Thus, the acquired ILP formulation for the above knapsack problem is as follows: maximize

5x1 + 3x2 + 2x3 + 2x4 + x5 subject to

4x1 + 7x2 + 3x3 + 5x4 + 4x4 ≤ 17 x ≥ 0 for j = 1, 2, . . . , 5 .

(2)

Table 1. Volume and weight of object for the knapsack problem. Object

1

2

3

4

5

Volume Weight

4 5

7 3

3 2

5 2

4 1

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3.2. Problem formulation With a given order of I types of sub-adders, seeking a solution of delay-constrained power optimization problem is equivalent to “finding each bit-width ni for subadder SAi to minimize the power of the n-bit heterogeneous adder, while satisfying a constraint that the total delay should be less than θdelay ”, where θdelay denotes the upper bound of the total delay allowed for the heterogeneous adder. In case of power-constrained delay optimization problem, delay is minimized under power constraints. 3.3. ILP formulation A delay-constrained power optimization can be described by the following expressions: arg

min POWER (Heterogeneous Adder)

(n1 ,n2 ,...,nI )

under constraints 1 : DELAY (Heterogeneous Adder) ≤ θdelay 2 : n1 + n2 +, . . . , +nI = n .

(3)

In the foregoing expressions, the “POWER”, “DELAY” are functions returning average power consumption and delay, respectively. The functions “POWER” and “DELAY” are expressed by linear combination of variables in order to use ILP10 for finding an optimal solution. The function “POWER” is expressed as follows: POWER (Heterogeneous Adder) =

I


POWER (ith type Sub-Adder) .

(4)

i=1

As mentioned previously, the order of sub-adder types of heterogeneous adders is assumed as shown in Fig. 2, and I(= 3) different types of sub-adders SAi , 1 ≤ i ≤ 3 are placed from the least significant bit (LSB) to the most significant bit (MSB). • Power Modeling: For ith type of sub-adder, POWER (SAi ) can be expressed as follows: n
ni =0

i SAi PnSA xni , i

subject to

n
ni =0

i xSA ni ≤ 1 ,

(5)

i i where PnSA is the power consumption of ith type sub-adder and xSA is a binary n i i i integer variable taking values of “0” or “1”. The inequality constraint nni =0 xSA ni ≤ 1 means at most one bit-width is selected for each type of sub-adder. Through i will take value “1” for each type of suboptimization, one integer variable xSA ni adder, indicating the architecture of heterogeneous adder. For instance, when an optimal heterogeneous adder takes a configuration of RCA for n3 = 64, CSKA for

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SA2 SA1 3 n2 = 32 bits, and CLA for n1 = 32, xSA will takes values of “1”, 64 , x32 , and x32 SAi and other xni s take values of “0”.

• Delay Modeling: The overall DELAY of a heterogeneous adder is the maximum propagation delay via several possible data propagation paths from the input. It for ni -th bit position of CLA is seen that in Fig. 2 that the delay of sum DnCLA i ,s for the same bit position. The difference is larger than the delay of carry DnCLA ,c i between the delay of sum and the delay of carry is the largest with CLA, smaller with CSKA, and the smallest with RCA. The delay of sum is always larger than the delay of carry for a given bit position of a sub-adder. With a heterogeneous adder of a given configuration as shown in Fig. 2, the , where the maximum delay of SA1 (n1 ), corresponding to CLA sub-adder, is DnCLA 1 ,s subscript s indicates the sum of CLA sub-adder. With the sub-adders CSKA and , DnCSKA + DnCLA }, CLA, the delay of the two combined sub-adders is max{DnCLA 1 ,s 2 ,s 1 ,c CLA where the subscript c of Dn1 ,c represents the carry of CLA sub-adder. Finally, with all the sub-adders RCA, CSKA, and CLA, the delay is given as , DnCSKA + DnCLA , DnRCA + DnCSKA + DnCLA } in Fig. 2. It is known for max{DnCLA 1 ,s 2 ,s 1 ,c 3 ,s 2 ,c 1 ,c such generalization that the delay of sum is larger than the delay of carry for each type of sub-adder. To implement delay-constrained power optimization fit for ILP, the DELAY (Heterogeneous Adder) is formulated as follows: DELAY (Heterogeneous Adder)  n
i SAi DnSA x (i = 1), = max i ,s ni ni =0

i−1


n


k=1 nk =0

subject to

n
ni =0

k SAk DnSA x k ,c nk

+

n
ni =0

 i SAi DnSA x (1 i ,s ni

< i ≤ I)

i xSA ni ≤ 1, i = 1, . . . , I.

(6)

From foregoing discussions, the detailed expressions for delay-constrained power optimization are obtained, depending on I value, as follows:  I n 

SAi SAi arg min Pni xni (n1 ,n2 ,...,nI )

i=1 ni =0

under constraints n
i SAi 1: DnSA x ≤ θdelay i ,s ni

(i = 1)

ni =0

2:

i−1
n
k=1 nk =0

k SAk DnSA x + k ,c nk

n
ni =0

i SAi DnSA x ≤ θdelay for all i (1 < i ≤ I) i ,s ni

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3:

n
ni =0

4:

i xSA ni ≤ 1 for all SAi

n I

i=1 ni =0

i ni xSA ni = n .

(7)

Similarly the power-constrained delay optimization is expressed as follows: arg (n1 ,n2 ,...,nI )

min{dmax }

under constraints n
i SAi DnSA x ≤ dmax 1: i ,s ni

(i = 1)

ni =0

2:

i−1
n
k=1 nk =0

3:

4:

5:

I
n


k SAk DnSA x + k ,c nk

i=1 ni =0

ni =0

i SAi DnSA x ≤ dmax i ,s ni

for all i (1 < i ≤ I)

i SAi PnSA xni ≤ θpower i

i=1 ni =0 n
i xSA ni ni =0 I
n


n


≤ 1 for all SAi

i ni xSA ni = n .

(8)

In the above expressions, θpower and θdelay denote the upper bound allowed for average power consumption and delay, respectively. dmax is a variable indicating the upper bound of delay and also the minimax objective, in power-constrained delay optimization. From the proposed ILP formulation for the delay-constrained power optimization, note that the following proposition is hold for an arbitrary θdelay . This is meaningful in that if we take a upper bound (θdelay or θpower ) from an implementation of a conventional adder, it can be applied to ILP optimization to find optimal configurations of the heterogeneous adder satisfying the upper bound. Proposition 1. Let CA and HA be a conventional adder (such as RCA, CSKA, and CLA, etc) and the heterogeneous adder modeled in above Eq. (8). For a specific adder CA, if θdelay is a given as a delay upper bound (given as a delay constraints) satisfying “θdelay ≥ DELAY(CA)”, then there exist an heterogeneous adder, HA, satisfying “θdelay ≥ DELAY(HA)”, while having POWER(HA) ≤ POWER(CA). Proof. Let us assume that we have a set of adders, CA1 , CA2 , . . . , CAn such that DELAY(CA1 ) ≥ DELAY(CA2 ) ≥ · · · ≥ DELAY(CAn ) and POWER(CA1 ) ≤ POWER(CAn ) ≤ · · · ≤ POWER(CAn ) for all the bit-widths. For an example, CA1 can be RCA, CA2 can be CSKA, CA3 can be CLA. Assume that we take a specific

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adder CAi and we have a given upper delay bound, θdelay , for the adder CAi . In this case, θdelay can be expressed in DELAY(CAi ) + δ where δ is a positive or zero number indicating some marginal delay. Then, simply by finding a heterogeneous adder, HA, using only the CAi , the θdelay can be applied to HA trivially, which satisfies θdelay ≥ DELAY(HA) = DELAY(CAi ). Now we can take CAj such that j < i (thus, DELAY(CAj ) ≥ DELAY(CAi ) and POWER(CAj ) ≤ POWER(CAi )) to make a heterogeneous adder by combining CAj and CAi . Using the marginal delay, we can increase DELAY(HA) by combining CAi with a slower adder component CAj on a heterogeneous adder with a proper bit-width assignment of those adders. The bit-width of CAj can be selected to meet the condition “θdelay ≥ DELAY(HA)”. The increased delay, which is less than δ, leads to decreased power consumption since POWER(CAj ) ≤ POWER(CAi ). Without loss of generality, the proposition can be rewritten with θpower instead of θdelay with little modification. 4. Experiments The three types of sub-adders RCA, CSKA, and CLA were considered for the experiment of power-delay optimization of four bit-widths of heterogeneous adders. Possible bit-widths of sub-adders are in the range of bit-widths from 2 to 128 bits, since 2 bits are minimum bit-width to distinguish each sub-adder type. The i i i , DnSA , and PnSA were acquired from synthesized delay and power estimates DnSA i ,s i ,c i designs using Synopsys with 0.18 µm CMOS technology.9 The ILP optimization was performed using an LP solver called “lp solve”.10 The ILP solver produced the sub-adder concatenations of RCA, CSKA, and CLA (the symbol “” denotes a concatenation between adjacent sub-adders). For example, in the case of RCA  CSKA  CLA, a CLA was located from the LSB and CSKA was used in the middle part, and RCA was located up to the MSB. In Fig. 3, the heterogeneous adder architecture obtained by “lp solve” is shown for the power-constrained and delay-constrained optimization of the four bit-widths of heterogeneous adders. Figures 3(a), 3(c), 3(e), 3(g) display power-constrained delay optimization results for the heterogeneous adders with the bit-widths of 128bit, 96-bit, 64-bit, and 32-bit. The delay-constrained power optimization results of 128-bit, 96-bit, 64-bit, and 32-bit heterogeneous adders are depicted in Figs. 3(b), 3(d), 3(f), and 3(h), respectively. With changing θdelay (or θpower ) upper bound, the optimal heterogeneous adder configurations are found. Several configurations of the optimized heterogeneous adder are indicated in Fig. 3(a). For instance, RCA97  CSKA31 (17.00/1600) obtained as the result of domination indicates that the optimal delay of the heterogeneous adder is 17.00 ns when θpower = 1600 µW with 97 bits of RCA and 31 bits of CSKA. In these figures, the two values in parentheses are “delay” and “θpower ” pairs or “θdelay ” and “power” of the corresponding heterogeneous adders.

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(a)

(b)

(c)

(d)

(e)

(f)

Fig. 3. Results of optimizations to get configurations of heterogeneous adders through: (a) 128-bit power-constrained delay optimization (b) 128-bit delay-constrained power optimization (c) 96-bit power-constrained delay optimization (d) 96-bit delay-constrained power optimization (e) 64-bit power-constrained delay optimization (f) 64-bit delay-constrained power optimization (g) 32-bit power-constrained delay optimization (h) 32-bit delay-constrained power optimization.

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(g)

797

(h) Fig. 3.

(Continued)

The design space covered by RCA  CSKA  CLA in Fig. 3 contains solutions with the various configurations of RCA, CSKA, and CLA. In Fig. 3(a), it is observed that RCA can be solely used to get optimized delay with tight upper bound θpower (θpower = 1490 µW), as expected from Fig. 1. As θpower increases, the configuration of RCA  CSKA becomes the optimal architecture of the heterogeneous adder due to their relative superiority in consequent power consumption to CSKA. With the maximum θpower (= 3240 µW) used for ILP, the CLA must be used to get small delay with relaxed power consumption constraints. In the middle range of θpower , a combination of RCA, CSKA, and CLA is used to acquire the configurations of the optimized heterogeneous adder. As indicated in Fig. 3(a), RCA  CSKA is a good candidate ordering for replacing CSKA and RCA  CSKA  CLA, RCA  CLA are good candidate orderings for replacing CLA in power-constrained delay optimization. It is found that RCA2  CSKA126 (i.e., RCA is used for MSB and the CSKA is adopted for the remaining 126 bits) is the optimal configuration for the range of 1980 ≤ θpower < 2320. Figure 3(b) corresponding to delay-constrained power optimization illustrates similar configurations of the heterogeneous adder. Above explanation about the 128bit heterogeneous adder configuration is also applied to Figs. 3(c)–3(h) for the other bit-widths of the heterogeneous adders except that the RCA  CSKA  CLA does not appear in Fig. 3(g), i.e., the power-constrained delay optimization of 32bit heterogeneous adder. This is due to that of the heterogeneous design space RCA  CSKA  CLA being absorbed into RCA  CLA since the compromised design space of RCA  CSKA cannot replace that of RCA for a short bit-width such as 32. Therefore, the optimal configuration of the heterogeneous adder can be obtained by either power-constrained delay optimization or delay-constrained power-optimization through ILP formulation and “lp solve”. The bit-width of each sub-adder shown in Fig. 3 explains clearly that heterogeneous adder indeed allows power-delay trade-offs much better than the conventional

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(a)

(b) Fig. 4. Delay/power and power/delay reduction rate by 32-bit, 64-bit, 96-bit, and 128-bit heterogeneous adder: (a) Delay reduction (b) Power reduction.

adder design. The solutions with RCA  CSKA, RCA  CSKA  CLA, and RCA  CLA are newly introduced design points. These newly introduced pareto-optimal points cannot be obtained without using heterogeneous adder architecture. Figure 4 shows the delay and the power reduction in percentage. The reduction of delay and power is calculated with respect to the delay and the power of a conventional adder matched to θpower or θdelay . For example, in case of RCA  CSKA for delay optimization, the component adder RCA incurring the larger delay while satisfying the power upper bound, is used as the 128-bit, 96-bit, 64-bit, and 32-bit adder to compute the reference delay.

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Exploration of Power-Delay Trade-Offs with Heterogeneous Adders by ILP Table 2.

799

Maximum running time of “lp solve” for the ILP optimizations. Bit-width

128

96

64

32

Delay-constrained power optimization

# of “lp solve” running Maximum running time (second)

174 3.01

124 0.89

78 0.28

32 0.03

Power-constrained delay optimization

# of “lp solve” running Maximum optimization time (second)

176 2.45

132 0.88

90 0.26

47 0.04

In Fig. 4(a), DR4MAX , DR3MAX , DR2MAX , and DR1MAX denote the maximum delay reduction of the heterogeneous adders with their bit-width, 128, 96, 64, and 32, respectively. It is observed that around 68% of DR4MAX , when θpower = 3200 µW, is achieved by RCA  CSKA configuration. As the bit-width becomes smaller, the DRiMAX also gets lower, with DR1MAX ≈ 54%. However, it is noteworthy that the difference among the power reductions of the four bit-widths of heterogeneous adders is negligible because the differences between each other are smaller than 1%. The power reduction of the four bit-widths of heterogeneous adders, P RMAX is around 40%. Finally, Table 2 shows the maximum running time of “lp solve” from the optimizations with the whole range of upper bounds. “lp solve” ran once for each ILP optimization with a specific θdelay or θpower and its running time depended on the upper bound for each ILP optimization. The experiments were performed by Intel Pentium 2.4 GHz CPU with Linux OS. For example, the maximum running time of “lp solve” for 128-bit delay-constrained power optimizations is 3.04 s, for the 174 runs of “lp solve”. These results show the high efficiency of the proposed method even for considerably large bit-width such as 128. The experimental results in Fig. 3 present the delay-constrained power optimization of the various bit-width of heterogeneous adders, or vice-versa. Also the reduction of power when compared to the case of using conventional adder and the running time of “lp solve” for an ILP formulation promises the feasibility of the proposed method for real applications. As shown in Fig. 4, the delay reduction increases as the bit-width of the heterogeneous adder becomes larger, whereas the power reduction according to the different bit-width of the heterogeneous adder, is almost identical.

5. Conclusions For designing power-delay efficient adders, the idea of a heterogeneous adder architecture is adopted and the ILP formulation of power and delay for the heterogeneous adder is introduced in this paper. Considering four bit-widths of adders (128, 96, 64, and 32), it is shown that multiple solutions for configurations of the heterogeneous adder were found by ILP. In comparison with conventional and homogeneous adders, the heterogeneous adders are more useful in that significant delay reduction and power consumption reduction can be achieved with a small optimization time.

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Acknowledgment This work has been supported in part by the Center for Distributed Sensor Network (CDSN) in GIST and in part by the Regional Innovation Program funded from Ministry of Knowledge Economy and in part by 2004 research funds from Chosun University. References 1. J.-G. Lee, J.-A. Lee, B.-S. Lee and M. D. Ergcegovac, A design method for heterogeneous adders, Proc. Int. Conf. Embedded Software and Systems, Lecture Notes in Computer Science, June 2007. 2. S. Kwak, D. Har, J.-G. Lee and J.-A. Lee, Design of hetereogeneous adders based on power-delay tradeoffs, Proc. IEEE Symp. Embedded Computing, October 2008, pp. 223–226. 3. Y. Wang, C. Pai and X. Song, The design of hybrid carry-lookahead/carry-select adders, IEEE Trans. Circuits Syst.-II: Analog Digit. Signal Process., Vol. 49, January 2002. 4. V. Oklobdzija, B. Zeydel, S. Mathew and R. Krishnamurthy, Energy-delay estimation technique for high-performance microprocessor VLSI adders, Proc. IEEE Symp. Computer Arithmetic, June 2003, pp. 272–279. 5. S. Knowles, A family of adders, Proc. IEEE Symp. Computer Arithmetic, June 2001, pp. 277–281. 6. Synopsys Corporation, DesignWare IP Family Reference Guide, September, 2005. 7. C. H. Papadimitriou and K. Steiglitz, Combinatorial Optimization: Algorithms and Complexity (Dover Publications, 1998). 8. G. De Micheli, Synthesis and Optimization of Digital Circuits (McGraw-Hill Inc, 1994). 9. Synopsys Corporation, Datasheet: ANAM 0.18 micron, 1.8 volt Optimum Silicon SC Library, August 2002. 10. M. Berkelaar, lp solve — Version 4.0, Eindhoven University of Technology, ftp://ftp.ics.ele.tue.nl/pub/lp solve/ (2003).