Advanced Gate Stacks with Fully Silicided (FUSI) Gates and High-K Dielectrics: Enhanced Performance at Reduced Gate Leakage E.P. Gusev', C. Cabral, Jr., B.P. Linder, Y.H. Kim, K. Maitra, E. Cartier, H. Nayfeh', R. Amos', G. Biery, N. Bojarczuk, A. Callegari, R. Carruthers, S.A. Cohen, M. Copel, S. Fang*, M.Frank, S. Guha, M. Gribelyuk, P. Jamison, R. Jammy, M. leong, J. Kedzierski, P. Kozlowski, V. Ku*, D. Lacey, D. LaTulipe, V. Narayanan, H. Ng',P. Nguyen', J. Newbury, V. Paruchuri, R. Rengarajan', G. Shahidi, A. Steegen', M. Steen, S. Zafar, and Y . Zhang IBM Semiconductor Research and Development Center (SRDC), IBM T.J. Watson Research Center, Yorktown Heights, NY 10598, USA 'IBM Microelectronic Division, Hopewell Junction, NY 12533, USA 'phone +I-914-945-1 168; fax +I-914-945-2141;
[email protected] Abstract
Experimental
The key result in this work is that FUSI/HRi,O, gate stacks offer both significant gate leakage reduction (due to high-x) and drive current improvement at T,, 2 nm (due to: (i) elimination of poly depletion effect, 0.5 nm, and (ii) the high mobility of HfSi,O,). We also demonstrate that threshold voltage for both PFETs and NFETs can he adjusted from midgap to the values of Vt(PFET)- -0.4 V and Vt(NFET) + 0.3 V by poly-Si predoping by implantation (AI or As) and FUSI alloying. Significantly improved charge trapping (V, stability) was found in the case of Nisi/ HfSi,O, compared to the same gate electrode with HfQ dielectric.
F U W high-K devices (0.3-100 pm) were fabricated based on the modified integration scheme described elsewhere.[ 1,3] Key process steps included (i) device isolation and well formation; (ii) gate stack formation; (iii) thin (50 nm) poly-Si deposition (that was either predoped or undoped); (iv) extensions and source/drain VI; (v) hightemperature (up to 1000 C) activation anneal; and (vi) FUSI gate formation (Fig.1). Nisi (or NiPtSi alloy) was used as a low-temperature FUSI process with temperature window in the 350-550°C range. The gate stack module consists o f ultrathin (2-4 nm) HfOl or HfSi,O, high-k dielectric deposited by MOCVD on sub-nm SO,, SiO,N,, or SiN, interfaces. Control SiOl and SiOxN, gate oxides (1.5 - 4 nm) were grown by rapid thermal oxidation. PolySL4Iigh-K and metal-gatehigh-K gate stacks were also fabricated fo; comparision, using integration schemes reported previously [7,8]
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Introduction Advanced high-performance (HP) CMOS devices require both aggressively scaled T,,, (below 2 nm) for performance gain and reduced gate leakage currents for lower power consumption. While poly-SU high-r stacks consistently exhibit significant gate leakage reduction, their scaling to below T,"" 1.5 nm appears to be very challenging. Metal gateihigh-x is an attractive candidate to meet HP technology targets due to elimination of the polydepletion effect (- 0.3-0.5 A) and an option of lower thermal budget processing. However, band edge P+ and N+ metals for CMOS and their integration is an enormous challenge. On the other hand, FUSI gates offer an attractive "metal" gate altemative due to relative simplicity of the integration process.[l-6] We demonstrated that V, tailoring as much as -400 meV (NFETs) and +200 meV (PFETs) from the mid-gap undoped FUSI value could be obtained by predoping with Sb, As, P ion implant (for NFETs) and B and AI VIS (for PFETs) in the case of FUSI on conventional SiOz gate dielectrics.[l,3] It is the purpose o f this paper to demonstrate s u b 4 nm (TI.") FUSU high-x NFET and PFET devices with significantly reduced gate leakage, high drive current and V, control.
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Results and Discussion As can be seen from Fig. 2, FUSI gates show a "metal"-like behavior (due to complete silicidation) with no signature of poly-depletion for both high-r and SiOl control gates. Both accumulation and inversion capacitances are equal. Undoped Nisi gates show a midgap work function, as expected. The gain of Tin, due to the FUSI process is approximately 0.5 nm, especially over the poly-sihigb-r devices without poly pre-doping.(Fig.3) The combination of poly-depletion elimination and high permittivity of the high-x layers results in very significant (6 to 7 orders of magnitude) gate leakage current reduction, plotted against Ti,, (Fig.4). As stated above, threshold voltage control (especially for low-Vt HP devices) is a challenge for both metal gate (band-edge metals) and poly-Sihigh-r devices (PFET Vt problem). With the help of poly-Si predoping (As I/I for NFETs and AI I/I for PFETs), we demonstrate (Figs. 5 and 6) that V, can he adjusted within 150 meV (PFET) and
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300 meV (NFET) from the mid-gap value of the undoped Nisi, in agreement with previous findings [1,3]. Alloying Ni with Pt before silicidation also helps to further lower PFET Vt by another -150-200 meV [3]. In terms of performance, FUSI/ HfSi,O, devices show carrier mobilities close to that of the SiO, control (Fig.7). This fact combined with reduced Ti., results in significant drive improvements. F i g 3 shows (over)drive current in the linear regime as a function of gate leakage. The upper Xaxis also shows equivalent gate oxide thickness extracted from gate current density assuming SiO, tunneling behavior. At a given gate leakage, the NFET performance gain is 25% for Nisi/ HfSi,O, and 15% for NiSiiSiO,. Another way to interpret the data shown in Fig. 8, is that, for a given drive current (equivalent of 1 nm Si02 gate dielectric), NiSiiHfSi,O, shows 6 orders of magnitude lower gate leakage. Charge (electron) trapping is a well-known phenomenon and a serious reliability concern in highK based devices.[7,9] It causes Vt instabilities and drive current degradation. We evaluated charge trapping using constant stress voltage technique.[7] Similarly to the polySimigh-K stacks, while FUSI on HfO, shows significant charge trapping causing Vt instability charge trapping in both doped and undoped FUSI on’HfSi,O, is negligible (Fig. 9), consistent with the poly:Si case [9,10]. This important observation is complimented by charge pumping measurements showing bulk trapping for NiSiiHfO, (Fig. IO) and low density of interface states for FUSI devices, both with SiO, and high-K. (Fie.11)
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temperatures. In fact, we observe that for similar gate stacks ( H Q on SiO,N, interface), ailer processing, FUSI gated devices show final equivalent thickness closer to poly-Si/ high-x while Me-gate stacks are electrically much thinner (Fig.12). One conventional way to scale the stack thinner is interface engineering which will need to be further optimized. , Conclusions We demonstrated high-perfoimance NiSiiHPji,O, NFET and PFET devices with: (i) sub-2 nm Ti”,,; (ii) 25 % performance gain over poly/Si02 at a given gate leakage; (iii) 6 to ,7 orders of gate leakage reduction (at a given T , d ; (iv) V, control for both NFET and PFET; and (v) negligible charge trapping.
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References 1. J. Kedzierski, D. Boyd, Y. Zhang, M. Steen, F.F. Jamin, J. Benedict, M. Ieong, and W. Haensch, “Issues in Nisi-gated FDSOI device integration” IEDM(2003) p.441; J. Kedzierski, D. Boyd, P. Ronsheim, S. Zafar, J. Newbuly, I. Ott, C. Cabral, M. Ieong, and W. Haensch, “Thrershold voltage control in Nisi-gated MOSFETSthrough silicidation induced impurity segregation (SIISY’ IEDM(2003) 0.315. 2. Z. krovokapic, W:i. Maszara, K. Achutan, P. King, I. Gray, M. Sidorow, E. Zhao, J. Zhang, J. Chan, A. Marathe, M.R. Lin, “Nickel silicide metal gate FDSOI devices with improved gate oxide leakage”, IEDM(2002) p. 271; W.P. Maczara, Z. Krivokapic, P. King, J.S. Goo, M.R. Lin, “Transistors with dual work function metal gates by single full silicidatioon (FUSI) of polysilicon gates”, IEDM(2002) p. 367. 3. C. Cabral, Jr., I. Kedzierski, B. Linder, S. Zafar, V. Narayanan, S. Fang, A. Steegen, P. Kozlowski, R. Carmthen ,and R. Jammy,” Dual workfunction fully silicided metal gates” VLSI (2004) p. 184. 4. K. G. Anil, A. Veloso, S. Kubicek, T. Schra$ E. Augendre, I. -F. de Mameffe, K. Devriend1;A. Lauwers, S. BNS, K. Henson, S. Biesemans, “Demonstration of fully Ni-silicided metal gates on HfD, based high-k gate dielectrics as a candidate for low power applications”, VLSI(2004) p.190. 5 . B. Tavel, T. Skotnicki, G. Pares, N. Carriere, M. Rivoire, F. Levered, C. Julien, J. Torres, R. Pantel, ‘Totally silicided (CoSiZ) polysilicon: a novel approach to vely low-resistive gate without metal CMP nor etching”, IEDM(2001) p.825. 6.C.Y. Lin,M.W. Ma,A. Chin, Y.C. Yeo,Z.Zhu,M.F.Li,D.L. Kwong, “ Fully silicided Nisi gate on La>O,MOSFETs”, IEEE EDL, 24 (2003) 348.
(2001) p. 45I. 8. V. Narayanan, A. Callegari, F.R. McFeely, K. Nakamura, P. Jamison, S. Zafar, E. Cartier, A. Steegen, V. Ku, P. Nguyen, K. Milkove, C. Cabral Jr., M. Gribelyuk, C . Wajda, Y.Kawano, D. Lacey, Y. Li, E. Sikorski, E. Duchl, H.Ng, C. Wann, R. Jammy, M. Ieong, G. Shahidi,” Dual work function metal gate CMOS using CVD metal electrodes” VLSI(2004) p.192. 9. Shanware, A.; Visokay, M.R.; Chambers, J.J.; Rotondaro, A.L.P.; McPherson, J.; Colombo, L, “Characterization and comparison of the charge trapping in HfSiON and HfOi gate dielectrics” IEDM(2003) p.38. IO. Z. Ren, M. Fischetti, E.P. Gusev, E. Cartier and M. Chudzik, “Inversion channel mobility in high-k high performance MOSFETs” IEDM(2003) p, 33.
Acknowledgement: Device processing support in the IBM MRL fabrication facility.
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Fig. 1. X-TEM image ofNiSi gate on HfQ. Columnar growth of Nisi grains with the size of greater than 50 nm can he seen. 34
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Fig. 4. Gate leakage current density as a function of inversion thickness. Gate leakage reductions due to the high-k layer and FWSI are illustrated by arrows. Dashed lines used for a guide only.
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